#include <linux/cpumask.h>
#include <asm/machvec.h>
#include <asm-generic/irq.h>
Go to the source code of this file.
#define irq_ctx_exit |
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cpu | ) |
do { } while (0) |
Definition at line 56 of file irq.h.
#define irq_ctx_init |
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cpu | ) |
do { } while (0) |
Definition at line 55 of file irq.h.
#define irq_demux |
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irq | ) |
sh_mv.mv_irq_demux(irq) |
Definition at line 43 of file irq.h.
#define irq_finish |
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irq | ) |
do { } while (0) |
Definition at line 64 of file irq.h.
#define irq_lookup |
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irq | ) |
(irq) |
Definition at line 63 of file irq.h.
#define NO_IRQ_IGNORE ((unsigned int)-1) |
Definition at line 24 of file irq.h.
Definition at line 15 of file irq.h.
The hexagon core comes with a first-level interrupt controller with 32 total possible interrupts. When the core is embedded into different systems/platforms, it is typically wrapped by macro cells that provide one or more second-level interrupt controllers that are cascaded into one or more of the first-level interrupts handled here. The precise wiring of these other irqs varies from platform to platform, and are set up & configured in the platform-specific files.
The first-level interrupt controller is wrapped by the VM, which virtualizes the interrupt controller for us. It provides a very simple, fast & efficient API, and so the fasteoi handler is appropriate for this case.
Definition at line 109 of file irq_alpha.c.
void make_imask_irq |
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unsigned int |
irq | ) |
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void make_maskreg_irq |
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unsigned int |
irq | ) |
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unsigned short* irq_mask_register |