Macros
#define	MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */

#define	MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */

#define	MMU_TTB 0xFFFFFFF8 /* Translation table base register */

#define	MMU_TEA 0xFFFFFFFC /* TLB Exception Address */

#define	MMUCR 0xFFFFFFE0 /* MMU Control Register */

#define	MMUCR_TI (1 << 2) /* TLB flush bit */

#define	MMU_TLB_ADDRESS_ARRAY 0xF2000000

#define	MMU_PAGE_ASSOC_BIT 0x80

#define	MMU_NTLB_ENTRIES 128 /* for 7708 */

#define	MMU_NTLB_WAYS 4

#define	MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */

#define	TRA 0xffffffd0

#define	EXPEVT 0xffffffd4

#define	INTEVT 0xffffffd8

Macro Definition Documentation

#define EXPEVT 0xffffffd4

Definition at line 29 of file mmu_context.h.

#define INTEVT 0xffffffd8

Definition at line 41 of file mmu_context.h.

#define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */

Definition at line 26 of file mmu_context.h.

#define MMU_NTLB_ENTRIES 128 /* for 7708 */

Definition at line 24 of file mmu_context.h.

#define MMU_NTLB_WAYS 4

Definition at line 25 of file mmu_context.h.

#define MMU_PAGE_ASSOC_BIT 0x80

Definition at line 22 of file mmu_context.h.

#define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */

Definition at line 13 of file mmu_context.h.

#define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */

Definition at line 14 of file mmu_context.h.

#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */

Definition at line 16 of file mmu_context.h.

#define MMU_TLB_ADDRESS_ARRAY 0xF2000000

Definition at line 21 of file mmu_context.h.

#define MMU_TTB 0xFFFFFFF8 /* Translation table base register */

Definition at line 15 of file mmu_context.h.

#define MMUCR 0xFFFFFFE0 /* MMU Control Register */

Definition at line 18 of file mmu_context.h.

#define MMUCR_TI (1 << 2) /* TLB flush bit */

Definition at line 19 of file mmu_context.h.

#define TRA 0xffffffd0

Definition at line 28 of file mmu_context.h.

Macros