#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel_stat.h>
#include <linux/uaccess.h>
#include <hv/drv_pcie_rc_intf.h>
#include <arch/spr_def.h>
#include <asm/traps.h>
Go to the source code of this file.
Definition at line 26 of file irq.c.
void ack_bad_irq |
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unsigned int |
irq | ) |
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DEFINE_PER_CPU |
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unsigned long |
long, |
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interrupts_enabled_mask |
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) |
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DEFINE_PER_CPU |
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irq_cpustat_t |
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irq_stat |
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) |
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Definition at line 40 of file irq.c.
EXPORT_PER_CPU_SYMBOL |
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interrupts_enabled_mask |
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The hexagon core comes with a first-level interrupt controller with 32 total possible interrupts. When the core is embedded into different systems/platforms, it is typically wrapped by macro cells that provide one or more second-level interrupt controllers that are cascaded into one or more of the first-level interrupts handled here. The precise wiring of these other irqs varies from platform to platform, and are set up & configured in the platform-specific files.
The first-level interrupt controller is wrapped by the VM, which virtualizes the interrupt controller for us. It provides a very simple, fast & efficient API, and so the fasteoi handler is appropriate for this case.
Definition at line 218 of file irq.c.
void tile_irq_activate |
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unsigned int |
irq, |
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int |
tile_irq_type |
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