irq.c File Reference

#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/random.h>
#include <linux/smp.h>
#include <linux/init.h>
#include <linux/seq_file.h>
#include <linux/errno.h>
#include <linux/list.h>
#include <linux/kallsyms.h>
#include <linux/proc_fs.h>
#include <linux/syscore_ops.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include "setup.h"

Go to the source code of this file.

Data Structures
struct	puv3_irq_state

Macros
#define	GPIO_MASK(irq)   (1 << (irq - IRQ_GPIO0))

Functions
	device_initcall (puv3_irq_init_syscore)
void __init	init_IRQ (void)
asmlinkage void	asm_do_IRQ (unsigned int irq, struct pt_regs *regs)

Macro Definition Documentation

#define GPIO_MASK

(

irq

)

(1 << (irq - IRQ_GPIO0))

Definition at line 42 of file irq.c.

Function Documentation

asmlinkage void asm_do_IRQ	(	unsigned int	irq,
		struct pt_regs *	regs
	)

Definition at line 355 of file irq.c.

device_initcall

(

puv3_irq_init_syscore

)

void __init init_IRQ

(

void

)

The hexagon core comes with a first-level interrupt controller with 32 total possible interrupts. When the core is embedded into different systems/platforms, it is typically wrapped by macro cells that provide one or more second-level interrupt controllers that are cascaded into one or more of the first-level interrupts handled here. The precise wiring of these other irqs varies from platform to platform, and are set up & configured in the platform-specific files.

The first-level interrupt controller is wrapped by the VM, which virtualizes the interrupt controller for us. It provides a very simple, fast & efficient API, and so the fasteoi handler is appropriate for this case.

Definition at line 295 of file irq.c.