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Macros
barrier.h File Reference
#include <asm/alternative.h>
#include <asm/nops.h>

Go to the source code of this file.

Macros

#define mb()   asm volatile("mfence":::"memory")
 
#define rmb()   asm volatile("lfence":::"memory")
 
#define wmb()   asm volatile("sfence" ::: "memory")
 
#define read_barrier_depends()   do { } while (0)
 
#define smp_mb()   barrier()
 
#define smp_rmb()   barrier()
 
#define smp_wmb()   barrier()
 
#define smp_read_barrier_depends()   do { } while (0)
 
#define set_mb(var, value)   do { var = value; barrier(); } while (0)
 

Macro Definition Documentation

#define mb (   void)    asm volatile("mfence":::"memory")

Definition at line 22 of file barrier.h.

#define read_barrier_depends ( )    do { } while (0)

read_barrier_depends - Flush all pending reads that subsequents reads depend on.

No data-dependent reads from memory-like regions are ever reordered over this barrier. All reads preceding this primitive are guaranteed to access memory (but not necessarily other CPUs' caches) before any reads following this primitive that depend on the data return by any of the preceding reads. This primitive is much lighter weight than rmb() on most CPUs, and is never heavier weight than is rmb().

These ordering constraints are respected by both the local CPU and the compiler.

Ordering is not guaranteed by anything other than these primitives, not even by data dependencies. See the documentation for memory_barrier() for examples and URLs to more information.

For example, the following code would force ordering (the initial value of "a" is zero, "b" is one, and "p" is "&a"):

<programlisting> CPU 0 CPU 1

b = 2; memory_barrier(); p = q = p; read_barrier_depends(); d = *q; </programlisting>

because the read of "*q" depends on the read of "p" and these two reads are separated by a read_barrier_depends(). However, the following code, with the same initial values for "a" and "b":

<programlisting> CPU 0 CPU 1

a = 2; memory_barrier(); b = 3; y = b; read_barrier_depends(); x = a; </programlisting>

does not enforce ordering, since there is no data dependency between the read of "a" and the read of "b". Therefore, on some CPUs, such as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() in cases like this where there are no data dependencies.

Definition at line 79 of file barrier.h.

#define rmb ( )    asm volatile("lfence":::"memory")

Definition at line 23 of file barrier.h.

#define set_mb (   var,
  value 
)    do { var = value; barrier(); } while (0)

Definition at line 100 of file barrier.h.

#define smp_mb ( )    barrier()

Definition at line 96 of file barrier.h.

#define smp_read_barrier_depends ( )    do { } while (0)

Definition at line 99 of file barrier.h.

#define smp_rmb ( )    barrier()

Definition at line 97 of file barrier.h.

#define smp_wmb ( )    barrier()

Definition at line 98 of file barrier.h.

#define wmb ( )    asm volatile("sfence" ::: "memory")

Definition at line 24 of file barrier.h.