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barrier.h
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1 #ifndef _ASM_X86_BARRIER_H
2 #define _ASM_X86_BARRIER_H
3 
4 #include <asm/alternative.h>
5 #include <asm/nops.h>
6 
7 /*
8  * Force strict CPU ordering.
9  * And yes, this is required on UP too when we're talking
10  * to devices.
11  */
12 
13 #ifdef CONFIG_X86_32
14 /*
15  * Some non-Intel clones support out of order store. wmb() ceases to be a
16  * nop for these.
17  */
18 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
19 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
20 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
21 #else
22 #define mb() asm volatile("mfence":::"memory")
23 #define rmb() asm volatile("lfence":::"memory")
24 #define wmb() asm volatile("sfence" ::: "memory")
25 #endif
26 
79 #define read_barrier_depends() do { } while (0)
80 
81 #ifdef CONFIG_SMP
82 #define smp_mb() mb()
83 #ifdef CONFIG_X86_PPRO_FENCE
84 # define smp_rmb() rmb()
85 #else
86 # define smp_rmb() barrier()
87 #endif
88 #ifdef CONFIG_X86_OOSTORE
89 # define smp_wmb() wmb()
90 #else
91 # define smp_wmb() barrier()
92 #endif
93 #define smp_read_barrier_depends() read_barrier_depends()
94 #define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
95 #else
96 #define smp_mb() barrier()
97 #define smp_rmb() barrier()
98 #define smp_wmb() barrier()
99 #define smp_read_barrier_depends() do { } while (0)
100 #define set_mb(var, value) do { var = value; barrier(); } while (0)
101 #endif
102 
103 /*
104  * Stop RDTSC speculation. This is needed when you need to use RDTSC
105  * (or get_cycles or vread that possibly accesses the TSC) in a defined
106  * code region.
107  *
108  * (Could use an alternative three way for this if there was one.)
109  */
110 static __always_inline void rdtsc_barrier(void)
111 {
114 }
115 
116 #endif /* _ASM_X86_BARRIER_H */