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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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#include <asm/required-features.h>Go to the source code of this file.
Macros | |
| #define | NCAPINTS 10 /* N 32-bit words worth of info */ |
| #define | X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ |
| #define | X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */ |
| #define | X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ |
| #define | X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ |
| #define | X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */ |
| #define | X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers */ |
| #define | X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ |
| #define | X86_FEATURE_MCE (0*32+ 7) /* Machine Check Exception */ |
| #define | X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ |
| #define | X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */ |
| #define | X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */ |
| #define | X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */ |
| #define | X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ |
| #define | X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ |
| #define | X86_FEATURE_CMOV (0*32+15) /* CMOV instructions */ |
| #define | X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ |
| #define | X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ |
| #define | X86_FEATURE_PN (0*32+18) /* Processor serial number */ |
| #define | X86_FEATURE_CLFLSH (0*32+19) /* "clflush" CLFLUSH instruction */ |
| #define | X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */ |
| #define | X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ |
| #define | X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ |
| #define | X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ |
| #define | X86_FEATURE_XMM (0*32+25) /* "sse" */ |
| #define | X86_FEATURE_XMM2 (0*32+26) /* "sse2" */ |
| #define | X86_FEATURE_SELFSNOOP (0*32+27) /* "ss" CPU self snoop */ |
| #define | X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ |
| #define | X86_FEATURE_ACC (0*32+29) /* "tm" Automatic clock control */ |
| #define | X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */ |
| #define | X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */ |
| #define | X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */ |
| #define | X86_FEATURE_MP (1*32+19) /* MP Capable. */ |
| #define | X86_FEATURE_NX (1*32+20) /* Execute Disable */ |
| #define | X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ |
| #define | X86_FEATURE_FXSR_OPT (1*32+25) /* FXSAVE/FXRSTOR optimizations */ |
| #define | X86_FEATURE_GBPAGES (1*32+26) /* "pdpe1gb" GB pages */ |
| #define | X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */ |
| #define | X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ |
| #define | X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ |
| #define | X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ |
| #define | X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */ |
| #define | X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */ |
| #define | X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */ |
| #define | X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */ |
| #define | X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ |
| #define | X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ |
| #define | X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ |
| #define | X86_FEATURE_K8 (3*32+ 4) /* "" Opteron, Athlon64 */ |
| #define | X86_FEATURE_K7 (3*32+ 5) /* "" Athlon */ |
| #define | X86_FEATURE_P3 (3*32+ 6) /* "" P3 */ |
| #define | X86_FEATURE_P4 (3*32+ 7) /* "" P4 */ |
| #define | X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */ |
| #define | X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ |
| #define | X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */ |
| #define | X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ |
| #define | X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ |
| #define | X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ |
| #define | X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */ |
| #define | X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in ia32 userspace */ |
| #define | X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */ |
| #define | X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */ |
| #define | X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */ |
| #define | X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */ |
| #define | X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ |
| #define | X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ |
| #define | X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */ |
| #define | X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */ |
| #define | X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */ |
| #define | X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */ |
| #define | X86_FEATURE_AMD_DCM (3*32+27) /* multi-node processor */ |
| #define | X86_FEATURE_APERFMPERF (3*32+28) /* APERFMPERF */ |
| #define | X86_FEATURE_EAGER_FPU (3*32+29) /* "eagerfpu" Non lazy FPU restore */ |
| #define | X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ |
| #define | X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */ |
| #define | X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */ |
| #define | X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */ |
| #define | X86_FEATURE_DSCPL (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ |
| #define | X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */ |
| #define | X86_FEATURE_SMX (4*32+ 6) /* Safer mode */ |
| #define | X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ |
| #define | X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ |
| #define | X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */ |
| #define | X86_FEATURE_CID (4*32+10) /* Context ID */ |
| #define | X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */ |
| #define | X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ |
| #define | X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ |
| #define | X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */ |
| #define | X86_FEATURE_PCID (4*32+17) /* Process Context Identifiers */ |
| #define | X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ |
| #define | X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */ |
| #define | X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */ |
| #define | X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ |
| #define | X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */ |
| #define | X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */ |
| #define | X86_FEATURE_TSC_DEADLINE_TIMER (4*32+24) /* Tsc deadline timer */ |
| #define | X86_FEATURE_AES (4*32+25) /* AES instructions */ |
| #define | X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ |
| #define | X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ |
| #define | X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ |
| #define | X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */ |
| #define | X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */ |
| #define | X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */ |
| #define | X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */ |
| #define | X86_FEATURE_XSTORE_EN (5*32+ 3) /* "rng_en" RNG enabled */ |
| #define | X86_FEATURE_XCRYPT (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ |
| #define | X86_FEATURE_XCRYPT_EN (5*32+ 7) /* "ace_en" on-CPU crypto enabled */ |
| #define | X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */ |
| #define | X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */ |
| #define | X86_FEATURE_PHE (5*32+10) /* PadLock Hash Engine */ |
| #define | X86_FEATURE_PHE_EN (5*32+11) /* PHE enabled */ |
| #define | X86_FEATURE_PMM (5*32+12) /* PadLock Montgomery Multiplier */ |
| #define | X86_FEATURE_PMM_EN (5*32+13) /* PMM enabled */ |
| #define | X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ |
| #define | X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ |
| #define | X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */ |
| #define | X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */ |
| #define | X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */ |
| #define | X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */ |
| #define | X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */ |
| #define | X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */ |
| #define | X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */ |
| #define | X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */ |
| #define | X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */ |
| #define | X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */ |
| #define | X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */ |
| #define | X86_FEATURE_WDT (6*32+13) /* Watchdog timer */ |
| #define | X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */ |
| #define | X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */ |
| #define | X86_FEATURE_TCE (6*32+17) /* translation cache extension */ |
| #define | X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */ |
| #define | X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */ |
| #define | X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */ |
| #define | X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */ |
| #define | X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ |
| #define | X86_FEATURE_ARAT (7*32+ 1) /* Always Running APIC Timer */ |
| #define | X86_FEATURE_CPB (7*32+ 2) /* AMD Core Performance Boost */ |
| #define | X86_FEATURE_EPB (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ |
| #define | X86_FEATURE_XSAVEOPT (7*32+ 4) /* Optimized Xsave */ |
| #define | X86_FEATURE_PLN (7*32+ 5) /* Intel Power Limit Notification */ |
| #define | X86_FEATURE_PTS (7*32+ 6) /* Intel Package Thermal Status */ |
| #define | X86_FEATURE_DTHERM (7*32+ 7) /* Digital Thermal Sensor */ |
| #define | X86_FEATURE_HW_PSTATE (7*32+ 8) /* AMD HW-PState */ |
| #define | X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */ |
| #define | X86_FEATURE_VNMI (8*32+ 1) /* Intel Virtual NMI */ |
| #define | X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */ |
| #define | X86_FEATURE_EPT (8*32+ 3) /* Intel Extended Page Table */ |
| #define | X86_FEATURE_VPID (8*32+ 4) /* Intel Virtual Processor ID */ |
| #define | X86_FEATURE_NPT (8*32+ 5) /* AMD Nested Page Table support */ |
| #define | X86_FEATURE_LBRV (8*32+ 6) /* AMD LBR Virtualization support */ |
| #define | X86_FEATURE_SVML (8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ |
| #define | X86_FEATURE_NRIPS (8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ |
| #define | X86_FEATURE_TSCRATEMSR (8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ |
| #define | X86_FEATURE_VMCBCLEAN (8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */ |
| #define | X86_FEATURE_FLUSHBYASID (8*32+11) /* AMD flush-by-ASID support */ |
| #define | X86_FEATURE_DECODEASSISTS (8*32+12) /* AMD Decode Assists support */ |
| #define | X86_FEATURE_PAUSEFILTER (8*32+13) /* AMD filtered pause intercept */ |
| #define | X86_FEATURE_PFTHRESHOLD (8*32+14) /* AMD pause filter threshold */ |
| #define | X86_FEATURE_FSGSBASE (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ |
| #define | X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */ |
| #define | X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */ |
| #define | X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */ |
| #define | X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */ |
| #define | X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */ |
| #define | X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ |
| #define | X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */ |
| #define | X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */ |
| #define | X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */ |
| #define | X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */ |
| #define | X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */ |
Definition at line 11 of file cpufeature.h.
| #define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */ |
Definition at line 92 of file cpufeature.h.
| #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ |
Definition at line 63 of file cpufeature.h.
| #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ |
Definition at line 62 of file cpufeature.h.
| #define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */ |
Definition at line 157 of file cpufeature.h.
| #define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */ |
Definition at line 154 of file cpufeature.h.
Definition at line 48 of file cpufeature.h.
| #define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */ |
Definition at line 141 of file cpufeature.h.
Definition at line 142 of file cpufeature.h.
| #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ |
Definition at line 41 of file cpufeature.h.
Definition at line 214 of file cpufeature.h.
| #define X86_FEATURE_AES (4*32+25) /* AES instructions */ |
Definition at line 128 of file cpufeature.h.
Definition at line 100 of file cpufeature.h.
| #define X86_FEATURE_APERFMPERF (3*32+28) /* APERFMPERF */ |
Definition at line 101 of file cpufeature.h.
| #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */ |
Definition at line 29 of file cpufeature.h.
Definition at line 176 of file cpufeature.h.
| #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ |
Definition at line 84 of file cpufeature.h.
| #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ |
Definition at line 131 of file cpufeature.h.
| #define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */ |
Definition at line 207 of file cpufeature.h.
| #define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */ |
Definition at line 205 of file cpufeature.h.
| #define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */ |
Definition at line 209 of file cpufeature.h.
| #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ |
Definition at line 86 of file cpufeature.h.
| #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ |
Definition at line 75 of file cpufeature.h.
| #define X86_FEATURE_CID (4*32+10) /* Context ID */ |
Definition at line 115 of file cpufeature.h.
| #define X86_FEATURE_CLFLSH (0*32+19) /* "clflush" CLFLUSH instruction */ |
Definition at line 39 of file cpufeature.h.
| #define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */ |
Definition at line 98 of file cpufeature.h.
| #define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions */ |
Definition at line 34 of file cpufeature.h.
Definition at line 150 of file cpufeature.h.
Definition at line 81 of file cpufeature.h.
| #define X86_FEATURE_CPB (7*32+ 2) /* AMD Core Performance Boost */ |
Definition at line 177 of file cpufeature.h.
Definition at line 153 of file cpufeature.h.
| #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ |
Definition at line 117 of file cpufeature.h.
| #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ |
Definition at line 28 of file cpufeature.h.
| #define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */ |
Definition at line 72 of file cpufeature.h.
| #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ |
Definition at line 74 of file cpufeature.h.
| #define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ |
Definition at line 121 of file cpufeature.h.
| #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ |
Definition at line 22 of file cpufeature.h.
| #define X86_FEATURE_DECODEASSISTS (8*32+12) /* AMD Decode Assists support */ |
Definition at line 198 of file cpufeature.h.
| #define X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */ |
Definition at line 40 of file cpufeature.h.
| #define X86_FEATURE_DSCPL (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ |
Definition at line 109 of file cpufeature.h.
| #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */ |
Definition at line 107 of file cpufeature.h.
| #define X86_FEATURE_DTHERM (7*32+ 7) /* Digital Thermal Sensor */ |
Definition at line 182 of file cpufeature.h.
| #define X86_FEATURE_EAGER_FPU (3*32+29) /* "eagerfpu" Non lazy FPU restore */ |
Definition at line 102 of file cpufeature.h.
| #define X86_FEATURE_EPB (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ |
Definition at line 178 of file cpufeature.h.
| #define X86_FEATURE_EPT (8*32+ 3) /* Intel Extended Page Table */ |
Definition at line 189 of file cpufeature.h.
| #define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ |
Definition at line 210 of file cpufeature.h.
| #define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ |
Definition at line 112 of file cpufeature.h.
| #define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */ |
Definition at line 152 of file cpufeature.h.
| #define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */ |
Definition at line 99 of file cpufeature.h.
Definition at line 132 of file cpufeature.h.
| #define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */ |
Definition at line 188 of file cpufeature.h.
Definition at line 197 of file cpufeature.h.
| #define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */ |
Definition at line 116 of file cpufeature.h.
| #define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */ |
Definition at line 164 of file cpufeature.h.
| #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ |
Definition at line 20 of file cpufeature.h.
Definition at line 204 of file cpufeature.h.
| #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */ |
Definition at line 83 of file cpufeature.h.
| #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ |
Definition at line 43 of file cpufeature.h.
| #define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSAVE/FXRSTOR optimizations */ |
Definition at line 58 of file cpufeature.h.
| #define X86_FEATURE_GBPAGES (1*32+26) /* "pdpe1gb" GB pages */ |
Definition at line 59 of file cpufeature.h.
| #define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */ |
Definition at line 206 of file cpufeature.h.
| #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ |
Definition at line 47 of file cpufeature.h.
| #define X86_FEATURE_HW_PSTATE (7*32+ 8) /* AMD HW-PState */ |
Definition at line 183 of file cpufeature.h.
Definition at line 134 of file cpufeature.h.
| #define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */ |
Definition at line 49 of file cpufeature.h.
| #define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */ |
Definition at line 159 of file cpufeature.h.
| #define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ |
Definition at line 175 of file cpufeature.h.
| #define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */ |
Definition at line 211 of file cpufeature.h.
| #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ |
Definition at line 73 of file cpufeature.h.
| #define X86_FEATURE_K7 (3*32+ 5) /* "" Athlon */ |
Definition at line 78 of file cpufeature.h.
| #define X86_FEATURE_K8 (3*32+ 4) /* "" Opteron, Athlon64 */ |
Definition at line 77 of file cpufeature.h.
Definition at line 149 of file cpufeature.h.
Definition at line 192 of file cpufeature.h.
| #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */ |
Definition at line 91 of file cpufeature.h.
Definition at line 61 of file cpufeature.h.
| #define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */ |
Definition at line 67 of file cpufeature.h.
Definition at line 68 of file cpufeature.h.
| #define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */ |
Definition at line 163 of file cpufeature.h.
| #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ |
Definition at line 33 of file cpufeature.h.
| #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Exception */ |
Definition at line 27 of file cpufeature.h.
| #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */ |
Definition at line 90 of file cpufeature.h.
Definition at line 156 of file cpufeature.h.
| #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ |
Definition at line 42 of file cpufeature.h.
| #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ |
Definition at line 57 of file cpufeature.h.
| #define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */ |
Definition at line 125 of file cpufeature.h.
| #define X86_FEATURE_MP (1*32+19) /* MP Capable. */ |
Definition at line 55 of file cpufeature.h.
| #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers */ |
Definition at line 25 of file cpufeature.h.
Definition at line 31 of file cpufeature.h.
| #define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */ |
Definition at line 108 of file cpufeature.h.
| #define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */ |
Definition at line 166 of file cpufeature.h.
Definition at line 97 of file cpufeature.h.
| #define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ |
Definition at line 93 of file cpufeature.h.
| #define X86_FEATURE_NPT (8*32+ 5) /* AMD Nested Page Table support */ |
Definition at line 191 of file cpufeature.h.
| #define X86_FEATURE_NRIPS (8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ |
Definition at line 194 of file cpufeature.h.
| #define X86_FEATURE_NX (1*32+20) /* Execute Disable */ |
Definition at line 56 of file cpufeature.h.
| #define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */ |
Definition at line 158 of file cpufeature.h.
Definition at line 130 of file cpufeature.h.
| #define X86_FEATURE_P3 (3*32+ 6) /* "" P3 */ |
Definition at line 79 of file cpufeature.h.
| #define X86_FEATURE_P4 (3*32+ 7) /* "" P4 */ |
Definition at line 80 of file cpufeature.h.
| #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ |
Definition at line 26 of file cpufeature.h.
| #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ |
Definition at line 36 of file cpufeature.h.
| #define X86_FEATURE_PAUSEFILTER (8*32+13) /* AMD filtered pause intercept */ |
Definition at line 199 of file cpufeature.h.
| #define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */ |
Definition at line 50 of file cpufeature.h.
| #define X86_FEATURE_PCID (4*32+17) /* Process Context Identifiers */ |
Definition at line 120 of file cpufeature.h.
| #define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */ |
Definition at line 106 of file cpufeature.h.
| #define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */ |
Definition at line 119 of file cpufeature.h.
| #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ |
Definition at line 85 of file cpufeature.h.
| #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */ |
Definition at line 169 of file cpufeature.h.
Definition at line 200 of file cpufeature.h.
| #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ |
Definition at line 32 of file cpufeature.h.
| #define X86_FEATURE_PHE (5*32+10) /* PadLock Hash Engine */ |
Definition at line 143 of file cpufeature.h.
| #define X86_FEATURE_PHE_EN (5*32+11) /* PHE enabled */ |
Definition at line 144 of file cpufeature.h.
| #define X86_FEATURE_PLN (7*32+ 5) /* Intel Power Limit Notification */ |
Definition at line 180 of file cpufeature.h.
| #define X86_FEATURE_PMM (5*32+12) /* PadLock Montgomery Multiplier */ |
Definition at line 145 of file cpufeature.h.
| #define X86_FEATURE_PMM_EN (5*32+13) /* PMM enabled */ |
Definition at line 146 of file cpufeature.h.
Definition at line 38 of file cpufeature.h.
| #define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */ |
Definition at line 126 of file cpufeature.h.
| #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ |
Definition at line 23 of file cpufeature.h.
| #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ |
Definition at line 37 of file cpufeature.h.
Definition at line 181 of file cpufeature.h.
| #define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */ |
Definition at line 133 of file cpufeature.h.
| #define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */ |
Definition at line 213 of file cpufeature.h.
| #define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */ |
Definition at line 60 of file cpufeature.h.
Definition at line 66 of file cpufeature.h.
Definition at line 89 of file cpufeature.h.
| #define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */ |
Definition at line 212 of file cpufeature.h.
| #define X86_FEATURE_SELFSNOOP (0*32+27) /* "ss" CPU self snoop */ |
Definition at line 46 of file cpufeature.h.
| #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */ |
Definition at line 30 of file cpufeature.h.
| #define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */ |
Definition at line 161 of file cpufeature.h.
Definition at line 215 of file cpufeature.h.
| #define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */ |
Definition at line 208 of file cpufeature.h.
| #define X86_FEATURE_SMX (4*32+ 6) /* Safer mode */ |
Definition at line 111 of file cpufeature.h.
| #define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */ |
Definition at line 155 of file cpufeature.h.
| #define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */ |
Definition at line 114 of file cpufeature.h.
| #define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */ |
Definition at line 151 of file cpufeature.h.
| #define X86_FEATURE_SVML (8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ |
Definition at line 193 of file cpufeature.h.
| #define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */ |
Definition at line 54 of file cpufeature.h.
Definition at line 87 of file cpufeature.h.
Definition at line 88 of file cpufeature.h.
| #define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */ |
Definition at line 167 of file cpufeature.h.
| #define X86_FEATURE_TCE (6*32+17) /* translation cache extension */ |
Definition at line 165 of file cpufeature.h.
| #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ |
Definition at line 113 of file cpufeature.h.
| #define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */ |
Definition at line 168 of file cpufeature.h.
| #define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */ |
Definition at line 186 of file cpufeature.h.
Definition at line 24 of file cpufeature.h.
| #define X86_FEATURE_TSC_DEADLINE_TIMER (4*32+24) /* Tsc deadline timer */ |
Definition at line 127 of file cpufeature.h.
| #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */ |
Definition at line 96 of file cpufeature.h.
| #define X86_FEATURE_TSCRATEMSR (8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ |
Definition at line 195 of file cpufeature.h.
Definition at line 82 of file cpufeature.h.
Definition at line 196 of file cpufeature.h.
| #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */ |
Definition at line 21 of file cpufeature.h.
| #define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */ |
Definition at line 110 of file cpufeature.h.
| #define X86_FEATURE_VNMI (8*32+ 1) /* Intel Virtual NMI */ |
Definition at line 187 of file cpufeature.h.
| #define X86_FEATURE_VPID (8*32+ 4) /* Intel Virtual Processor ID */ |
Definition at line 190 of file cpufeature.h.
| #define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */ |
Definition at line 162 of file cpufeature.h.
| #define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ |
Definition at line 124 of file cpufeature.h.
| #define X86_FEATURE_XCRYPT (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ |
Definition at line 139 of file cpufeature.h.
Definition at line 140 of file cpufeature.h.
| #define X86_FEATURE_XMM (0*32+25) /* "sse" */ |
Definition at line 44 of file cpufeature.h.
| #define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */ |
Definition at line 45 of file cpufeature.h.
| #define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ |
Definition at line 105 of file cpufeature.h.
| #define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */ |
Definition at line 122 of file cpufeature.h.
| #define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */ |
Definition at line 123 of file cpufeature.h.
| #define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */ |
Definition at line 160 of file cpufeature.h.
| #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ |
Definition at line 129 of file cpufeature.h.
| #define X86_FEATURE_XSAVEOPT (7*32+ 4) /* Optimized Xsave */ |
Definition at line 179 of file cpufeature.h.
| #define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */ |
Definition at line 137 of file cpufeature.h.
| #define X86_FEATURE_XSTORE_EN (5*32+ 3) /* "rng_en" RNG enabled */ |
Definition at line 138 of file cpufeature.h.
| #define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ |
Definition at line 95 of file cpufeature.h.
| #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ |
Definition at line 118 of file cpufeature.h.
1.8.2