#include <linux/platform_data/dma-atmel.h>

Data Structures
struct	at_lli

struct	at_desc

struct	at_dma_chan

struct	at_dma

Macros
#define	AT_DMA_MAX_NR_CHANNELS 8

#define	AT_DMA_GCFG 0x00 /* Global Configuration Register */

#define	AT_DMA_IF_BIGEND(i) (0x1 << (i)) /* AHB-Lite Interface i in Big-endian mode */

#define	AT_DMA_ARB_CFG (0x1 << 4) /* Arbiter mode. */

#define	AT_DMA_ARB_CFG_FIXED (0x0 << 4)

#define	AT_DMA_ARB_CFG_ROUND_ROBIN (0x1 << 4)

#define	AT_DMA_EN 0x04 /* Controller Enable Register */

#define	AT_DMA_ENABLE (0x1 << 0)

#define	AT_DMA_SREQ 0x08 /* Software Single Request Register */

#define	AT_DMA_SSREQ(x) (0x1 << ((x) << 1)) /* Request a source single transfer on channel x */

#define	AT_DMA_DSREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination single transfer on channel x */

#define	AT_DMA_CREQ 0x0C /* Software Chunk Transfer Request Register */

#define	AT_DMA_SCREQ(x) (0x1 << ((x) << 1)) /* Request a source chunk transfer on channel x */

#define	AT_DMA_DCREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination chunk transfer on channel x */

#define	AT_DMA_LAST 0x10 /* Software Last Transfer Flag Register */

#define	AT_DMA_SLAST(x) (0x1 << ((x) << 1)) /* This src rq is last tx of buffer on channel x */

#define	AT_DMA_DLAST(x) (0x1 << (1 + ((x) << 1))) /* This dst rq is last tx of buffer on channel x */

#define	AT_DMA_SYNC 0x14 /* Request Synchronization Register */

#define	AT_DMA_SYR(h) (0x1 << (h)) /* Synchronize handshake line h */

#define	AT_DMA_EBCIER 0x18 /* Enable register */

#define	AT_DMA_EBCIDR 0x1C /* Disable register */

#define	AT_DMA_EBCIMR 0x20 /* Mask Register */

#define	AT_DMA_EBCISR 0x24 /* Status Register */

#define	AT_DMA_CBTC_OFFSET 8

#define	AT_DMA_ERR_OFFSET 16

#define	AT_DMA_BTC(x) (0x1 << (x))

#define	AT_DMA_CBTC(x) (0x1 << (AT_DMA_CBTC_OFFSET + (x)))

#define	AT_DMA_ERR(x) (0x1 << (AT_DMA_ERR_OFFSET + (x)))

#define	AT_DMA_CHER 0x28 /* Channel Handler Enable Register */

#define	AT_DMA_ENA(x) (0x1 << (x))

#define	AT_DMA_SUSP(x) (0x1 << ( 8 + (x)))

#define	AT_DMA_KEEP(x) (0x1 << (24 + (x)))

#define	AT_DMA_CHDR 0x2C /* Channel Handler Disable Register */

#define	AT_DMA_DIS(x) (0x1 << (x))

#define	AT_DMA_RES(x) (0x1 << ( 8 + (x)))

#define	AT_DMA_CHSR 0x30 /* Channel Handler Status Register */

#define	AT_DMA_EMPT(x) (0x1 << (16 + (x)))

#define	AT_DMA_STAL(x) (0x1 << (24 + (x)))

#define	AT_DMA_CH_REGS_BASE 0x3C /* Channel registers base address */

#define	ch_regs(x) (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */

#define	ATC_SADDR_OFFSET 0x00 /* Source Address Register */

#define	ATC_DADDR_OFFSET 0x04 /* Destination Address Register */

#define	ATC_DSCR_OFFSET 0x08 /* Descriptor Address Register */

#define	ATC_CTRLA_OFFSET 0x0C /* Control A Register */

#define	ATC_CTRLB_OFFSET 0x10 /* Control B Register */

#define	ATC_CFG_OFFSET 0x14 /* Configuration Register */

#define	ATC_SPIP_OFFSET 0x18 /* Src PIP Configuration Register */

#define	ATC_DPIP_OFFSET 0x1C /* Dst PIP Configuration Register */

#define	ATC_DSCR_IF(i) (0x3 & (i)) /* Dsc feched via AHB-Lite Interface i */

#define	ATC_BTSIZE_MAX 0xFFFFUL /* Maximum Buffer Transfer Size */

#define	ATC_BTSIZE(x) (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */

#define	ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */

#define	ATC_SCSIZE(x) (ATC_SCSIZE_MASK & ((x) << 16))

#define	ATC_SCSIZE_1 (0x0 << 16)

#define	ATC_SCSIZE_4 (0x1 << 16)

#define	ATC_SCSIZE_8 (0x2 << 16)

#define	ATC_SCSIZE_16 (0x3 << 16)

#define	ATC_SCSIZE_32 (0x4 << 16)

#define	ATC_SCSIZE_64 (0x5 << 16)

#define	ATC_SCSIZE_128 (0x6 << 16)

#define	ATC_SCSIZE_256 (0x7 << 16)

#define	ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */

#define	ATC_DCSIZE(x) (ATC_DCSIZE_MASK & ((x) << 20))

#define	ATC_DCSIZE_1 (0x0 << 20)

#define	ATC_DCSIZE_4 (0x1 << 20)

#define	ATC_DCSIZE_8 (0x2 << 20)

#define	ATC_DCSIZE_16 (0x3 << 20)

#define	ATC_DCSIZE_32 (0x4 << 20)

#define	ATC_DCSIZE_64 (0x5 << 20)

#define	ATC_DCSIZE_128 (0x6 << 20)

#define	ATC_DCSIZE_256 (0x7 << 20)

#define	ATC_SRC_WIDTH_MASK (0x3 << 24) /* Source Single Transfer Size */

#define	ATC_SRC_WIDTH(x) ((x) << 24)

#define	ATC_SRC_WIDTH_BYTE (0x0 << 24)

#define	ATC_SRC_WIDTH_HALFWORD (0x1 << 24)

#define	ATC_SRC_WIDTH_WORD (0x2 << 24)

#define	ATC_DST_WIDTH_MASK (0x3 << 28) /* Destination Single Transfer Size */

#define	ATC_DST_WIDTH(x) ((x) << 28)

#define	ATC_DST_WIDTH_BYTE (0x0 << 28)

#define	ATC_DST_WIDTH_HALFWORD (0x1 << 28)

#define	ATC_DST_WIDTH_WORD (0x2 << 28)

#define	ATC_DONE (0x1 << 31) /* Tx Done (only written back in descriptor) */

#define	ATC_SIF(i) (0x3 & (i)) /* Src tx done via AHB-Lite Interface i */

#define	ATC_DIF(i) ((0x3 & (i)) << 4) /* Dst tx done via AHB-Lite Interface i */

#define	AT_DMA_MEM_IF 0 /* interface 0 as memory interface */

#define	AT_DMA_PER_IF 1 /* interface 1 as peripheral interface */

#define	ATC_SRC_PIP (0x1 << 8) /* Source Picture-in-Picture enabled */

#define	ATC_DST_PIP (0x1 << 12) /* Destination Picture-in-Picture enabled */

#define	ATC_SRC_DSCR_DIS (0x1 << 16) /* Src Descriptor fetch disable */

#define	ATC_DST_DSCR_DIS (0x1 << 20) /* Dst Descriptor fetch disable */

#define	ATC_FC_MASK (0x7 << 21) /* Choose Flow Controller */

#define	ATC_FC_MEM2MEM (0x0 << 21) /* Mem-to-Mem (DMA) */

#define	ATC_FC_MEM2PER (0x1 << 21) /* Mem-to-Periph (DMA) */

#define	ATC_FC_PER2MEM (0x2 << 21) /* Periph-to-Mem (DMA) */

#define	ATC_FC_PER2PER (0x3 << 21) /* Periph-to-Periph (DMA) */

#define	ATC_FC_PER2MEM_PER (0x4 << 21) /* Periph-to-Mem (Peripheral) */

#define	ATC_FC_MEM2PER_PER (0x5 << 21) /* Mem-to-Periph (Peripheral) */

#define	ATC_FC_PER2PER_SRCPER (0x6 << 21) /* Periph-to-Periph (Src Peripheral) */

#define	ATC_FC_PER2PER_DSTPER (0x7 << 21) /* Periph-to-Periph (Dst Peripheral) */

#define	ATC_SRC_ADDR_MODE_MASK (0x3 << 24)

#define	ATC_SRC_ADDR_MODE_INCR (0x0 << 24) /* Incrementing Mode */

#define	ATC_SRC_ADDR_MODE_DECR (0x1 << 24) /* Decrementing Mode */

#define	ATC_SRC_ADDR_MODE_FIXED (0x2 << 24) /* Fixed Mode */

#define	ATC_DST_ADDR_MODE_MASK (0x3 << 28)

#define	ATC_DST_ADDR_MODE_INCR (0x0 << 28) /* Incrementing Mode */

#define	ATC_DST_ADDR_MODE_DECR (0x1 << 28) /* Decrementing Mode */

#define	ATC_DST_ADDR_MODE_FIXED (0x2 << 28) /* Fixed Mode */

#define	ATC_IEN (0x1 << 30) /* BTC interrupt enable (active low) */

#define	ATC_AUTO (0x1 << 31) /* Auto multiple buffer tx enable */

#define	ATC_SPIP_HOLE(x) (0xFFFFU & (x))

#define	ATC_SPIP_BOUNDARY(x) ((0x3FF & (x)) << 16)

#define	ATC_DPIP_HOLE(x) (0xFFFFU & (x))

#define	ATC_DPIP_BOUNDARY(x) ((0x3FF & (x)) << 16)

#define	channel_readl(atchan, name) __raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)

#define	channel_writel(atchan, name, val) __raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)

#define	dma_readl(atdma, name) __raw_readl((atdma)->regs + AT_DMA_##name)

#define	dma_writel(atdma, name, val) __raw_writel((val), (atdma)->regs + AT_DMA_##name)

Enumerations
enum	atc_status { ATC_IS_ERROR = 0, ATC_IS_PAUSED = 1, ATC_IS_CYCLIC = 24 }

Macro Definition Documentation

#define AT_DMA_ARB_CFG (0x1 << 4) /* Arbiter mode. */

Definition at line 21 of file at_hdmac_regs.h.

#define AT_DMA_ARB_CFG_FIXED (0x0 << 4)

Definition at line 22 of file at_hdmac_regs.h.

#define AT_DMA_ARB_CFG_ROUND_ROBIN (0x1 << 4)

Definition at line 23 of file at_hdmac_regs.h.

#define AT_DMA_BTC ( x ) (0x1 << (x))

Definition at line 50 of file at_hdmac_regs.h.

#define AT_DMA_CBTC ( x ) (0x1 << (AT_DMA_CBTC_OFFSET + (x)))

Definition at line 51 of file at_hdmac_regs.h.

#define AT_DMA_CBTC_OFFSET 8

Definition at line 48 of file at_hdmac_regs.h.

#define AT_DMA_CH_REGS_BASE 0x3C /* Channel registers base address */

Definition at line 68 of file at_hdmac_regs.h.

#define AT_DMA_CHDR 0x2C /* Channel Handler Disable Register */

Definition at line 59 of file at_hdmac_regs.h.

#define AT_DMA_CHER 0x28 /* Channel Handler Enable Register */

Definition at line 54 of file at_hdmac_regs.h.

#define AT_DMA_CHSR 0x30 /* Channel Handler Status Register */

Definition at line 63 of file at_hdmac_regs.h.

#define AT_DMA_CREQ 0x0C /* Software Chunk Transfer Request Register */

Definition at line 32 of file at_hdmac_regs.h.

#define AT_DMA_DCREQ ( x ) (0x1 << (1 + ((x) << 1))) /* Request a destination chunk transfer on channel x */

Definition at line 34 of file at_hdmac_regs.h.

#define AT_DMA_DIS ( x ) (0x1 << (x))

Definition at line 60 of file at_hdmac_regs.h.

#define AT_DMA_DLAST ( x ) (0x1 << (1 + ((x) << 1))) /* This dst rq is last tx of buffer on channel x */

Definition at line 38 of file at_hdmac_regs.h.

#define AT_DMA_DSREQ ( x ) (0x1 << (1 + ((x) << 1))) /* Request a destination single transfer on channel x */

Definition at line 30 of file at_hdmac_regs.h.

#define AT_DMA_EBCIDR 0x1C /* Disable register */

Definition at line 45 of file at_hdmac_regs.h.

#define AT_DMA_EBCIER 0x18 /* Enable register */

Definition at line 44 of file at_hdmac_regs.h.

#define AT_DMA_EBCIMR 0x20 /* Mask Register */

Definition at line 46 of file at_hdmac_regs.h.

#define AT_DMA_EBCISR 0x24 /* Status Register */

Definition at line 47 of file at_hdmac_regs.h.

#define AT_DMA_EMPT ( x ) (0x1 << (16 + (x)))

Definition at line 64 of file at_hdmac_regs.h.

#define AT_DMA_EN 0x04 /* Controller Enable Register */

Definition at line 25 of file at_hdmac_regs.h.

#define AT_DMA_ENA ( x ) (0x1 << (x))

Definition at line 55 of file at_hdmac_regs.h.

#define AT_DMA_ENABLE (0x1 << 0)

Definition at line 26 of file at_hdmac_regs.h.

#define AT_DMA_ERR ( x ) (0x1 << (AT_DMA_ERR_OFFSET + (x)))

Definition at line 52 of file at_hdmac_regs.h.

#define AT_DMA_ERR_OFFSET 16

Definition at line 49 of file at_hdmac_regs.h.

#define AT_DMA_GCFG 0x00 /* Global Configuration Register */

Definition at line 19 of file at_hdmac_regs.h.

#define AT_DMA_IF_BIGEND ( i ) (0x1 << (i)) /* AHB-Lite Interface i in Big-endian mode */

Definition at line 20 of file at_hdmac_regs.h.

#define AT_DMA_KEEP ( x ) (0x1 << (24 + (x)))

Definition at line 57 of file at_hdmac_regs.h.

#define AT_DMA_LAST 0x10 /* Software Last Transfer Flag Register */

Definition at line 36 of file at_hdmac_regs.h.

#define AT_DMA_MAX_NR_CHANNELS 8

Definition at line 16 of file at_hdmac_regs.h.

#define AT_DMA_MEM_IF 0 /* interface 0 as memory interface */

Definition at line 126 of file at_hdmac_regs.h.

#define AT_DMA_PER_IF 1 /* interface 1 as peripheral interface */

Definition at line 127 of file at_hdmac_regs.h.

#define AT_DMA_RES ( x ) (0x1 << ( 8 + (x)))

Definition at line 61 of file at_hdmac_regs.h.

#define AT_DMA_SCREQ ( x ) (0x1 << ((x) << 1)) /* Request a source chunk transfer on channel x */

Definition at line 33 of file at_hdmac_regs.h.

#define AT_DMA_SLAST ( x ) (0x1 << ((x) << 1)) /* This src rq is last tx of buffer on channel x */

Definition at line 37 of file at_hdmac_regs.h.

#define AT_DMA_SREQ 0x08 /* Software Single Request Register */

Definition at line 28 of file at_hdmac_regs.h.

#define AT_DMA_SSREQ ( x ) (0x1 << ((x) << 1)) /* Request a source single transfer on channel x */

Definition at line 29 of file at_hdmac_regs.h.

#define AT_DMA_STAL ( x ) (0x1 << (24 + (x)))

Definition at line 65 of file at_hdmac_regs.h.

#define AT_DMA_SUSP ( x ) (0x1 << ( 8 + (x)))

Definition at line 56 of file at_hdmac_regs.h.

#define AT_DMA_SYNC 0x14 /* Request Synchronization Register */

Definition at line 40 of file at_hdmac_regs.h.

#define AT_DMA_SYR ( h ) (0x1 << (h)) /* Synchronize handshake line h */

Definition at line 41 of file at_hdmac_regs.h.

#define ATC_AUTO (0x1 << 31) /* Auto multiple buffer tx enable */

Definition at line 151 of file at_hdmac_regs.h.

#define ATC_BTSIZE ( x ) (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */

Definition at line 89 of file at_hdmac_regs.h.

#define ATC_BTSIZE_MAX 0xFFFFUL /* Maximum Buffer Transfer Size */

Definition at line 88 of file at_hdmac_regs.h.

#define ATC_CFG_OFFSET 0x14 /* Configuration Register */

Definition at line 77 of file at_hdmac_regs.h.

#define ATC_CTRLA_OFFSET 0x0C /* Control A Register */

Definition at line 75 of file at_hdmac_regs.h.

#define ATC_CTRLB_OFFSET 0x10 /* Control B Register */

Definition at line 76 of file at_hdmac_regs.h.

#define ATC_DADDR_OFFSET 0x04 /* Destination Address Register */

Definition at line 73 of file at_hdmac_regs.h.

#define ATC_DCSIZE ( x ) (ATC_DCSIZE_MASK & ((x) << 20))

Definition at line 101 of file at_hdmac_regs.h.

#define ATC_DCSIZE_1 (0x0 << 20)

Definition at line 102 of file at_hdmac_regs.h.

#define ATC_DCSIZE_128 (0x6 << 20)

Definition at line 108 of file at_hdmac_regs.h.

#define ATC_DCSIZE_16 (0x3 << 20)

Definition at line 105 of file at_hdmac_regs.h.

#define ATC_DCSIZE_256 (0x7 << 20)

Definition at line 109 of file at_hdmac_regs.h.

#define ATC_DCSIZE_32 (0x4 << 20)

Definition at line 106 of file at_hdmac_regs.h.

#define ATC_DCSIZE_4 (0x1 << 20)

Definition at line 103 of file at_hdmac_regs.h.

#define ATC_DCSIZE_64 (0x5 << 20)

Definition at line 107 of file at_hdmac_regs.h.

#define ATC_DCSIZE_8 (0x2 << 20)

Definition at line 104 of file at_hdmac_regs.h.

#define ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */

Definition at line 100 of file at_hdmac_regs.h.

#define ATC_DIF ( i ) ((0x3 & (i)) << 4) /* Dst tx done via AHB-Lite Interface i */

Definition at line 124 of file at_hdmac_regs.h.

#define ATC_DONE (0x1 << 31) /* Tx Done (only written back in descriptor) */

Definition at line 120 of file at_hdmac_regs.h.

#define ATC_DPIP_BOUNDARY ( x ) ((0x3FF & (x)) << 16)

Definition at line 162 of file at_hdmac_regs.h.

#define ATC_DPIP_HOLE ( x ) (0xFFFFU & (x))

Definition at line 161 of file at_hdmac_regs.h.

#define ATC_DPIP_OFFSET 0x1C /* Dst PIP Configuration Register */

Definition at line 79 of file at_hdmac_regs.h.

#define ATC_DSCR_IF ( i ) (0x3 & (i)) /* Dsc feched via AHB-Lite Interface i */

Definition at line 85 of file at_hdmac_regs.h.

#define ATC_DSCR_OFFSET 0x08 /* Descriptor Address Register */

Definition at line 74 of file at_hdmac_regs.h.

#define ATC_DST_ADDR_MODE_DECR (0x1 << 28) /* Decrementing Mode */

Definition at line 148 of file at_hdmac_regs.h.

#define ATC_DST_ADDR_MODE_FIXED (0x2 << 28) /* Fixed Mode */

Definition at line 149 of file at_hdmac_regs.h.

#define ATC_DST_ADDR_MODE_INCR (0x0 << 28) /* Incrementing Mode */

Definition at line 147 of file at_hdmac_regs.h.

#define ATC_DST_ADDR_MODE_MASK (0x3 << 28)

Definition at line 146 of file at_hdmac_regs.h.

#define ATC_DST_DSCR_DIS (0x1 << 20) /* Dst Descriptor fetch disable */

Definition at line 132 of file at_hdmac_regs.h.

#define ATC_DST_PIP (0x1 << 12) /* Destination Picture-in-Picture enabled */

Definition at line 130 of file at_hdmac_regs.h.

#define ATC_DST_WIDTH ( x ) ((x) << 28)

Definition at line 116 of file at_hdmac_regs.h.

#define ATC_DST_WIDTH_BYTE (0x0 << 28)

Definition at line 117 of file at_hdmac_regs.h.

#define ATC_DST_WIDTH_HALFWORD (0x1 << 28)

Definition at line 118 of file at_hdmac_regs.h.

#define ATC_DST_WIDTH_MASK (0x3 << 28) /* Destination Single Transfer Size */

Definition at line 115 of file at_hdmac_regs.h.

#define ATC_DST_WIDTH_WORD (0x2 << 28)

Definition at line 119 of file at_hdmac_regs.h.

#define ATC_FC_MASK (0x7 << 21) /* Choose Flow Controller */

Definition at line 133 of file at_hdmac_regs.h.

#define ATC_FC_MEM2MEM (0x0 << 21) /* Mem-to-Mem (DMA) */

Definition at line 134 of file at_hdmac_regs.h.

#define ATC_FC_MEM2PER (0x1 << 21) /* Mem-to-Periph (DMA) */

Definition at line 135 of file at_hdmac_regs.h.

#define ATC_FC_MEM2PER_PER (0x5 << 21) /* Mem-to-Periph (Peripheral) */

Definition at line 139 of file at_hdmac_regs.h.

#define ATC_FC_PER2MEM (0x2 << 21) /* Periph-to-Mem (DMA) */

Definition at line 136 of file at_hdmac_regs.h.

#define ATC_FC_PER2MEM_PER (0x4 << 21) /* Periph-to-Mem (Peripheral) */

Definition at line 138 of file at_hdmac_regs.h.

#define ATC_FC_PER2PER (0x3 << 21) /* Periph-to-Periph (DMA) */

Definition at line 137 of file at_hdmac_regs.h.

#define ATC_FC_PER2PER_DSTPER (0x7 << 21) /* Periph-to-Periph (Dst Peripheral) */

Definition at line 141 of file at_hdmac_regs.h.

#define ATC_FC_PER2PER_SRCPER (0x6 << 21) /* Periph-to-Periph (Src Peripheral) */

Definition at line 140 of file at_hdmac_regs.h.

#define ATC_IEN (0x1 << 30) /* BTC interrupt enable (active low) */

Definition at line 150 of file at_hdmac_regs.h.

#define ATC_SADDR_OFFSET 0x00 /* Source Address Register */

Definition at line 72 of file at_hdmac_regs.h.

#define ATC_SCSIZE ( x ) (ATC_SCSIZE_MASK & ((x) << 16))

Definition at line 91 of file at_hdmac_regs.h.

#define ATC_SCSIZE_1 (0x0 << 16)

Definition at line 92 of file at_hdmac_regs.h.

#define ATC_SCSIZE_128 (0x6 << 16)

Definition at line 98 of file at_hdmac_regs.h.

#define ATC_SCSIZE_16 (0x3 << 16)

Definition at line 95 of file at_hdmac_regs.h.

#define ATC_SCSIZE_256 (0x7 << 16)

Definition at line 99 of file at_hdmac_regs.h.

#define ATC_SCSIZE_32 (0x4 << 16)

Definition at line 96 of file at_hdmac_regs.h.

#define ATC_SCSIZE_4 (0x1 << 16)

Definition at line 93 of file at_hdmac_regs.h.

#define ATC_SCSIZE_64 (0x5 << 16)

Definition at line 97 of file at_hdmac_regs.h.

#define ATC_SCSIZE_8 (0x2 << 16)

Definition at line 94 of file at_hdmac_regs.h.

#define ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */

Definition at line 90 of file at_hdmac_regs.h.

#define ATC_SIF ( i ) (0x3 & (i)) /* Src tx done via AHB-Lite Interface i */

Definition at line 123 of file at_hdmac_regs.h.

#define ATC_SPIP_BOUNDARY ( x ) ((0x3FF & (x)) << 16)

Definition at line 158 of file at_hdmac_regs.h.

#define ATC_SPIP_HOLE ( x ) (0xFFFFU & (x))

Definition at line 157 of file at_hdmac_regs.h.

#define ATC_SPIP_OFFSET 0x18 /* Src PIP Configuration Register */

Definition at line 78 of file at_hdmac_regs.h.

#define ATC_SRC_ADDR_MODE_DECR (0x1 << 24) /* Decrementing Mode */

Definition at line 144 of file at_hdmac_regs.h.

#define ATC_SRC_ADDR_MODE_FIXED (0x2 << 24) /* Fixed Mode */

Definition at line 145 of file at_hdmac_regs.h.

#define ATC_SRC_ADDR_MODE_INCR (0x0 << 24) /* Incrementing Mode */

Definition at line 143 of file at_hdmac_regs.h.

#define ATC_SRC_ADDR_MODE_MASK (0x3 << 24)

Definition at line 142 of file at_hdmac_regs.h.

#define ATC_SRC_DSCR_DIS (0x1 << 16) /* Src Descriptor fetch disable */

Definition at line 131 of file at_hdmac_regs.h.

#define ATC_SRC_PIP (0x1 << 8) /* Source Picture-in-Picture enabled */

Definition at line 129 of file at_hdmac_regs.h.

#define ATC_SRC_WIDTH ( x ) ((x) << 24)

Definition at line 111 of file at_hdmac_regs.h.

#define ATC_SRC_WIDTH_BYTE (0x0 << 24)

Definition at line 112 of file at_hdmac_regs.h.

#define ATC_SRC_WIDTH_HALFWORD (0x1 << 24)

Definition at line 113 of file at_hdmac_regs.h.

#define ATC_SRC_WIDTH_MASK (0x3 << 24) /* Source Single Transfer Size */

Definition at line 110 of file at_hdmac_regs.h.

#define ATC_SRC_WIDTH_WORD (0x2 << 24)

Definition at line 114 of file at_hdmac_regs.h.

#define ch_regs ( x ) (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */

Definition at line 69 of file at_hdmac_regs.h.

#define channel_readl	(	atchan,
		name
	)	__raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)

Definition at line 256 of file at_hdmac_regs.h.

#define channel_writel	(	atchan,
		name,
		val
	)	__raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)

Definition at line 259 of file at_hdmac_regs.h.

#define dma_readl	(	atdma,
		name
	)	__raw_readl((atdma)->regs + AT_DMA_##name)

Definition at line 324 of file at_hdmac_regs.h.

#define dma_writel	(	atdma,
		name,
		val
	)	__raw_writel((val), (atdma)->regs + AT_DMA_##name)

Definition at line 326 of file at_hdmac_regs.h.

Enumeration Type Documentation

enum atc_status

atc_status - information bits stored in channel status flag

Manipulated with atomic operations.

Enumerator:

ATC_IS_ERROR
ATC_IS_PAUSED
ATC_IS_CYCLIC

Definition at line 211 of file at_hdmac_regs.h.

Data Structures

Macros

Enumerations

Macro Definition Documentation

Enumeration Type Documentation