#include <at_hdmac_regs.h>

Data Fields
struct dma_chan	chan_common

struct at_dma *	device

void __iomem *	ch_regs

u8	mask

unsigned long	status

struct tasklet_struct	tasklet

u32	save_cfg

u32	save_dscr

struct dma_slave_config	dma_sconfig

spinlock_t	lock

struct list_head	active_list

struct list_head	queue

struct list_head	free_list

unsigned int	descs_allocated

Detailed Description

struct at_dma_chan - internal representation of an Atmel HDMAC channel : common dmaengine channel object members : parent device : memory mapped register base : channel index in a mask : transmit status information from irq/prep* functions to tasklet (use atomic operations) : bottom half to finish transaction work : configuration register that is saved on suspend/resume cycle : for cyclic operations, preserve next descriptor address in the cyclic list on suspend/resume cycle : configuration for slave transfers, passed via DMA_SLAVE_CONFIG : serializes enqueue/dequeue operations to descriptors lists : list of descriptors dmaengine is being running on : list of descriptors ready to be submitted to engine : list of descriptors usable by the channel : records the actual size of the descriptor pool

Definition at line 236 of file at_hdmac_regs.h.