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| #define | ATLX_DRIVER_NAME "atl1" |
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| #define | atlx_adapter atl1_adapter |
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| #define | atlx_check_for_link atl1_check_for_link |
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| #define | atlx_check_link atl1_check_link |
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| #define | atlx_hash_mc_addr atl1_hash_mc_addr |
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| #define | atlx_hash_set atl1_hash_set |
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| #define | atlx_hw atl1_hw |
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| #define | atlx_mii_ioctl atl1_mii_ioctl |
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| #define | atlx_read_phy_reg atl1_read_phy_reg |
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| #define | atlx_set_mac atl1_set_mac |
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| #define | atlx_set_mac_addr atl1_set_mac_addr |
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| #define | IDLE_STATUS_RXMAC 0x1 |
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| #define | IDLE_STATUS_TXMAC 0x2 |
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| #define | IDLE_STATUS_RXQ 0x4 |
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| #define | IDLE_STATUS_TXQ 0x8 |
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| #define | IDLE_STATUS_DMAR 0x10 |
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| #define | IDLE_STATUS_DMAW 0x20 |
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| #define | IDLE_STATUS_SMB 0x40 |
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| #define | IDLE_STATUS_CMB 0x80 |
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| #define | MDIO_WAIT_TIMES 30 |
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| #define | MAC_CTRL_TX_PAUSE 0x10000 |
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| #define | MAC_CTRL_SCNT 0x20000 |
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| #define | MAC_CTRL_SRST_TX 0x40000 |
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| #define | MAC_CTRL_TX_SIMURST 0x80000 |
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| #define | MAC_CTRL_SPEED_SHIFT 20 |
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| #define | MAC_CTRL_SPEED_MASK 0x300000 |
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| #define | MAC_CTRL_SPEED_1000 0x2 |
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| #define | MAC_CTRL_SPEED_10_100 0x1 |
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| #define | MAC_CTRL_DBG_TX_BKPRESURE 0x400000 |
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| #define | MAC_CTRL_TX_HUGE 0x800000 |
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| #define | MAC_CTRL_RX_CHKSUM_EN 0x1000000 |
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| #define | MAC_CTRL_DBG 0x8000000 |
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| #define | WOL_CLK_SWITCH_EN 0x8000 |
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| #define | WOL_PT5_EN 0x200000 |
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| #define | WOL_PT6_EN 0x400000 |
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| #define | WOL_PT5_MATCH 0x8000000 |
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| #define | WOL_PT6_MATCH 0x10000000 |
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| #define | REG_WOL_PATTERN_LEN 0x14A4 |
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| #define | WOL_PT_LEN_MASK 0x7F |
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| #define | WOL_PT0_LEN_SHIFT 0 |
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| #define | WOL_PT1_LEN_SHIFT 8 |
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| #define | WOL_PT2_LEN_SHIFT 16 |
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| #define | WOL_PT3_LEN_SHIFT 24 |
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| #define | WOL_PT4_LEN_SHIFT 0 |
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| #define | WOL_PT5_LEN_SHIFT 8 |
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| #define | WOL_PT6_LEN_SHIFT 16 |
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| #define | REG_SRAM_RFD_LEN 0x1504 |
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| #define | REG_SRAM_RRD_ADDR 0x1508 |
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| #define | REG_SRAM_RRD_LEN 0x150C |
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| #define | REG_SRAM_TPD_ADDR 0x1510 |
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| #define | REG_SRAM_TPD_LEN 0x1514 |
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| #define | REG_SRAM_TRD_ADDR 0x1518 |
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| #define | REG_SRAM_TRD_LEN 0x151C |
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| #define | REG_SRAM_RXF_ADDR 0x1520 |
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| #define | REG_SRAM_RXF_LEN 0x1524 |
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| #define | REG_SRAM_TXF_ADDR 0x1528 |
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| #define | REG_SRAM_TXF_LEN 0x152C |
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| #define | REG_SRAM_TCPH_PATH_ADDR 0x1530 |
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| #define | SRAM_TCPH_ADDR_MASK 0xFFF |
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| #define | SRAM_TCPH_ADDR_SHIFT 0 |
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| #define | SRAM_PATH_ADDR_MASK 0xFFF |
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| #define | SRAM_PATH_ADDR_SHIFT 16 |
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| #define | REG_LOAD_PTR 0x1534 |
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| #define | REG_DESC_RFD_ADDR_LO 0x1544 |
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| #define | REG_DESC_RRD_ADDR_LO 0x1548 |
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| #define | REG_DESC_TPD_ADDR_LO 0x154C |
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| #define | REG_DESC_CMB_ADDR_LO 0x1550 |
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| #define | REG_DESC_SMB_ADDR_LO 0x1554 |
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| #define | REG_DESC_RFD_RRD_RING_SIZE 0x1558 |
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| #define | DESC_RFD_RING_SIZE_MASK 0x7FF |
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| #define | DESC_RFD_RING_SIZE_SHIFT 0 |
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| #define | DESC_RRD_RING_SIZE_MASK 0x7FF |
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| #define | DESC_RRD_RING_SIZE_SHIFT 16 |
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| #define | REG_DESC_TPD_RING_SIZE 0x155C |
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| #define | DESC_TPD_RING_SIZE_MASK 0x3FF |
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| #define | DESC_TPD_RING_SIZE_SHIFT 0 |
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| #define | REG_TXQ_CTRL 0x1580 |
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| #define | TXQ_CTRL_TPD_BURST_NUM_SHIFT 0 |
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| #define | TXQ_CTRL_TPD_BURST_NUM_MASK 0x1F |
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| #define | TXQ_CTRL_EN 0x20 |
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| #define | TXQ_CTRL_ENH_MODE 0x40 |
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| #define | TXQ_CTRL_TPD_FETCH_TH_SHIFT 8 |
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| #define | TXQ_CTRL_TPD_FETCH_TH_MASK 0x3F |
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| #define | TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 |
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| #define | TXQ_CTRL_TXF_BURST_NUM_MASK 0xFFFF |
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| #define | REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584 |
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| #define | TX_JUMBO_TASK_TH_MASK 0x7FF |
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| #define | TX_JUMBO_TASK_TH_SHIFT 0 |
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| #define | TX_TPD_MIN_IPG_MASK 0x1F |
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| #define | TX_TPD_MIN_IPG_SHIFT 16 |
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| #define | REG_RXQ_CTRL 0x15A0 |
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| #define | RXQ_CTRL_RFD_BURST_NUM_SHIFT 0 |
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| #define | RXQ_CTRL_RFD_BURST_NUM_MASK 0xFF |
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| #define | RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8 |
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| #define | RXQ_CTRL_RRD_BURST_THRESH_MASK 0xFF |
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| #define | RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16 |
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| #define | RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1F |
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| #define | RXQ_CTRL_CUT_THRU_EN 0x40000000 |
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| #define | RXQ_CTRL_EN 0x80000000 |
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| #define | REG_RXQ_JMBOSZ_RRDTIM 0x15A4 |
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| #define | RXQ_JMBOSZ_TH_MASK 0x7FF |
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| #define | RXQ_JMBOSZ_TH_SHIFT 0 |
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| #define | RXQ_JMBO_LKAH_MASK 0xF |
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| #define | RXQ_JMBO_LKAH_SHIFT 11 |
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| #define | RXQ_RRD_TIMER_MASK 0xFFFF |
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| #define | RXQ_RRD_TIMER_SHIFT 16 |
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| #define | REG_RXQ_RXF_PAUSE_THRESH 0x15A8 |
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| #define | RXQ_RXF_PAUSE_TH_HI_SHIFT 16 |
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| #define | RXQ_RXF_PAUSE_TH_HI_MASK 0xFFF |
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| #define | RXQ_RXF_PAUSE_TH_LO_SHIFT 0 |
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| #define | RXQ_RXF_PAUSE_TH_LO_MASK 0xFFF |
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| #define | REG_RXQ_RRD_PAUSE_THRESH 0x15AC |
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| #define | RXQ_RRD_PAUSE_TH_HI_SHIFT 0 |
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| #define | RXQ_RRD_PAUSE_TH_HI_MASK 0xFFF |
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| #define | RXQ_RRD_PAUSE_TH_LO_SHIFT 16 |
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| #define | RXQ_RRD_PAUSE_TH_LO_MASK 0xFFF |
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| #define | REG_DMA_CTRL 0x15C0 |
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| #define | DMA_CTRL_DMAR_IN_ORDER 0x1 |
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| #define | DMA_CTRL_DMAR_ENH_ORDER 0x2 |
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| #define | DMA_CTRL_DMAR_OUT_ORDER 0x4 |
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| #define | DMA_CTRL_RCB_VALUE 0x8 |
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| #define | DMA_CTRL_DMAR_BURST_LEN_SHIFT 4 |
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| #define | DMA_CTRL_DMAR_BURST_LEN_MASK 7 |
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| #define | DMA_CTRL_DMAW_BURST_LEN_SHIFT 7 |
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| #define | DMA_CTRL_DMAW_BURST_LEN_MASK 7 |
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| #define | DMA_CTRL_DMAR_EN 0x400 |
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| #define | DMA_CTRL_DMAW_EN 0x800 |
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| #define | REG_CSMB_CTRL 0x15D0 |
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| #define | CSMB_CTRL_CMB_NOW 1 |
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| #define | CSMB_CTRL_SMB_NOW 2 |
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| #define | CSMB_CTRL_CMB_EN 4 |
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| #define | CSMB_CTRL_SMB_EN 8 |
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| #define | REG_CMB_WRITE_TH 0x15D4 |
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| #define | CMB_RRD_TH_SHIFT 0 |
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| #define | CMB_RRD_TH_MASK 0x7FF |
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| #define | CMB_TPD_TH_SHIFT 16 |
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| #define | CMB_TPD_TH_MASK 0x7FF |
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| #define | REG_CMB_WRITE_TIMER 0x15D8 |
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| #define | CMB_RX_TM_SHIFT 0 |
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| #define | CMB_RX_TM_MASK 0xFFFF |
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| #define | CMB_TX_TM_SHIFT 16 |
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| #define | CMB_TX_TM_MASK 0xFFFF |
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| #define | REG_CMB_RX_PKT_CNT 0x15DC |
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| #define | REG_CMB_TX_PKT_CNT 0x15E0 |
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| #define | REG_SMB_TIMER 0x15E4 |
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| #define | REG_MAILBOX 0x15F0 |
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| #define | MB_RFD_PROD_INDX_SHIFT 0 |
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| #define | MB_RFD_PROD_INDX_MASK 0x7FF |
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| #define | MB_RRD_CONS_INDX_SHIFT 11 |
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| #define | MB_RRD_CONS_INDX_MASK 0x7FF |
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| #define | MB_TPD_PROD_INDX_SHIFT 22 |
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| #define | MB_TPD_PROD_INDX_MASK 0x3FF |
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| #define | ISR_SMB 0x1 |
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| #define | ISR_TIMER 0x2 |
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| #define | ISR_MANUAL 0x4 |
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| #define | ISR_RXF_OV 0x8 |
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| #define | ISR_RFD_UNRUN 0x10 |
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| #define | ISR_RRD_OV 0x20 |
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| #define | ISR_TXF_UNRUN 0x40 |
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| #define | ISR_LINK 0x80 |
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| #define | ISR_HOST_RFD_UNRUN 0x100 |
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| #define | ISR_HOST_RRD_OV 0x200 |
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| #define | ISR_DMAR_TO_RST 0x400 |
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| #define | ISR_DMAW_TO_RST 0x800 |
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| #define | ISR_GPHY 0x1000 |
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| #define | ISR_RX_PKT 0x10000 |
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| #define | ISR_TX_PKT 0x20000 |
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| #define | ISR_TX_DMA 0x40000 |
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| #define | ISR_RX_DMA 0x80000 |
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| #define | ISR_CMB_RX 0x100000 |
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| #define | ISR_CMB_TX 0x200000 |
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| #define | ISR_MAC_RX 0x400000 |
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| #define | ISR_MAC_TX 0x800000 |
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| #define | ISR_DIS_SMB 0x20000000 |
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| #define | ISR_DIS_DMA 0x40000000 |
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| #define | IMR_NORXTX_MASK |
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| #define | IMR_NORMAL_MASK |
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| #define | IMR_DEBUG_MASK |
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| #define | MEDIA_TYPE_1000M_FULL 1 |
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| #define | MEDIA_TYPE_100M_FULL 2 |
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| #define | MEDIA_TYPE_100M_HALF 3 |
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| #define | MEDIA_TYPE_10M_FULL 4 |
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| #define | MEDIA_TYPE_10M_HALF 5 |
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| #define | AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* All but 1000-Half */ |
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| #define | MAX_JUMBO_FRAME_SIZE 10240 |
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| #define | ATL1_EEDUMP_LEN 48 |
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| #define | PACKET_FLAG_ETH_TYPE 0x0080 |
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| #define | PACKET_FLAG_VLAN_INS 0x0100 |
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| #define | PACKET_FLAG_ERR 0x0200 |
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| #define | PACKET_FLAG_IPV4 0x0400 |
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| #define | PACKET_FLAG_UDP 0x0800 |
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| #define | PACKET_FLAG_TCP 0x1000 |
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| #define | PACKET_FLAG_BCAST 0x2000 |
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| #define | PACKET_FLAG_MCAST 0x4000 |
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| #define | PACKET_FLAG_PAUSE 0x8000 |
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| #define | ERR_FLAG_CRC 0x0001 |
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| #define | ERR_FLAG_CODE 0x0002 |
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| #define | ERR_FLAG_DRIBBLE 0x0004 |
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| #define | ERR_FLAG_RUNT 0x0008 |
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| #define | ERR_FLAG_OV 0x0010 |
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| #define | ERR_FLAG_TRUNC 0x0020 |
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| #define | ERR_FLAG_IP_CHKSUM 0x0040 |
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| #define | ERR_FLAG_L4_CHKSUM 0x0080 |
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| #define | ERR_FLAG_LEN 0x0100 |
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| #define | ERR_FLAG_DES_ADDR 0x0200 |
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| #define | TPD_BUFLEN_MASK 0x3FFF |
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| #define | TPD_BUFLEN_SHIFT 0 |
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| #define | TPD_DMAINT_MASK 0x0001 |
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| #define | TPD_DMAINT_SHIFT 14 |
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| #define | TPD_PKTNT_MASK 0x0001 |
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| #define | TPD_PKTINT_SHIFT 15 |
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| #define | TPD_VLANTAG_MASK 0xFFFF |
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| #define | TPD_VLANTAG_SHIFT 16 |
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| #define | TPD_EOP_MASK 0x0001 |
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| #define | TPD_EOP_SHIFT 0 |
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| #define | TPD_COALESCE_MASK 0x0001 |
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| #define | TPD_COALESCE_SHIFT 1 |
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| #define | TPD_INS_VL_TAG_MASK 0x0001 |
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| #define | TPD_INS_VL_TAG_SHIFT 2 |
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| #define | TPD_CUST_CSUM_EN_MASK 0x0001 |
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| #define | TPD_CUST_CSUM_EN_SHIFT 3 |
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| #define | TPD_SEGMENT_EN_MASK 0x0001 |
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| #define | TPD_SEGMENT_EN_SHIFT 4 |
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| #define | TPD_IP_CSUM_MASK 0x0001 |
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| #define | TPD_IP_CSUM_SHIFT 5 |
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| #define | TPD_TCP_CSUM_MASK 0x0001 |
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| #define | TPD_TCP_CSUM_SHIFT 6 |
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| #define | TPD_UDP_CSUM_MASK 0x0001 |
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| #define | TPD_UDP_CSUM_SHIFT 7 |
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| #define | TPD_VL_TAGGED_MASK 0x0001 |
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| #define | TPD_VL_TAGGED_SHIFT 8 |
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| #define | TPD_ETHTYPE_MASK 0x0001 |
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| #define | TPD_ETHTYPE_SHIFT 9 |
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| #define | TPD_IPHL_MASK 0x000F |
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| #define | TPD_IPHL_SHIFT 10 |
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| #define | TPD_TCPHDRLEN_MASK 0x000F |
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| #define | TPD_TCPHDRLEN_SHIFT 14 |
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| #define | TPD_HDRFLAG_MASK 0x0001 |
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| #define | TPD_HDRFLAG_SHIFT 18 |
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| #define | TPD_MSS_MASK 0x1FFF |
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| #define | TPD_MSS_SHIFT 19 |
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| #define | TPD_PLOADOFFSET_MASK 0x00FF |
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| #define | TPD_PLOADOFFSET_SHIFT 16 |
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| #define | TPD_CCSUMOFFSET_MASK 0x00FF |
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| #define | TPD_CCSUMOFFSET_SHIFT 24 |
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| #define | ATL1_MAX_INTR 3 |
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| #define | ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */ |
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| #define | ATL1_DEFAULT_TPD 256 |
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| #define | ATL1_MAX_TPD 1024 |
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| #define | ATL1_MIN_TPD 64 |
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| #define | ATL1_DEFAULT_RFD 512 |
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| #define | ATL1_MIN_RFD 128 |
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| #define | ATL1_MAX_RFD 2048 |
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| #define | ATL1_REG_COUNT 1538 |
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| #define | ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) |
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| #define | ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc) |
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| #define | ATL1_TPD_DESC(R, i) ATL1_GET_DESC(R, i, struct tx_packet_desc) |
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| #define | ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc) |
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1.8.2