Data Structures
struct	dbdma_global

struct	au1xxx_dma_channel

struct	au1xxx_ddma_desc

struct	dbdma_device_table

struct	dbdma_chan_config

Macros
#define	DDMA_CONFIG_AF (1 << 2)

#define	DDMA_CONFIG_AH (1 << 1)

#define	DDMA_CONFIG_AL (1 << 0)

#define	DDMA_THROTTLE_EN (1 << 31)

#define	DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */

#define	DDMA_CFG_SP (1 << 8) /* source DMA polarity */

#define	DDMA_CFG_DED (1 << 7) /* destination DMA level/edge detect */

#define	DDMA_CFG_DP (1 << 6) /* destination DMA polarity */

#define	DDMA_CFG_SYNC (1 << 5) /* Sync static bus controller */

#define	DDMA_CFG_PPR (1 << 4) /* PCI posted read/write control */

#define	DDMA_CFG_DFN (1 << 3) /* Descriptor fetch non-coherent */

#define	DDMA_CFG_SBE (1 << 2) /* Source big endian */

#define	DDMA_CFG_DBE (1 << 1) /* Destination big endian */

#define	DDMA_CFG_EN (1 << 0) /* Channel enable */

#define	DDMA_IRQ_IN (1 << 0)

#define	DDMA_STAT_DB (1 << 2) /* Doorbell pushed */

#define	DDMA_STAT_V (1 << 1) /* Descriptor valid */

#define	DDMA_STAT_H (1 << 0) /* Channel Halted */

#define	DSCR_CMD0_V (1 << 31) /* Descriptor valid */

#define	DSCR_CMD0_MEM (1 << 30) /* mem-mem transfer */

#define	DSCR_CMD0_SID_MASK (0x1f << 25) /* Source ID */

#define	DSCR_CMD0_DID_MASK (0x1f << 20) /* Destination ID */

#define	DSCR_CMD0_SW_MASK (0x3 << 18) /* Source Width */

#define	DSCR_CMD0_DW_MASK (0x3 << 16) /* Destination Width */

#define	DSCR_CMD0_ARB (0x1 << 15) /* Set for Hi Pri */

#define	DSCR_CMD0_DT_MASK (0x3 << 13) /* Descriptor Type */

#define	DSCR_CMD0_SN (0x1 << 12) /* Source non-coherent */

#define	DSCR_CMD0_DN (0x1 << 11) /* Destination non-coherent */

#define	DSCR_CMD0_SM (0x1 << 10) /* Stride mode */

#define	DSCR_CMD0_IE (0x1 << 8) /* Interrupt Enable */

#define	DSCR_CMD0_SP (0x1 << 4) /* Status pointer select */

#define	DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */

#define	DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */

#define	SW_STATUS_INUSE (1 << 0)

#define	AU1550_DSCR_CMD0_UART0_TX 0

#define	AU1550_DSCR_CMD0_UART0_RX 1

#define	AU1550_DSCR_CMD0_UART3_TX 2

#define	AU1550_DSCR_CMD0_UART3_RX 3

#define	AU1550_DSCR_CMD0_DMA_REQ0 4

#define	AU1550_DSCR_CMD0_DMA_REQ1 5

#define	AU1550_DSCR_CMD0_DMA_REQ2 6

#define	AU1550_DSCR_CMD0_DMA_REQ3 7

#define	AU1550_DSCR_CMD0_USBDEV_RX0 8

#define	AU1550_DSCR_CMD0_USBDEV_TX0 9

#define	AU1550_DSCR_CMD0_USBDEV_TX1 10

#define	AU1550_DSCR_CMD0_USBDEV_TX2 11

#define	AU1550_DSCR_CMD0_USBDEV_RX3 12

#define	AU1550_DSCR_CMD0_USBDEV_RX4 13

#define	AU1550_DSCR_CMD0_PSC0_TX 14

#define	AU1550_DSCR_CMD0_PSC0_RX 15

#define	AU1550_DSCR_CMD0_PSC1_TX 16

#define	AU1550_DSCR_CMD0_PSC1_RX 17

#define	AU1550_DSCR_CMD0_PSC2_TX 18

#define	AU1550_DSCR_CMD0_PSC2_RX 19

#define	AU1550_DSCR_CMD0_PSC3_TX 20

#define	AU1550_DSCR_CMD0_PSC3_RX 21

#define	AU1550_DSCR_CMD0_PCI_WRITE 22

#define	AU1550_DSCR_CMD0_NAND_FLASH 23

#define	AU1550_DSCR_CMD0_MAC0_RX 24

#define	AU1550_DSCR_CMD0_MAC0_TX 25

#define	AU1550_DSCR_CMD0_MAC1_RX 26

#define	AU1550_DSCR_CMD0_MAC1_TX 27

#define	AU1200_DSCR_CMD0_UART0_TX 0

#define	AU1200_DSCR_CMD0_UART0_RX 1

#define	AU1200_DSCR_CMD0_UART1_TX 2

#define	AU1200_DSCR_CMD0_UART1_RX 3

#define	AU1200_DSCR_CMD0_DMA_REQ0 4

#define	AU1200_DSCR_CMD0_DMA_REQ1 5

#define	AU1200_DSCR_CMD0_MAE_BE 6

#define	AU1200_DSCR_CMD0_MAE_FE 7

#define	AU1200_DSCR_CMD0_SDMS_TX0 8

#define	AU1200_DSCR_CMD0_SDMS_RX0 9

#define	AU1200_DSCR_CMD0_SDMS_TX1 10

#define	AU1200_DSCR_CMD0_SDMS_RX1 11

#define	AU1200_DSCR_CMD0_AES_TX 13

#define	AU1200_DSCR_CMD0_AES_RX 12

#define	AU1200_DSCR_CMD0_PSC0_TX 14

#define	AU1200_DSCR_CMD0_PSC0_RX 15

#define	AU1200_DSCR_CMD0_PSC1_TX 16

#define	AU1200_DSCR_CMD0_PSC1_RX 17

#define	AU1200_DSCR_CMD0_CIM_RXA 18

#define	AU1200_DSCR_CMD0_CIM_RXB 19

#define	AU1200_DSCR_CMD0_CIM_RXC 20

#define	AU1200_DSCR_CMD0_MAE_BOTH 21

#define	AU1200_DSCR_CMD0_LCD 22

#define	AU1200_DSCR_CMD0_NAND_FLASH 23

#define	AU1200_DSCR_CMD0_PSC0_SYNC 24

#define	AU1200_DSCR_CMD0_PSC1_SYNC 25

#define	AU1200_DSCR_CMD0_CIM_SYNC 26

#define	AU1300_DSCR_CMD0_UART0_TX 0

#define	AU1300_DSCR_CMD0_UART0_RX 1

#define	AU1300_DSCR_CMD0_UART1_TX 2

#define	AU1300_DSCR_CMD0_UART1_RX 3

#define	AU1300_DSCR_CMD0_UART2_TX 4

#define	AU1300_DSCR_CMD0_UART2_RX 5

#define	AU1300_DSCR_CMD0_UART3_TX 6

#define	AU1300_DSCR_CMD0_UART3_RX 7

#define	AU1300_DSCR_CMD0_SDMS_TX0 8

#define	AU1300_DSCR_CMD0_SDMS_RX0 9

#define	AU1300_DSCR_CMD0_SDMS_TX1 10

#define	AU1300_DSCR_CMD0_SDMS_RX1 11

#define	AU1300_DSCR_CMD0_AES_TX 12

#define	AU1300_DSCR_CMD0_AES_RX 13

#define	AU1300_DSCR_CMD0_PSC0_TX 14

#define	AU1300_DSCR_CMD0_PSC0_RX 15

#define	AU1300_DSCR_CMD0_PSC1_TX 16

#define	AU1300_DSCR_CMD0_PSC1_RX 17

#define	AU1300_DSCR_CMD0_PSC2_TX 18

#define	AU1300_DSCR_CMD0_PSC2_RX 19

#define	AU1300_DSCR_CMD0_PSC3_TX 20

#define	AU1300_DSCR_CMD0_PSC3_RX 21

#define	AU1300_DSCR_CMD0_LCD 22

#define	AU1300_DSCR_CMD0_NAND_FLASH 23

#define	AU1300_DSCR_CMD0_SDMS_TX2 24

#define	AU1300_DSCR_CMD0_SDMS_RX2 25

#define	AU1300_DSCR_CMD0_CIM_SYNC 26

#define	AU1300_DSCR_CMD0_UDMA 27

#define	AU1300_DSCR_CMD0_DMA_REQ0 28

#define	AU1300_DSCR_CMD0_DMA_REQ1 29

#define	DSCR_CMD0_THROTTLE 30

#define	DSCR_CMD0_ALWAYS 31

#define	DSCR_NDEV_IDS 32

#define	DSCR_DEV2CUSTOM_ID(x, d)

#define	DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF)

#define	DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)

#define	DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)

#define	DSCR_CMD0_BYTE 0

#define	DSCR_CMD0_HALFWORD 1

#define	DSCR_CMD0_WORD 2

#define	DSCR_CMD0_SW(x) (((x) & 0x3) << 18)

#define	DSCR_CMD0_DW(x) (((x) & 0x3) << 16)

#define	DSCR_CMD0_STANDARD 0

#define	DSCR_CMD0_LITERAL 1

#define	DSCR_CMD0_CMP_BRANCH 2

#define	DSCR_CMD0_DT(x) (((x) & 0x3) << 13)

#define	DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */

#define	DSCR_CMD0_ST_CURRENT 1 /* Write current status */

#define	DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */

#define	DSCR_CMD0_ST_BYTECNT 3 /* Write remaining byte count */

#define	DSCR_CMD0_ST(x) (((x) & 0x3) << 0)

#define	DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */

#define	DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */

#define	DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */

#define	DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */

#define	DSCR_CMD1_FL_MEM_STRIDE0 0

#define	DSCR_CMD1_FL_MEM_STRIDE1 1

#define	DSCR_CMD1_FL_MEM_STRIDE2 2

#define	DSCR_CMD1_FL(x) (((x) & 0x3) << 22)

#define	DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */

#define	DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */

#define	DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */

#define	DSCR_SRC1_SB(x) (((x) & 0x3fff) << 14)

#define	DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */

#define	DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0)

#define	DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */

#define	DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */

#define	DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */

#define	DSCR_DEST1_DB(x) (((x) & 0x3fff) << 14)

#define	DSCR_DEST1_DS_MASK (0x3fff << 0) /* Stride */

#define	DSCR_DEST1_DS(x) (((x) & 0x3fff) << 0)

#define	DSCR_xTS_SIZE1 0

#define	DSCR_xTS_SIZE2 1

#define	DSCR_xTS_SIZE4 2

#define	DSCR_xTS_SIZE8 3

#define	DSCR_SRC1_STS(x) (((x) & 3) << 30)

#define	DSCR_DEST1_DTS(x) (((x) & 3) << 30)

#define	DSCR_xAM_INCREMENT 0

#define	DSCR_xAM_DECREMENT 1

#define	DSCR_xAM_STATIC 2

#define	DSCR_xAM_BURST 3

#define	DSCR_SRC1_SAM(x) (((x) & 3) << 28)

#define	DSCR_DEST1_DAM(x) (((x) & 3) << 28)

#define	DSCR_NXTPTR_MASK (0x07ffffff)

#define	DSCR_NXTPTR(x) ((x) >> 5)

#define	DSCR_GET_NXTPTR(x) ((x) << 5)

#define	DSCR_NXTPTR_MS (1 << 27)

#define	NUM_DBDMA_CHANS 16

#define	DEV_FLAGS_INUSE (1 << 0)

#define	DEV_FLAGS_ANYUSE (1 << 1)

#define	DEV_FLAGS_OUT (1 << 2)

#define	DEV_FLAGS_IN (1 << 3)

#define	DEV_FLAGS_BURSTABLE (1 << 4)

#define	DEV_FLAGS_SYNC (1 << 5)

#define	DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS

#define	DDMA_FLAGS_IE (1 << 0)

#define	DDMA_FLAGS_NOIE (1 << 1)

Typedefs
typedef struct dbdma_global	dbdma_global_t

typedef struct au1xxx_dma_channel	au1x_dma_chan_t

typedef struct au1xxx_ddma_desc	au1x_ddma_desc_t

typedef struct dbdma_device_table	dbdev_tab_t

typedef struct dbdma_chan_config	chan_tab_t

Functions
u32	au1xxx_dbdma_chan_alloc (u32 srcid, u32 destid, void(callback)(int, void ), void *callparam)

u32	au1xxx_dbdma_set_devwidth (u32 chanid, int bits)

u32	au1xxx_dbdma_ring_alloc (u32 chanid, int entries)

u32	au1xxx_dbdma_put_source (u32 chanid, dma_addr_t buf, int nbytes, u32 flags)

u32	au1xxx_dbdma_put_dest (u32 chanid, dma_addr_t buf, int nbytes, u32 flags)

u32	au1xxx_dbdma_get_dest (u32 chanid, void *buf, int nbytes)

void	au1xxx_dbdma_stop (u32 chanid)

void	au1xxx_dbdma_start (u32 chanid)

void	au1xxx_dbdma_reset (u32 chanid)

u32	au1xxx_get_dma_residue (u32 chanid)

void	au1xxx_dbdma_chan_free (u32 chanid)

void	au1xxx_dbdma_dump (u32 chanid)

u32	au1xxx_dbdma_put_dscr (u32 chanid, au1x_ddma_desc_t *dscr)

u32	au1xxx_ddma_add_device (dbdev_tab_t *dev)

void	au1xxx_ddma_del_device (u32 devid)

void *	au1xxx_ddma_get_nextptr_virt (au1x_ddma_desc_t *dp)

Macro Definition Documentation

#define AU1200_DSCR_CMD0_AES_RX 12

Definition at line 171 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_AES_TX 13

Definition at line 170 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_CIM_RXA 18

Definition at line 176 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_CIM_RXB 19

Definition at line 177 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_CIM_RXC 20

Definition at line 178 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_CIM_SYNC 26

Definition at line 184 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_DMA_REQ0 4

Definition at line 162 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_DMA_REQ1 5

Definition at line 163 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_LCD 22

Definition at line 180 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_MAE_BE 6

Definition at line 164 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_MAE_BOTH 21

Definition at line 179 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_MAE_FE 7

Definition at line 165 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_NAND_FLASH 23

Definition at line 181 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_PSC0_RX 15

Definition at line 173 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_PSC0_SYNC 24

Definition at line 182 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_PSC0_TX 14

Definition at line 172 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_PSC1_RX 17

Definition at line 175 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_PSC1_SYNC 25

Definition at line 183 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_PSC1_TX 16

Definition at line 174 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_SDMS_RX0 9

Definition at line 167 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_SDMS_RX1 11

Definition at line 169 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_SDMS_TX0 8

Definition at line 166 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_SDMS_TX1 10

Definition at line 168 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_UART0_RX 1

Definition at line 159 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_UART0_TX 0

Definition at line 158 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_UART1_RX 3

Definition at line 161 of file au1xxx_dbdma.h.

#define AU1200_DSCR_CMD0_UART1_TX 2

Definition at line 160 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_AES_RX 13

Definition at line 199 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_AES_TX 12

Definition at line 198 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_CIM_SYNC 26

Definition at line 212 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_DMA_REQ0 28

Definition at line 214 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_DMA_REQ1 29

Definition at line 215 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_LCD 22

Definition at line 208 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_NAND_FLASH 23

Definition at line 209 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_PSC0_RX 15

Definition at line 201 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_PSC0_TX 14

Definition at line 200 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_PSC1_RX 17

Definition at line 203 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_PSC1_TX 16

Definition at line 202 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_PSC2_RX 19

Definition at line 205 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_PSC2_TX 18

Definition at line 204 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_PSC3_RX 21

Definition at line 207 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_PSC3_TX 20

Definition at line 206 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_SDMS_RX0 9

Definition at line 195 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_SDMS_RX1 11

Definition at line 197 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_SDMS_RX2 25

Definition at line 211 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_SDMS_TX0 8

Definition at line 194 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_SDMS_TX1 10

Definition at line 196 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_SDMS_TX2 24

Definition at line 210 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_UART0_RX 1

Definition at line 187 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_UART0_TX 0

Definition at line 186 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_UART1_RX 3

Definition at line 189 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_UART1_TX 2

Definition at line 188 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_UART2_RX 5

Definition at line 191 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_UART2_TX 4

Definition at line 190 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_UART3_RX 7

Definition at line 193 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_UART3_TX 6

Definition at line 192 of file au1xxx_dbdma.h.

#define AU1300_DSCR_CMD0_UDMA 27

Definition at line 213 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_DMA_REQ0 4

Definition at line 133 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_DMA_REQ1 5

Definition at line 134 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_DMA_REQ2 6

Definition at line 135 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_DMA_REQ3 7

Definition at line 136 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_MAC0_RX 24

Definition at line 153 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_MAC0_TX 25

Definition at line 154 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_MAC1_RX 26

Definition at line 155 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_MAC1_TX 27

Definition at line 156 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_NAND_FLASH 23

Definition at line 152 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_PCI_WRITE 22

Definition at line 151 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_PSC0_RX 15

Definition at line 144 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_PSC0_TX 14

Definition at line 143 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_PSC1_RX 17

Definition at line 146 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_PSC1_TX 16

Definition at line 145 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_PSC2_RX 19

Definition at line 148 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_PSC2_TX 18

Definition at line 147 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_PSC3_RX 21

Definition at line 150 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_PSC3_TX 20

Definition at line 149 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_UART0_RX 1

Definition at line 130 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_UART0_TX 0

Definition at line 129 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_UART3_RX 3

Definition at line 132 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_UART3_TX 2

Definition at line 131 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_USBDEV_RX0 8

Definition at line 137 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_USBDEV_RX3 12

Definition at line 141 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_USBDEV_RX4 13

Definition at line 142 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_USBDEV_TX0 9

Definition at line 138 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_USBDEV_TX1 10

Definition at line 139 of file au1xxx_dbdma.h.

#define AU1550_DSCR_CMD0_USBDEV_TX2 11

Definition at line 140 of file au1xxx_dbdma.h.

#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS

Definition at line 352 of file au1xxx_dbdma.h.

#define DDMA_CFG_DBE (1 << 1) /* Destination big endian */

Definition at line 74 of file au1xxx_dbdma.h.

#define DDMA_CFG_DED (1 << 7) /* destination DMA level/edge detect */

Definition at line 68 of file au1xxx_dbdma.h.

#define DDMA_CFG_DFN (1 << 3) /* Descriptor fetch non-coherent */

Definition at line 72 of file au1xxx_dbdma.h.

#define DDMA_CFG_DP (1 << 6) /* destination DMA polarity */

Definition at line 69 of file au1xxx_dbdma.h.

#define DDMA_CFG_EN (1 << 0) /* Channel enable */

Definition at line 75 of file au1xxx_dbdma.h.

#define DDMA_CFG_PPR (1 << 4) /* PCI posted read/write control */

Definition at line 71 of file au1xxx_dbdma.h.

#define DDMA_CFG_SBE (1 << 2) /* Source big endian */

Definition at line 73 of file au1xxx_dbdma.h.

#define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */

Definition at line 66 of file au1xxx_dbdma.h.

#define DDMA_CFG_SP (1 << 8) /* source DMA polarity */

Definition at line 67 of file au1xxx_dbdma.h.

#define DDMA_CFG_SYNC (1 << 5) /* Sync static bus controller */

Definition at line 70 of file au1xxx_dbdma.h.

#define DDMA_CONFIG_AF (1 << 2)

Definition at line 48 of file au1xxx_dbdma.h.

#define DDMA_CONFIG_AH (1 << 1)

Definition at line 49 of file au1xxx_dbdma.h.

#define DDMA_CONFIG_AL (1 << 0)

Definition at line 50 of file au1xxx_dbdma.h.

#define DDMA_FLAGS_IE (1 << 0)

Definition at line 384 of file au1xxx_dbdma.h.

#define DDMA_FLAGS_NOIE (1 << 1)

Definition at line 385 of file au1xxx_dbdma.h.

#define DDMA_IRQ_IN (1 << 0)

Definition at line 82 of file au1xxx_dbdma.h.

#define DDMA_STAT_DB (1 << 2) /* Doorbell pushed */

Definition at line 84 of file au1xxx_dbdma.h.

#define DDMA_STAT_H (1 << 0) /* Channel Halted */

Definition at line 86 of file au1xxx_dbdma.h.

#define DDMA_STAT_V (1 << 1) /* Descriptor valid */

Definition at line 85 of file au1xxx_dbdma.h.

#define DDMA_THROTTLE_EN (1 << 31)

Definition at line 52 of file au1xxx_dbdma.h.

#define DEV_FLAGS_ANYUSE (1 << 1)

Definition at line 334 of file au1xxx_dbdma.h.

#define DEV_FLAGS_BURSTABLE (1 << 4)

Definition at line 337 of file au1xxx_dbdma.h.

#define DEV_FLAGS_IN (1 << 3)

Definition at line 336 of file au1xxx_dbdma.h.

#define DEV_FLAGS_INUSE (1 << 0)

Definition at line 333 of file au1xxx_dbdma.h.

#define DEV_FLAGS_OUT (1 << 2)

Definition at line 335 of file au1xxx_dbdma.h.

#define DEV_FLAGS_SYNC (1 << 5)

Definition at line 338 of file au1xxx_dbdma.h.

#define DSCR_CMD0_ALWAYS 31

Definition at line 218 of file au1xxx_dbdma.h.

#define DSCR_CMD0_ARB (0x1 << 15) /* Set for Hi Pri */

Definition at line 116 of file au1xxx_dbdma.h.

#define DSCR_CMD0_BYTE 0

Definition at line 229 of file au1xxx_dbdma.h.

#define DSCR_CMD0_CMP_BRANCH 2

Definition at line 239 of file au1xxx_dbdma.h.

#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */

Definition at line 123 of file au1xxx_dbdma.h.

#define DSCR_CMD0_DID ( x ) (((x) & 0x1f) << 20)

Definition at line 226 of file au1xxx_dbdma.h.

#define DSCR_CMD0_DID_MASK (0x1f << 20) /* Destination ID */

Definition at line 113 of file au1xxx_dbdma.h.

#define DSCR_CMD0_DN (0x1 << 11) /* Destination non-coherent */

Definition at line 119 of file au1xxx_dbdma.h.

#define DSCR_CMD0_DT ( x ) (((x) & 0x3) << 13)

Definition at line 241 of file au1xxx_dbdma.h.

#define DSCR_CMD0_DT_MASK (0x3 << 13) /* Descriptor Type */

Definition at line 117 of file au1xxx_dbdma.h.

#define DSCR_CMD0_DW ( x ) (((x) & 0x3) << 16)

Definition at line 234 of file au1xxx_dbdma.h.

#define DSCR_CMD0_DW_MASK (0x3 << 16) /* Destination Width */

Definition at line 115 of file au1xxx_dbdma.h.

#define DSCR_CMD0_HALFWORD 1

Definition at line 230 of file au1xxx_dbdma.h.

#define DSCR_CMD0_IE (0x1 << 8) /* Interrupt Enable */

Definition at line 121 of file au1xxx_dbdma.h.

#define DSCR_CMD0_LITERAL 1

Definition at line 238 of file au1xxx_dbdma.h.

#define DSCR_CMD0_MEM (1 << 30) /* mem-mem transfer */

Definition at line 111 of file au1xxx_dbdma.h.

#define DSCR_CMD0_SID ( x ) (((x) & 0x1f) << 25)

Definition at line 225 of file au1xxx_dbdma.h.

#define DSCR_CMD0_SID_MASK (0x1f << 25) /* Source ID */

Definition at line 112 of file au1xxx_dbdma.h.

#define DSCR_CMD0_SM (0x1 << 10) /* Stride mode */

Definition at line 120 of file au1xxx_dbdma.h.

#define DSCR_CMD0_SN (0x1 << 12) /* Source non-coherent */

Definition at line 118 of file au1xxx_dbdma.h.

#define DSCR_CMD0_SP (0x1 << 4) /* Status pointer select */

Definition at line 122 of file au1xxx_dbdma.h.

#define DSCR_CMD0_ST ( x ) (((x) & 0x3) << 0)

Definition at line 249 of file au1xxx_dbdma.h.

#define DSCR_CMD0_ST_BYTECNT 3 /* Write remaining byte count */

Definition at line 247 of file au1xxx_dbdma.h.

#define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */

Definition at line 246 of file au1xxx_dbdma.h.

#define DSCR_CMD0_ST_CURRENT 1 /* Write current status */

Definition at line 245 of file au1xxx_dbdma.h.

#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */

Definition at line 124 of file au1xxx_dbdma.h.

#define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */

Definition at line 244 of file au1xxx_dbdma.h.

#define DSCR_CMD0_STANDARD 0

Definition at line 237 of file au1xxx_dbdma.h.

#define DSCR_CMD0_SW ( x ) (((x) & 0x3) << 18)

Definition at line 233 of file au1xxx_dbdma.h.

#define DSCR_CMD0_SW_MASK (0x3 << 18) /* Source Width */

Definition at line 114 of file au1xxx_dbdma.h.

#define DSCR_CMD0_THROTTLE 30

Definition at line 217 of file au1xxx_dbdma.h.

#define DSCR_CMD0_V (1 << 31) /* Descriptor valid */

Definition at line 110 of file au1xxx_dbdma.h.

#define DSCR_CMD0_WORD 2

Definition at line 231 of file au1xxx_dbdma.h.

#define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */

Definition at line 255 of file au1xxx_dbdma.h.

#define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */

Definition at line 253 of file au1xxx_dbdma.h.

#define DSCR_CMD1_FL ( x ) (((x) & 0x3) << 22)

Definition at line 262 of file au1xxx_dbdma.h.

#define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */

Definition at line 254 of file au1xxx_dbdma.h.

#define DSCR_CMD1_FL_MEM_STRIDE0 0

Definition at line 258 of file au1xxx_dbdma.h.

#define DSCR_CMD1_FL_MEM_STRIDE1 1

Definition at line 259 of file au1xxx_dbdma.h.

#define DSCR_CMD1_FL_MEM_STRIDE2 2

Definition at line 260 of file au1xxx_dbdma.h.

#define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */

Definition at line 252 of file au1xxx_dbdma.h.

#define DSCR_CUSTOM2DEV_ID ( x ) ((x) & 0xFF)

Definition at line 223 of file au1xxx_dbdma.h.

#define DSCR_DEST1_DAM ( x ) (((x) & 3) << 28)

Definition at line 292 of file au1xxx_dbdma.h.

#define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */

Definition at line 274 of file au1xxx_dbdma.h.

#define DSCR_DEST1_DB ( x ) (((x) & 0x3fff) << 14)

Definition at line 276 of file au1xxx_dbdma.h.

#define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */

Definition at line 275 of file au1xxx_dbdma.h.

#define DSCR_DEST1_DS ( x ) (((x) & 0x3fff) << 0)

Definition at line 278 of file au1xxx_dbdma.h.

#define DSCR_DEST1_DS_MASK (0x3fff << 0) /* Stride */

Definition at line 277 of file au1xxx_dbdma.h.

#define DSCR_DEST1_DTS ( x ) (((x) & 3) << 30)

Definition at line 285 of file au1xxx_dbdma.h.

#define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */

Definition at line 273 of file au1xxx_dbdma.h.

#define DSCR_DEV2CUSTOM_ID	(	x,
		d
	)

Value:

(((((x) & 0xFFFF) << 8) | 0x32000000) | \

((d) & 0xFF))

Definition at line 221 of file au1xxx_dbdma.h.

#define DSCR_GET_NXTPTR ( x ) ((x) << 5)

Definition at line 297 of file au1xxx_dbdma.h.

#define DSCR_NDEV_IDS 32

Definition at line 219 of file au1xxx_dbdma.h.

#define DSCR_NXTPTR ( x ) ((x) >> 5)

Definition at line 296 of file au1xxx_dbdma.h.

#define DSCR_NXTPTR_MASK (0x07ffffff)

Definition at line 295 of file au1xxx_dbdma.h.

#define DSCR_NXTPTR_MS (1 << 27)

Definition at line 298 of file au1xxx_dbdma.h.

#define DSCR_SRC1_SAM ( x ) (((x) & 3) << 28)

Definition at line 291 of file au1xxx_dbdma.h.

#define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */

Definition at line 266 of file au1xxx_dbdma.h.

#define DSCR_SRC1_SB ( x ) (((x) & 0x3fff) << 14)

Definition at line 268 of file au1xxx_dbdma.h.

#define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */

Definition at line 267 of file au1xxx_dbdma.h.

#define DSCR_SRC1_SS ( x ) (((x) & 0x3fff) << 0)

Definition at line 270 of file au1xxx_dbdma.h.

#define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */

Definition at line 269 of file au1xxx_dbdma.h.

#define DSCR_SRC1_STS ( x ) (((x) & 3) << 30)

Definition at line 284 of file au1xxx_dbdma.h.

#define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */

Definition at line 265 of file au1xxx_dbdma.h.

#define DSCR_xAM_BURST 3

Definition at line 290 of file au1xxx_dbdma.h.

#define DSCR_xAM_DECREMENT 1

Definition at line 288 of file au1xxx_dbdma.h.

#define DSCR_xAM_INCREMENT 0

Definition at line 287 of file au1xxx_dbdma.h.

#define DSCR_xAM_STATIC 2

Definition at line 289 of file au1xxx_dbdma.h.

#define DSCR_xTS_SIZE1 0

Definition at line 280 of file au1xxx_dbdma.h.

#define DSCR_xTS_SIZE2 1

Definition at line 281 of file au1xxx_dbdma.h.

#define DSCR_xTS_SIZE4 2

Definition at line 282 of file au1xxx_dbdma.h.

#define DSCR_xTS_SIZE8 3

Definition at line 283 of file au1xxx_dbdma.h.

#define NUM_DBDMA_CHANS 16

Definition at line 301 of file au1xxx_dbdma.h.

#define SW_STATUS_INUSE (1 << 0)

Definition at line 126 of file au1xxx_dbdma.h.

Typedef Documentation

typedef struct au1xxx_ddma_desc au1x_ddma_desc_t

typedef struct au1xxx_dma_channel au1x_dma_chan_t

typedef struct dbdma_chan_config chan_tab_t

typedef struct dbdma_device_table dbdev_tab_t

typedef struct dbdma_global dbdma_global_t

Function Documentation

u32 au1xxx_dbdma_chan_alloc	(	u32	srcid,
		u32	destid,
		void()(int, void )	callback,
		void *	callparam
	)

Definition at line 252 of file dbdma.c.

void au1xxx_dbdma_chan_free ( u32 chanid )

Definition at line 841 of file dbdma.c.

void au1xxx_dbdma_dump ( u32 chanid )

Definition at line 889 of file dbdma.c.

u32 au1xxx_dbdma_get_dest	(	u32	chanid,
		void **	buf,
		int *	nbytes
	)

Definition at line 714 of file dbdma.c.

u32 au1xxx_dbdma_put_dest	(	u32	chanid,
		dma_addr_t	buf,
		int	nbytes,
		u32	flags
	)

Definition at line 650 of file dbdma.c.

u32 au1xxx_dbdma_put_dscr	(	u32	chanid,
		au1x_ddma_desc_t *	dscr
	)

Definition at line 934 of file dbdma.c.

u32 au1xxx_dbdma_put_source	(	u32	chanid,
		dma_addr_t	buf,
		int	nbytes,
		u32	flags
	)

Definition at line 591 of file dbdma.c.

void au1xxx_dbdma_reset ( u32 chanid )

Definition at line 798 of file dbdma.c.

u32 au1xxx_dbdma_ring_alloc	(	u32	chanid,
		int	entries
	)

Definition at line 390 of file dbdma.c.

u32 au1xxx_dbdma_set_devwidth	(	u32	chanid,
		int	bits
	)

Definition at line 365 of file dbdma.c.

void au1xxx_dbdma_start ( u32 chanid )

Definition at line 783 of file dbdma.c.

void au1xxx_dbdma_stop ( u32 chanid )

Definition at line 753 of file dbdma.c.

u32 au1xxx_ddma_add_device ( dbdev_tab_t * dev )

Definition at line 218 of file dbdma.c.

void au1xxx_ddma_del_device ( u32 devid )

Definition at line 240 of file dbdma.c.

void* au1xxx_ddma_get_nextptr_virt ( au1x_ddma_desc_t * dp )

Definition at line 212 of file dbdma.c.

u32 au1xxx_get_dma_residue ( u32 chanid )

Definition at line 824 of file dbdma.c.

Data Structures

Macros

Typedefs

Functions

Macro Definition Documentation

Typedef Documentation

Function Documentation