#include <linux/types.h>

Data Structures
struct	bcma_drv_pci

Macros
#define	BCMA_CORE_PCI_CTL 0x0000 /* PCI Control */

#define	BCMA_CORE_PCI_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */

#define	BCMA_CORE_PCI_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */

#define	BCMA_CORE_PCI_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */

#define	BCMA_CORE_PCI_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */

#define	BCMA_CORE_PCI_ARBCTL 0x0010 /* PCI Arbiter Control */

#define	BCMA_CORE_PCI_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */

#define	BCMA_CORE_PCI_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */

#define	BCMA_CORE_PCI_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */

#define	BCMA_CORE_PCI_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */

#define	BCMA_CORE_PCI_ARBCTL_PARKID_4710 0x00000002 /* 4710 */

#define	BCMA_CORE_PCI_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */

#define	BCMA_CORE_PCI_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */

#define	BCMA_CORE_PCI_ISTAT 0x0020 /* Interrupt status */

#define	BCMA_CORE_PCI_ISTAT_INTA 0x00000001 /* PCI INTA# */

#define	BCMA_CORE_PCI_ISTAT_INTB 0x00000002 /* PCI INTB# */

#define	BCMA_CORE_PCI_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */

#define	BCMA_CORE_PCI_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */

#define	BCMA_CORE_PCI_ISTAT_PME 0x00000010 /* PCI PME# */

#define	BCMA_CORE_PCI_IMASK 0x0024 /* Interrupt mask */

#define	BCMA_CORE_PCI_IMASK_INTA 0x00000001 /* PCI INTA# */

#define	BCMA_CORE_PCI_IMASK_INTB 0x00000002 /* PCI INTB# */

#define	BCMA_CORE_PCI_IMASK_SERR 0x00000004 /* PCI SERR# */

#define	BCMA_CORE_PCI_IMASK_PERR 0x00000008 /* PCI PERR# */

#define	BCMA_CORE_PCI_IMASK_PME 0x00000010 /* PCI PME# */

#define	BCMA_CORE_PCI_MBOX 0x0028 /* Backplane to PCI Mailbox */

#define	BCMA_CORE_PCI_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */

#define	BCMA_CORE_PCI_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */

#define	BCMA_CORE_PCI_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */

#define	BCMA_CORE_PCI_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */

#define	BCMA_CORE_PCI_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */

#define	BCMA_CORE_PCI_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */

#define	BCMA_CORE_PCI_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */

#define	BCMA_CORE_PCI_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */

#define	BCMA_CORE_PCI_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */

#define	BCMA_CORE_PCI_BCAST_ADDR_MASK 0x000000FF

#define	BCMA_CORE_PCI_BCAST_DATA 0x0054 /* Backplane Broadcast Data */

#define	BCMA_CORE_PCI_GPIO_IN 0x0060 /* rev >= 2 only */

#define	BCMA_CORE_PCI_GPIO_OUT 0x0064 /* rev >= 2 only */

#define	BCMA_CORE_PCI_GPIO_ENABLE 0x0068 /* rev >= 2 only */

#define	BCMA_CORE_PCI_GPIO_CTL 0x006C /* rev >= 2 only */

#define	BCMA_CORE_PCI_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */

#define	BCMA_CORE_PCI_SBTOPCI0_MASK 0xFC000000

#define	BCMA_CORE_PCI_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */

#define	BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000

#define	BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */

#define	BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000

#define	BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */

#define	BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */

#define	BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */

#define	BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */

#define	BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2

#define	BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */

#define	BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */

#define	BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */

#define	BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */

#define	BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */

#define	BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */

#define	BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */

#define	BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */

#define	BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */

#define	BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */

#define	BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */

#define	BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */

#define	BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */

#define	BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */

#define	BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */

#define	BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */

#define	BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */

#define	BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */

#define	BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */

#define	BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */

#define	BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */

#define	BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */

#define	BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */

#define	BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */

#define	BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */

#define	BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */

#define	BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */

#define	BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */

#define	BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */

#define	BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */

#define	BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */

#define	BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */

#define	BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */

#define	BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */

#define	BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */

#define	BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */

#define	BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000

#define	BCMA_CORE_PCI_SBTOPCI_IO 0x00000001

#define	BCMA_CORE_PCI_SBTOPCI_CFG0 0x00000002

#define	BCMA_CORE_PCI_SBTOPCI_CFG1 0x00000003

#define	BCMA_CORE_PCI_SBTOPCI_PREF 0x00000004 /* Prefetch enable */

#define	BCMA_CORE_PCI_SBTOPCI_BURST 0x00000008 /* Burst enable */

#define	BCMA_CORE_PCI_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */

#define	BCMA_CORE_PCI_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */

#define	BCMA_CORE_PCI_SBTOPCI_RC_READ 0x00000000 /* Memory read */

#define	BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */

#define	BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */

#define	BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */

#define	BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */

#define	BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */

#define	BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */

#define	BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */

#define	BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */

#define	BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */

#define	BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */

#define	BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */

#define	BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */

#define	BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */

#define	BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */

#define	BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */

#define	BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */

#define	BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */

#define	BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */

#define	BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */

#define	BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */

#define	BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */

#define	BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */

#define	BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)

#define	BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */

#define	BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */

#define	BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */

#define	BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */

#define	BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */

#define	BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */

#define	BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */

#define	BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */

#define	BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */

#define	BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */

#define	BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */

#define	BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */

#define	BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */

#define	BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */

#define	BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */

#define	BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */

#define	BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */

#define	BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */

#define	BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */

#define	BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */

#define	BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */

#define	BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */

#define	BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */

#define	BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */

#define	BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */

#define	BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */

#define	BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */

#define	BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */

#define	BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */

#define	BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */

#define	BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */

#define	BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */

#define	BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */

#define	BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */

#define	BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */

#define	BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */

#define	BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */

#define	BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001

#define	pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)

#define	pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)

#define	pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)

#define	pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)

Functions
void __devinit	bcma_core_pci_init (struct bcma_drv_pci *pc)

int	bcma_core_pci_irq_ctl (struct bcma_drv_pci pc, struct bcma_device core, bool enable)

void	bcma_core_pci_extend_L1timer (struct bcma_drv_pci *pc, bool extend)

int	bcma_core_pci_pcibios_map_irq (const struct pci_dev *dev)

int	bcma_core_pci_plat_dev_init (struct pci_dev *dev)

Macro Definition Documentation

#define BCMA_CORE_PCI_ARBCTL 0x0010 /* PCI Arbiter Control */

Definition at line 14 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */

Definition at line 16 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */

Definition at line 15 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */

Definition at line 17 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_ARBCTL_PARKID_4710 0x00000002 /* 4710 */

Definition at line 19 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */

Definition at line 20 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */

Definition at line 21 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */

Definition at line 18 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */

Definition at line 143 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */

Definition at line 43 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_BCAST_ADDR_MASK 0x000000FF

Definition at line 44 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_BCAST_DATA 0x0054 /* Backplane Broadcast Data */

Definition at line 45 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */

Definition at line 169 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */

Definition at line 177 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */

Definition at line 172 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */

Definition at line 179 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */

Definition at line 174 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */

Definition at line 180 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */

Definition at line 175 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */

Definition at line 178 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */

Definition at line 173 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */

Definition at line 84 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */

Definition at line 56 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */

Definition at line 57 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CTL 0x0000 /* PCI Control */

PCI core registers.

Definition at line 9 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */

Definition at line 13 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */

Definition at line 12 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */

Definition at line 11 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */

Definition at line 10 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */

Definition at line 137 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */

Definition at line 148 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */

Definition at line 150 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */

Definition at line 141 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */

Definition at line 135 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */

Definition at line 133 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */

Definition at line 131 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */

Definition at line 140 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */

Definition at line 132 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)

Definition at line 134 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */

Definition at line 151 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */

Definition at line 136 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */

Definition at line 154 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */

Definition at line 153 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */

Definition at line 142 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */

Definition at line 138 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */

Definition at line 147 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */

Definition at line 146 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */

Definition at line 145 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */

Definition at line 144 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */

Definition at line 139 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */

Definition at line 152 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */

Definition at line 149 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_GPIO_CTL 0x006C /* rev >= 2 only */

Definition at line 49 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_GPIO_ENABLE 0x0068 /* rev >= 2 only */

Definition at line 48 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_GPIO_IN 0x0060 /* rev >= 2 only */

Definition at line 46 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_GPIO_OUT 0x0064 /* rev >= 2 only */

Definition at line 47 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_IMASK 0x0024 /* Interrupt mask */

Definition at line 28 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_IMASK_INTA 0x00000001 /* PCI INTA# */

Definition at line 29 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_IMASK_INTB 0x00000002 /* PCI INTB# */

Definition at line 30 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_IMASK_PERR 0x00000008 /* PCI PERR# */

Definition at line 32 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_IMASK_PME 0x00000010 /* PCI PME# */

Definition at line 33 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_IMASK_SERR 0x00000004 /* PCI SERR# */

Definition at line 31 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_ISTAT 0x0020 /* Interrupt status */

Definition at line 22 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_ISTAT_INTA 0x00000001 /* PCI INTA# */

Definition at line 23 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_ISTAT_INTB 0x00000002 /* PCI INTB# */

Definition at line 24 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */

Definition at line 26 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_ISTAT_PME 0x00000010 /* PCI PME# */

Definition at line 27 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */

Definition at line 25 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MBOX 0x0028 /* Backplane to PCI Mailbox */

Definition at line 34 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */

Definition at line 35 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */

Definition at line 36 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */

Definition at line 37 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */

Definition at line 38 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */

Definition at line 39 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */

Definition at line 40 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */

Definition at line 41 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */

Definition at line 42 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */

Definition at line 58 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */

Definition at line 63 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */

Definition at line 62 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */

Definition at line 59 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2

Definition at line 60 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */

Definition at line 61 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */

Definition at line 78 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */

Definition at line 77 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */

Definition at line 79 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */

Definition at line 81 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */

Definition at line 80 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */

Definition at line 73 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */

Definition at line 69 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */

Definition at line 72 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */

Definition at line 68 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */

Definition at line 64 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */

Definition at line 75 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */

Definition at line 71 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */

Definition at line 67 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */

Definition at line 70 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */

Definition at line 66 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */

Definition at line 76 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */

Definition at line 65 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */

Definition at line 74 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */

Definition at line 85 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */

Definition at line 86 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */

Definition at line 87 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */

Definition at line 88 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */

Definition at line 82 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */

Definition at line 83 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */

Definition at line 166 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */

Definition at line 120 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */

Definition at line 119 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */

Definition at line 117 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */

Definition at line 116 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */

Definition at line 118 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */

Definition at line 115 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */

Definition at line 128 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */

Definition at line 112 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */

Definition at line 114 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */

Definition at line 121 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */

Definition at line 123 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */

Definition at line 122 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */

Definition at line 127 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */

Definition at line 125 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */

Definition at line 113 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */

Definition at line 124 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */

Definition at line 126 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001

Definition at line 183 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */

Definition at line 50 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI0_MASK 0xFC000000

Definition at line 51 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */

Definition at line 52 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000

Definition at line 53 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */

Definition at line 54 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000

Definition at line 55 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI_BURST 0x00000008 /* Burst enable */

Definition at line 104 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI_CFG0 0x00000002

Definition at line 101 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI_CFG1 0x00000003

Definition at line 102 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI_IO 0x00000001

Definition at line 100 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000

Definition at line 99 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */

Definition at line 105 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI_PREF 0x00000004 /* Prefetch enable */

Definition at line 103 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */

Definition at line 106 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI_RC_READ 0x00000000 /* Memory read */

Definition at line 107 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */

Definition at line 108 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */

Definition at line 109 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */

Definition at line 165 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */

Definition at line 161 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */

Definition at line 162 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */

Definition at line 157 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */

Definition at line 158 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */

Definition at line 159 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */

Definition at line 160 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SPROM ( wordoffset ) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */

Definition at line 89 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */

Definition at line 96 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */

Definition at line 95 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */

Definition at line 94 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */

Definition at line 93 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */

Definition at line 91 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */

Definition at line 90 of file bcma_driver_pci.h.

#define BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */

Definition at line 92 of file bcma_driver_pci.h.

#define pcicore_read16	(	pc,
		offset
	)	bcma_read16((pc)->core, offset)

Definition at line 212 of file bcma_driver_pci.h.

#define pcicore_read32	(	pc,
		offset
	)	bcma_read32((pc)->core, offset)

Definition at line 213 of file bcma_driver_pci.h.

#define pcicore_write16	(	pc,
		offset,
		val
	)	bcma_write16((pc)->core, offset, val)

Definition at line 214 of file bcma_driver_pci.h.

#define pcicore_write32	(	pc,
		offset,
		val
	)	bcma_write32((pc)->core, offset, val)

Definition at line 215 of file bcma_driver_pci.h.

Function Documentation

void bcma_core_pci_extend_L1timer	(	struct bcma_drv_pci *	pc,
		bool	extend
	)

Definition at line 265 of file driver_pci.c.

void __devinit bcma_core_pci_init ( struct bcma_drv_pci * pc )

Definition at line 217 of file driver_pci.c.

int bcma_core_pci_irq_ctl	(	struct bcma_drv_pci *	pc,
		struct bcma_device *	core,
		bool	enable
	)

Definition at line 232 of file driver_pci.c.

int bcma_core_pci_pcibios_map_irq ( const struct pci_dev * dev )

Definition at line 580 of file driver_pci_host.c.

int bcma_core_pci_plat_dev_init ( struct pci_dev * dev )

Definition at line 558 of file driver_pci_host.c.

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation