bf5xx_nand.c File Reference

#include <linux/module.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <asm/blackfin.h>
#include <asm/dma.h>
#include <asm/cacheflush.h>
#include <asm/nand.h>
#include <asm/portmux.h>

Go to the source code of this file.

Data Structures
struct	bf5xx_nand_info

Macros
#define	DRV_NAME   "bf5xx-nand"
#define	DRV_VERSION   "1.2"
#define	DRV_AUTHOR   "Bryan Wu <[email protected]>"
#define	DRV_DESC   "BF5xx on-chip NAND FLash Controller Driver"
#define	NBUSY   0x01 /* Not Busy */
#define	WB_FULL   0x02 /* Write Buffer Full */
#define	PG_WR_STAT   0x04 /* Page Write Pending */
#define	PG_RD_STAT   0x08 /* Page Read Pending */
#define	WB_EMPTY   0x10 /* Write Buffer Empty */
#define	NBUSYIRQ   0x01 /* Not Busy IRQ */
#define	WB_OVF   0x02 /* Write Buffer Overflow */
#define	WB_EDGE   0x04 /* Write Buffer Edge Detect */
#define	RD_RDY   0x08 /* Read Data Ready */
#define	WR_DONE   0x10 /* Page Write Done */
#define	ECC_RST   0x01 /* ECC (and NFC counters) Reset */
#define	PG_RD_START   0x01 /* Page Read Start */
#define	PG_WR_START   0x02 /* Page Write Start */
#define	bf5xx_nand_suspend   NULL
#define	bf5xx_nand_resume   NULL

Functions
	module_init (bf5xx_nand_init)
	module_exit (bf5xx_nand_exit)
	MODULE_LICENSE ("GPL")
	MODULE_AUTHOR (DRV_AUTHOR)
	MODULE_DESCRIPTION (DRV_DESC)
	MODULE_ALIAS ("platform:"DRV_NAME)

Macro Definition Documentation

#define bf5xx_nand_resume   NULL

Definition at line 862 of file bf5xx_nand.c.

#define bf5xx_nand_suspend   NULL

Definition at line 861 of file bf5xx_nand.c.

#define DRV_AUTHOR   "Bryan Wu <[email protected]>"

Definition at line 65 of file bf5xx_nand.c.

#define DRV_DESC   "BF5xx on-chip NAND FLash Controller Driver"

Definition at line 66 of file bf5xx_nand.c.

#define DRV_NAME   "bf5xx-nand"

Definition at line 63 of file bf5xx_nand.c.

#define DRV_VERSION   "1.2"

Definition at line 64 of file bf5xx_nand.c.

#define ECC_RST   0x01 /* ECC (and NFC counters) Reset */

Definition at line 83 of file bf5xx_nand.c.

#define NBUSY   0x01 /* Not Busy */

Definition at line 69 of file bf5xx_nand.c.

#define NBUSYIRQ   0x01 /* Not Busy IRQ */

Definition at line 76 of file bf5xx_nand.c.

#define PG_RD_START   0x01 /* Page Read Start */

Definition at line 86 of file bf5xx_nand.c.

#define PG_RD_STAT   0x08 /* Page Read Pending */

Definition at line 72 of file bf5xx_nand.c.

#define PG_WR_START   0x02 /* Page Write Start */

Definition at line 87 of file bf5xx_nand.c.

#define PG_WR_STAT   0x04 /* Page Write Pending */

Definition at line 71 of file bf5xx_nand.c.

#define RD_RDY   0x08 /* Read Data Ready */

Definition at line 79 of file bf5xx_nand.c.

#define WB_EDGE   0x04 /* Write Buffer Edge Detect */

Definition at line 78 of file bf5xx_nand.c.

#define WB_EMPTY   0x10 /* Write Buffer Empty */

Definition at line 73 of file bf5xx_nand.c.

#define WB_FULL   0x02 /* Write Buffer Full */

Definition at line 70 of file bf5xx_nand.c.

#define WB_OVF   0x02 /* Write Buffer Overflow */

Definition at line 77 of file bf5xx_nand.c.

#define WR_DONE   0x10 /* Page Write Done */

Definition at line 80 of file bf5xx_nand.c.

Function Documentation

MODULE_ALIAS

(

"platform:"

DRV_NAME

)

MODULE_AUTHOR

(

DRV_AUTHOR

)

MODULE_DESCRIPTION

(

DRV_DESC

)

module_exit

(

bf5xx_nand_exit

)

module_init

(

bf5xx_nand_init

)

MODULE_LICENSE

(

"GPL"

)