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include
linux
mtd
nand.h
Go to the documentation of this file.
1
/*
2
* linux/include/linux/mtd/nand.h
3
*
4
* Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5
* Steven J. Hill <sjhill@realitydiluted.com>
6
* Thomas Gleixner <tglx@linutronix.de>
7
*
8
* This program is free software; you can redistribute it and/or modify
9
* it under the terms of the GNU General Public License version 2 as
10
* published by the Free Software Foundation.
11
*
12
* Info:
13
* Contains standard defines and IDs for NAND flash devices
14
*
15
* Changelog:
16
* See git changelog.
17
*/
18
#ifndef __LINUX_MTD_NAND_H
19
#define __LINUX_MTD_NAND_H
20
21
#include <linux/wait.h>
22
#include <
linux/spinlock.h
>
23
#include <
linux/mtd/mtd.h
>
24
#include <
linux/mtd/flashchip.h
>
25
#include <
linux/mtd/bbm.h
>
26
27
struct
mtd_info
;
28
struct
nand_flash_dev
;
29
/* Scan and identify a NAND device */
30
extern
int
nand_scan
(
struct
mtd_info
*mtd,
int
max_chips);
31
/*
32
* Separate phases of nand_scan(), allowing board driver to intervene
33
* and override command or ECC setup according to flash type.
34
*/
35
extern
int
nand_scan_ident
(
struct
mtd_info
*mtd,
int
max_chips,
36
struct
nand_flash_dev
*
table
);
37
extern
int
nand_scan_tail
(
struct
mtd_info
*mtd);
38
39
/* Free resources held by the NAND device */
40
extern
void
nand_release
(
struct
mtd_info
*mtd);
41
42
/* Internal helper for board drivers which need to override command function */
43
extern
void
nand_wait_ready
(
struct
mtd_info
*mtd);
44
45
/* locks all blocks present in the device */
46
extern
int
nand_lock
(
struct
mtd_info
*mtd, loff_t ofs,
uint64_t
len);
47
48
/* unlocks specified locked blocks */
49
extern
int
nand_unlock
(
struct
mtd_info
*mtd, loff_t ofs,
uint64_t
len);
50
51
/* The maximum number of NAND chips in an array */
52
#define NAND_MAX_CHIPS 8
53
54
/*
55
* This constant declares the max. oobsize / page, which
56
* is supported now. If you add a chip with bigger oobsize/page
57
* adjust this accordingly.
58
*/
59
#define NAND_MAX_OOBSIZE 640
60
#define NAND_MAX_PAGESIZE 8192
61
62
/*
63
* Constants for hardware specific CLE/ALE/NCE function
64
*
65
* These are bits which can be or'ed to set/clear multiple
66
* bits in one go.
67
*/
68
/* Select the chip by setting nCE to low */
69
#define NAND_NCE 0x01
70
/* Select the command latch by setting CLE to high */
71
#define NAND_CLE 0x02
72
/* Select the address latch by setting ALE to high */
73
#define NAND_ALE 0x04
74
75
#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
76
#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
77
#define NAND_CTRL_CHANGE 0x80
78
79
/*
80
* Standard NAND flash commands
81
*/
82
#define NAND_CMD_READ0 0
83
#define NAND_CMD_READ1 1
84
#define NAND_CMD_RNDOUT 5
85
#define NAND_CMD_PAGEPROG 0x10
86
#define NAND_CMD_READOOB 0x50
87
#define NAND_CMD_ERASE1 0x60
88
#define NAND_CMD_STATUS 0x70
89
#define NAND_CMD_STATUS_MULTI 0x71
90
#define NAND_CMD_SEQIN 0x80
91
#define NAND_CMD_RNDIN 0x85
92
#define NAND_CMD_READID 0x90
93
#define NAND_CMD_ERASE2 0xd0
94
#define NAND_CMD_PARAM 0xec
95
#define NAND_CMD_GET_FEATURES 0xee
96
#define NAND_CMD_SET_FEATURES 0xef
97
#define NAND_CMD_RESET 0xff
98
99
#define NAND_CMD_LOCK 0x2a
100
#define NAND_CMD_UNLOCK1 0x23
101
#define NAND_CMD_UNLOCK2 0x24
102
103
/* Extended commands for large page devices */
104
#define NAND_CMD_READSTART 0x30
105
#define NAND_CMD_RNDOUTSTART 0xE0
106
#define NAND_CMD_CACHEDPROG 0x15
107
108
/* Extended commands for AG-AND device */
109
/*
110
* Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
111
* there is no way to distinguish that from NAND_CMD_READ0
112
* until the remaining sequence of commands has been completed
113
* so add a high order bit and mask it off in the command.
114
*/
115
#define NAND_CMD_DEPLETE1 0x100
116
#define NAND_CMD_DEPLETE2 0x38
117
#define NAND_CMD_STATUS_MULTI 0x71
118
#define NAND_CMD_STATUS_ERROR 0x72
119
/* multi-bank error status (banks 0-3) */
120
#define NAND_CMD_STATUS_ERROR0 0x73
121
#define NAND_CMD_STATUS_ERROR1 0x74
122
#define NAND_CMD_STATUS_ERROR2 0x75
123
#define NAND_CMD_STATUS_ERROR3 0x76
124
#define NAND_CMD_STATUS_RESET 0x7f
125
#define NAND_CMD_STATUS_CLEAR 0xff
126
127
#define NAND_CMD_NONE -1
128
129
/* Status bits */
130
#define NAND_STATUS_FAIL 0x01
131
#define NAND_STATUS_FAIL_N1 0x02
132
#define NAND_STATUS_TRUE_READY 0x20
133
#define NAND_STATUS_READY 0x40
134
#define NAND_STATUS_WP 0x80
135
136
/*
137
* Constants for ECC_MODES
138
*/
139
typedef
enum
{
140
NAND_ECC_NONE
,
141
NAND_ECC_SOFT
,
142
NAND_ECC_HW
,
143
NAND_ECC_HW_SYNDROME
,
144
NAND_ECC_HW_OOB_FIRST
,
145
NAND_ECC_SOFT_BCH
,
146
}
nand_ecc_modes_t
;
147
148
/*
149
* Constants for Hardware ECC
150
*/
151
/* Reset Hardware ECC for read */
152
#define NAND_ECC_READ 0
153
/* Reset Hardware ECC for write */
154
#define NAND_ECC_WRITE 1
155
/* Enable Hardware ECC before syndrome is read back from flash */
156
#define NAND_ECC_READSYN 2
157
158
/* Bit mask for flags passed to do_nand_read_ecc */
159
#define NAND_GET_DEVICE 0x80
160
161
162
/*
163
* Option constants for bizarre disfunctionality and real
164
* features.
165
*/
166
/* Buswidth is 16 bit */
167
#define NAND_BUSWIDTH_16 0x00000002
168
/* Device supports partial programming without padding */
169
#define NAND_NO_PADDING 0x00000004
170
/* Chip has cache program function */
171
#define NAND_CACHEPRG 0x00000008
172
/* Chip has copy back function */
173
#define NAND_COPYBACK 0x00000010
174
/*
175
* AND Chip which has 4 banks and a confusing page / block
176
* assignment. See Renesas datasheet for further information.
177
*/
178
#define NAND_IS_AND 0x00000020
179
/*
180
* Chip has a array of 4 pages which can be read without
181
* additional ready /busy waits.
182
*/
183
#define NAND_4PAGE_ARRAY 0x00000040
184
/*
185
* Chip requires that BBT is periodically rewritten to prevent
186
* bits from adjacent blocks from 'leaking' in altering data.
187
* This happens with the Renesas AG-AND chips, possibly others.
188
*/
189
#define BBT_AUTO_REFRESH 0x00000080
190
/* Chip does not allow subpage writes */
191
#define NAND_NO_SUBPAGE_WRITE 0x00000200
192
193
/* Device is one of 'new' xD cards that expose fake nand command set */
194
#define NAND_BROKEN_XD 0x00000400
195
196
/* Device behaves just like nand, but is readonly */
197
#define NAND_ROM 0x00000800
198
199
/* Device supports subpage reads */
200
#define NAND_SUBPAGE_READ 0x00001000
201
202
/* Options valid for Samsung large page devices */
203
#define NAND_SAMSUNG_LP_OPTIONS \
204
(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
205
206
/* Macros to identify the above */
207
#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
208
#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
209
#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
210
#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
211
212
/* Non chip related options */
213
/* This option skips the bbt scan during initialization. */
214
#define NAND_SKIP_BBTSCAN 0x00010000
215
/*
216
* This option is defined if the board driver allocates its own buffers
217
* (e.g. because it needs them DMA-coherent).
218
*/
219
#define NAND_OWN_BUFFERS 0x00020000
220
/* Chip may not exist, so silence any errors in scan */
221
#define NAND_SCAN_SILENT_NODEV 0x00040000
222
223
/* Options set by nand scan */
224
/* Nand scan has allocated controller struct */
225
#define NAND_CONTROLLER_ALLOC 0x80000000
226
227
/* Cell info constants */
228
#define NAND_CI_CHIPNR_MSK 0x03
229
#define NAND_CI_CELLTYPE_MSK 0x0C
230
231
/* Keep gcc happy */
232
struct
nand_chip
;
233
234
/* ONFI timing mode, used in both asynchronous and synchronous mode */
235
#define ONFI_TIMING_MODE_0 (1 << 0)
236
#define ONFI_TIMING_MODE_1 (1 << 1)
237
#define ONFI_TIMING_MODE_2 (1 << 2)
238
#define ONFI_TIMING_MODE_3 (1 << 3)
239
#define ONFI_TIMING_MODE_4 (1 << 4)
240
#define ONFI_TIMING_MODE_5 (1 << 5)
241
#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
242
243
/* ONFI feature address */
244
#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
245
246
/* ONFI subfeature parameters length */
247
#define ONFI_SUBFEATURE_PARAM_LEN 4
248
249
struct
nand_onfi_params
{
250
/* rev info and features block */
251
/* 'O' 'N' 'F' 'I' */
252
u8
sig
[4];
253
__le16
revision
;
254
__le16
features
;
255
__le16
opt_cmd
;
256
u8
reserved
[22];
257
258
/* manufacturer information block */
259
char
manufacturer
[12];
260
char
model
[20];
261
u8
jedec_id
;
262
__le16
date_code
;
263
u8
reserved2
[13];
264
265
/* memory organization block */
266
__le32
byte_per_page
;
267
__le16
spare_bytes_per_page
;
268
__le32
data_bytes_per_ppage
;
269
__le16
spare_bytes_per_ppage
;
270
__le32
pages_per_block
;
271
__le32
blocks_per_lun
;
272
u8
lun_count
;
273
u8
addr_cycles
;
274
u8
bits_per_cell
;
275
__le16
bb_per_lun
;
276
__le16
block_endurance
;
277
u8
guaranteed_good_blocks
;
278
__le16
guaranteed_block_endurance
;
279
u8
programs_per_page
;
280
u8
ppage_attr
;
281
u8
ecc_bits
;
282
u8
interleaved_bits
;
283
u8
interleaved_ops
;
284
u8
reserved3
[13];
285
286
/* electrical parameter block */
287
u8
io_pin_capacitance_max
;
288
__le16
async_timing_mode
;
289
__le16
program_cache_timing_mode
;
290
__le16
t_prog
;
291
__le16
t_bers
;
292
__le16
t_r
;
293
__le16
t_ccs
;
294
__le16
src_sync_timing_mode
;
295
__le16
src_ssync_features
;
296
__le16
clk_pin_capacitance_typ
;
297
__le16
io_pin_capacitance_typ
;
298
__le16
input_pin_capacitance_typ
;
299
u8
input_pin_capacitance_max
;
300
u8
driver_strenght_support
;
301
__le16
t_int_r
;
302
__le16
t_ald
;
303
u8
reserved4
[7];
304
305
/* vendor */
306
u8
reserved5
[90];
307
308
__le16
crc
;
309
}
__attribute__
((packed));
310
311
#define ONFI_CRC_BASE 0x4F4E
312
321
struct
nand_hw_control
{
322
spinlock_t
lock
;
323
struct
nand_chip
*
active
;
324
wait_queue_head_t
wq
;
325
};
326
357
struct
nand_ecc_ctrl
{
358
nand_ecc_modes_t
mode
;
359
int
steps
;
360
int
size
;
361
int
bytes
;
362
int
total
;
363
int
strength
;
364
int
prepad
;
365
int
postpad
;
366
struct
nand_ecclayout
*
layout
;
367
void
*
priv
;
368
void
(*
hwctl
)(
struct
mtd_info
*mtd,
int
mode
);
369
int
(*
calculate
)(
struct
mtd_info
*mtd,
const
uint8_t
*
dat
,
370
uint8_t
*ecc_code);
371
int
(*
correct
)(
struct
mtd_info
*mtd,
uint8_t
*
dat
,
uint8_t
*read_ecc,
372
uint8_t
*calc_ecc);
373
int
(*
read_page_raw
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
chip
,
374
uint8_t
*
buf
,
int
oob_required,
int
page
);
375
int
(*
write_page_raw
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
chip
,
376
const
uint8_t
*
buf
,
int
oob_required);
377
int
(*
read_page
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
chip
,
378
uint8_t
*
buf
,
int
oob_required,
int
page
);
379
int
(*
read_subpage
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
chip
,
380
uint32_t
offs
,
uint32_t
len
,
uint8_t
*
buf
);
381
int
(*
write_page
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
chip
,
382
const
uint8_t
*
buf
,
int
oob_required);
383
int
(*
write_oob_raw
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
chip
,
384
int
page
);
385
int
(*
read_oob_raw
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
chip
,
386
int
page
);
387
int
(*
read_oob
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
chip
,
int
page
);
388
int
(*
write_oob
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
chip
,
389
int
page
);
390
};
391
401
struct
nand_buffers
{
402
uint8_t
ecccalc
[
NAND_MAX_OOBSIZE
];
403
uint8_t
ecccode
[
NAND_MAX_OOBSIZE
];
404
uint8_t
databuf
[
NAND_MAX_PAGESIZE
+
NAND_MAX_OOBSIZE
];
405
};
406
493
struct
nand_chip
{
494
void
__iomem
*
IO_ADDR_R
;
495
void
__iomem
*
IO_ADDR_W
;
496
497
uint8_t
(*
read_byte
)(
struct
mtd_info
*mtd);
498
u16
(*
read_word
)(
struct
mtd_info
*mtd);
499
void
(*
write_buf
)(
struct
mtd_info
*mtd,
const
uint8_t
*
buf
,
int
len
);
500
void
(*
read_buf
)(
struct
mtd_info
*mtd,
uint8_t
*
buf
,
int
len
);
501
void
(*
select_chip
)(
struct
mtd_info
*mtd,
int
chip
);
502
int
(*
block_bad
)(
struct
mtd_info
*mtd, loff_t ofs,
int
getchip);
503
int
(*
block_markbad
)(
struct
mtd_info
*mtd, loff_t ofs);
504
void
(*
cmd_ctrl
)(
struct
mtd_info
*mtd,
int
dat
,
unsigned
int
ctrl
);
505
int
(*
init_size
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
this
,
506
u8
*id_data);
507
int
(*
dev_ready
)(
struct
mtd_info
*mtd);
508
void
(*
cmdfunc
)(
struct
mtd_info
*mtd,
unsigned
command
,
int
column,
509
int
page_addr);
510
int
(*
waitfunc
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
this
);
511
void
(*
erase_cmd
)(
struct
mtd_info
*mtd,
int
page
);
512
int
(*
scan_bbt
)(
struct
mtd_info
*mtd);
513
int
(*
errstat
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
this
,
int
state
,
514
int
status
,
int
page
);
515
int
(*
write_page
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
chip
,
516
const
uint8_t
*
buf
,
int
oob_required,
int
page
,
517
int
cached
,
int
raw
);
518
int
(*
onfi_set_features
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
chip
,
519
int
feature_addr,
uint8_t
*subfeature_para);
520
int
(*
onfi_get_features
)(
struct
mtd_info
*mtd,
struct
nand_chip
*
chip
,
521
int
feature_addr,
uint8_t
*subfeature_para);
522
523
int
chip_delay
;
524
unsigned
int
options
;
525
unsigned
int
bbt_options
;
526
527
int
page_shift
;
528
int
phys_erase_shift
;
529
int
bbt_erase_shift
;
530
int
chip_shift
;
531
int
numchips
;
532
uint64_t
chipsize
;
533
int
pagemask
;
534
int
pagebuf
;
535
unsigned
int
pagebuf_bitflips
;
536
int
subpagesize
;
537
uint8_t
cellinfo
;
538
int
badblockpos
;
539
int
badblockbits
;
540
541
int
onfi_version
;
542
struct
nand_onfi_params
onfi_params
;
543
544
flstate_t
state
;
545
546
uint8_t
*
oob_poi
;
547
struct
nand_hw_control
*
controller
;
548
struct
nand_ecclayout
*
ecclayout
;
549
550
struct
nand_ecc_ctrl
ecc
;
551
struct
nand_buffers
*
buffers
;
552
struct
nand_hw_control
hwcontrol
;
553
554
uint8_t
*
bbt
;
555
struct
nand_bbt_descr
*
bbt_td
;
556
struct
nand_bbt_descr
*
bbt_md
;
557
558
struct
nand_bbt_descr
*
badblock_pattern
;
559
560
void
*
priv
;
561
};
562
563
/*
564
* NAND Flash Manufacturer ID Codes
565
*/
566
#define NAND_MFR_TOSHIBA 0x98
567
#define NAND_MFR_SAMSUNG 0xec
568
#define NAND_MFR_FUJITSU 0x04
569
#define NAND_MFR_NATIONAL 0x8f
570
#define NAND_MFR_RENESAS 0x07
571
#define NAND_MFR_STMICRO 0x20
572
#define NAND_MFR_HYNIX 0xad
573
#define NAND_MFR_MICRON 0x2c
574
#define NAND_MFR_AMD 0x01
575
#define NAND_MFR_MACRONIX 0xc2
576
#define NAND_MFR_EON 0x92
577
590
struct
nand_flash_dev
{
591
char
*
name
;
592
int
id
;
593
unsigned
long
pagesize
;
594
unsigned
long
chipsize
;
595
unsigned
long
erasesize
;
596
unsigned
long
options
;
597
};
598
604
struct
nand_manufacturers
{
605
int
id
;
606
char
*
name
;
607
};
608
609
extern
struct
nand_flash_dev
nand_flash_ids
[];
610
extern
struct
nand_manufacturers
nand_manuf_ids
[];
611
612
extern
int
nand_scan_bbt
(
struct
mtd_info
*mtd,
struct
nand_bbt_descr
*bd);
613
extern
int
nand_update_bbt
(
struct
mtd_info
*mtd, loff_t
offs
);
614
extern
int
nand_default_bbt
(
struct
mtd_info
*mtd);
615
extern
int
nand_isbad_bbt
(
struct
mtd_info
*mtd, loff_t
offs
,
int
allowbbt);
616
extern
int
nand_erase_nand
(
struct
mtd_info
*mtd,
struct
erase_info
*
instr
,
617
int
allowbbt);
618
extern
int
nand_do_read
(
struct
mtd_info
*mtd, loff_t
from
,
size_t
len,
619
size_t
*retlen,
uint8_t
*
buf
);
620
633
struct
platform_nand_chip
{
634
int
nr_chips
;
635
int
chip_offset
;
636
int
nr_partitions
;
637
struct
mtd_partition
*
partitions
;
638
struct
nand_ecclayout
*
ecclayout
;
639
int
chip_delay
;
640
unsigned
int
options
;
641
unsigned
int
bbt_options
;
642
const
char
**
part_probe_types
;
643
};
644
645
/* Keep gcc happy */
646
struct
platform_device
;
647
664
struct
platform_nand_ctrl
{
665
int
(*
probe
)(
struct
platform_device
*
pdev
);
666
void
(*
remove
)(
struct
platform_device
*
pdev
);
667
void
(*
hwcontrol
)(
struct
mtd_info
*mtd,
int
cmd
);
668
int
(*
dev_ready
)(
struct
mtd_info
*mtd);
669
void
(*
select_chip
)(
struct
mtd_info
*mtd,
int
chip
);
670
void
(*
cmd_ctrl
)(
struct
mtd_info
*mtd,
int
dat
,
unsigned
int
ctrl
);
671
void
(*
write_buf
)(
struct
mtd_info
*mtd,
const
uint8_t
*
buf
,
int
len
);
672
void
(*
read_buf
)(
struct
mtd_info
*mtd,
uint8_t
*
buf
,
int
len
);
673
unsigned
char
(*
read_byte
)(
struct
mtd_info
*mtd);
674
void
*
priv
;
675
};
676
682
struct
platform_nand_data
{
683
struct
platform_nand_chip
chip
;
684
struct
platform_nand_ctrl
ctrl
;
685
};
686
687
/* Some helpers to access the data structures */
688
static
inline
689
struct
platform_nand_chip
*get_platform_nandchip(
struct
mtd_info
*mtd)
690
{
691
struct
nand_chip
*
chip
= mtd->
priv
;
692
693
return
chip->
priv
;
694
}
695
696
/* return the supported asynchronous timing mode. */
697
static
inline
int
onfi_get_async_timing_mode(
struct
nand_chip
*
chip
)
698
{
699
if
(!chip->
onfi_version
)
700
return
ONFI_TIMING_MODE_UNKNOWN
;
701
return
le16_to_cpu
(chip->
onfi_params
.async_timing_mode);
702
}
703
704
/* return the supported synchronous timing mode. */
705
static
inline
int
onfi_get_sync_timing_mode(
struct
nand_chip
*chip)
706
{
707
if
(!chip->
onfi_version
)
708
return
ONFI_TIMING_MODE_UNKNOWN
;
709
return
le16_to_cpu
(chip->
onfi_params
.src_sync_timing_mode);
710
}
711
712
#endif
/* __LINUX_MTD_NAND_H */
Generated on Thu Jan 10 2013 13:04:08 for Linux Kernel by
1.8.2