Go to the source code of this file.
| #define EXC_0x03 |
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level | ) |
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Value:"Application stack overflow\n" \
level " - Please increase the stack size of the application using elf2flt -s option,\n" \
level " and/or reduce the stack use of the application.\n"
Definition at line 69 of file traps.h.
| #define EXC_0x04 |
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level | ) |
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Value:"Unimplmented exception occurred\n" \
level " - Maybe you forgot to install a custom exception handler?\n"
Definition at line 59 of file traps.h.
| #define EXC_0x10 |
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level | ) |
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Value:"Single step\n" \
level " - When the processor is in single step mode, every instruction\n" \
level " generates an exception. Primarily used for debugging.\n"
Definition at line 73 of file traps.h.
| #define EXC_0x11 |
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Value:"Exception caused by a trace buffer full condition\n" \
level " - The processor takes this exception when the trace\n" \
level " buffer overflows (only when enabled by the Trace Unit Control register).\n"
Definition at line 77 of file traps.h.
| #define EXC_0x21 |
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level | ) |
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Value:"Undefined instruction\n" \
level " - May be used to emulate instructions that are not defined for\n" \
level " a particular processor implementation.\n"
Definition at line 81 of file traps.h.
| #define EXC_0x22 |
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level | ) |
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Value:"Illegal instruction combination\n" \
level " - See section for multi-issue rules in the Blackfin\n" \
level " Processor Instruction Set Reference.\n"
Definition at line 85 of file traps.h.
| #define EXC_0x23 |
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level | ) |
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Value:"Data access CPLB protection violation\n" \
level " - Attempted read or write to Supervisor resource,\n" \
level " or illegal data memory access. \n"
Definition at line 89 of file traps.h.
| #define EXC_0x24 |
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level | ) |
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Value:"Data access misaligned address violation\n" \
level " - Attempted misaligned data memory or data cache access.\n"
Definition at line 93 of file traps.h.
| #define EXC_0x25 |
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level | ) |
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Value:"Unrecoverable event\n" \
level " - For example, an exception generated while processing a previous exception.\n"
Definition at line 96 of file traps.h.
| #define EXC_0x26 |
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level | ) |
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Value:"Data access CPLB miss\n" \
level " - Used by the MMU to signal a CPLB miss on a data access.\n"
Definition at line 99 of file traps.h.
| #define EXC_0x27 |
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level | ) |
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Value:"Data access multiple CPLB hits\n" \
level " - More than one CPLB entry matches data fetch address.\n"
Definition at line 102 of file traps.h.
| #define EXC_0x28 |
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level | ) |
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Value:"Program Sequencer Exception caused by an emulation watchpoint match\n" \
level " - There is a watchpoint match, and one of the EMUSW\n" \
level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
Definition at line 105 of file traps.h.
| #define EXC_0x2A |
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level | ) |
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Value:"Instruction fetch misaligned address violation\n" \
level " - Attempted misaligned instruction cache fetch.\n"
Definition at line 109 of file traps.h.
| #define EXC_0x2B |
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level | ) |
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Value:"CPLB protection violation\n" \
level " - Illegal instruction fetch access (memory protection violation).\n"
Definition at line 112 of file traps.h.
| #define EXC_0x2C |
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level | ) |
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Value:"Instruction fetch CPLB miss\n" \
level " - CPLB miss on an instruction fetch.\n"
Definition at line 115 of file traps.h.
| #define EXC_0x2D |
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level | ) |
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Value:"Instruction fetch multiple CPLB hits\n" \
level " - More than one CPLB entry matches instruction fetch address.\n"
Definition at line 118 of file traps.h.
| #define EXC_0x2E |
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level | ) |
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Value:"Illegal use of supervisor resource\n" \
level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
level " Supervisor resources are registers and instructions that are reserved\n" \
level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
level " only instructions.\n"
Definition at line 121 of file traps.h.
| #define HWC_default |
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level | ) |
"Reserved\n" |
Value:"RAISE 5 instruction\n" \
level " Software issued a RAISE 5 instruction to invoke the Hardware\n"
Definition at line 64 of file traps.h.
Value:"System MMR Error\n" \
level " - An error occurred due to an invalid access to an System MMR location\n" \
level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
level " or a 16-bit register is accessed with a 32-bit instruction.\n"
Definition at line 52 of file traps.h.
| #define VEC_CPLB_I_M (44) |
| #define VEC_CPLB_I_MHIT (45) |
| #define VEC_CPLB_I_VL (43) |
| #define VEC_CPLB_MHIT (39) |
| #define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ |
| #define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */ |
| #define VEC_MISALI_D (36) |
| #define VEC_MISALI_I (42) |
1.8.2