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bnx2x_link.h
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1 /* Copyright 2008-2012 Broadcom Corporation
2  *
3  * Unless you and Broadcom execute a separate written software license
4  * agreement governing use of this software, this software is licensed to you
5  * under the terms of the GNU General Public License version 2, available
6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7  *
8  * Notwithstanding the above, under no circumstances may you combine this
9  * software in any way with any other Broadcom software provided under a
10  * license other than the GPL, without Broadcom's express prior written
11  * consent.
12  *
13  * Written by Yaniv Rosner
14  *
15  */
16 
17 #ifndef BNX2X_LINK_H
18 #define BNX2X_LINK_H
19 
20 
21 
22 /***********************************************************/
23 /* Defines */
24 /***********************************************************/
25 #define DEFAULT_PHY_DEV_ADDR 3
26 #define E2_DEFAULT_PHY_DEV_ADDR 5
27 
28 
29 
30 #define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
31 #define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
32 #define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
33 #define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
34 #define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
35 
36 #define NET_SERDES_IF_XFI 1
37 #define NET_SERDES_IF_SFI 2
38 #define NET_SERDES_IF_KR 3
39 #define NET_SERDES_IF_DXGXS 4
40 
41 #define SPEED_AUTO_NEG 0
42 #define SPEED_20000 20000
43 
44 #define SFP_EEPROM_PAGE_SIZE 16
45 #define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
46 #define SFP_EEPROM_VENDOR_NAME_SIZE 16
47 #define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
48 #define SFP_EEPROM_VENDOR_OUI_SIZE 3
49 #define SFP_EEPROM_PART_NO_ADDR 0x28
50 #define SFP_EEPROM_PART_NO_SIZE 16
51 #define SFP_EEPROM_REVISION_ADDR 0x38
52 #define SFP_EEPROM_REVISION_SIZE 4
53 #define SFP_EEPROM_SERIAL_ADDR 0x44
54 #define SFP_EEPROM_SERIAL_SIZE 16
55 #define SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */
56 #define SFP_EEPROM_DATE_SIZE 6
57 #define PWR_FLT_ERR_MSG_LEN 250
58 
59 #define XGXS_EXT_PHY_TYPE(ext_phy_config) \
60  ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
61 #define XGXS_EXT_PHY_ADDR(ext_phy_config) \
62  (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
63  PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
64 #define SERDES_EXT_PHY_TYPE(ext_phy_config) \
65  ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
66 
67 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
68 #define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
69 /* Single Media board contains single external phy */
70 #define SINGLE_MEDIA(params) (params->num_phys == 2)
71 /* Dual Media board contains two external phy with different media */
72 #define DUAL_MEDIA(params) (params->num_phys == 3)
73 
74 #define FW_PARAM_PHY_ADDR_MASK 0x000000FF
75 #define FW_PARAM_PHY_TYPE_MASK 0x0000FF00
76 #define FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000
77 #define FW_PARAM_MDIO_CTRL_OFFSET 16
78 #define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
79  FW_PARAM_PHY_ADDR_MASK)
80 #define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
81  FW_PARAM_PHY_TYPE_MASK)
82 #define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
83  FW_PARAM_MDIO_CTRL_MASK) >> \
84  FW_PARAM_MDIO_CTRL_OFFSET)
85 #define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
86  (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
87 
88 
89 #define PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
90 #define PFC_BRB_FULL_LB_XON_THRESHOLD 250
91 
92 #define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
93 
94 #define BMAC_CONTROL_RX_ENABLE 2
95 /***********************************************************/
96 /* Structs */
97 /***********************************************************/
98 #define INT_PHY 0
99 #define EXT_PHY1 1
100 #define EXT_PHY2 2
101 #define MAX_PHYS 3
102 
103 /* Same configuration is shared between the XGXS and the first external phy */
104 #define LINK_CONFIG_SIZE (MAX_PHYS - 1)
105 #define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
106  0 : (_phy_idx - 1))
107 /***********************************************************/
108 /* bnx2x_phy struct */
109 /* Defines the required arguments and function per phy */
110 /***********************************************************/
111 struct link_vars;
112 struct link_params;
113 struct bnx2x_phy;
114 
115 typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
116  struct link_vars *vars);
117 typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
118  struct link_vars *vars);
119 typedef void (*link_reset_t)(struct bnx2x_phy *phy,
120  struct link_params *params);
121 typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
122  struct link_params *params);
123 typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
124 typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
125 typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
126  struct link_params *params, u8 mode);
128  struct link_params *params, u32 action);
133 };
134 
135 struct bnx2x_phy {
137 
138  /* Loaded during init */
142  /* Require HW lock */
143 #define FLAGS_HW_LOCK_REQUIRED (1<<0)
144  /* No Over-Current detection */
145 #define FLAGS_NOC (1<<1)
146  /* Fan failure detection required */
147 #define FLAGS_FAN_FAILURE_DET_REQ (1<<2)
148  /* Initialize first the XGXS and only then the phy itself */
149 #define FLAGS_INIT_XGXS_FIRST (1<<3)
150 #define FLAGS_WC_DUAL_MODE (1<<4)
151 #define FLAGS_4_PORT_MODE (1<<5)
152 #define FLAGS_REARM_LATCH_SIGNAL (1<<6)
153 #define FLAGS_SFP_NOT_APPROVED (1<<7)
154 #define FLAGS_MDC_MDIO_WA (1<<8)
155 #define FLAGS_DUMMY_READ (1<<9)
156 #define FLAGS_MDC_MDIO_WA_B0 (1<<10)
157 #define FLAGS_TX_ERROR_CHECK (1<<12)
158 #define FLAGS_EEE (1<<13)
159 
160  /* preemphasis values for the rx side */
162 
163  /* preemphasis values for the tx side */
165 
166  /* EMAC address for access MDIO */
168 
170 
172 #define ETH_PHY_UNSPECIFIED 0x0
173 #define ETH_PHY_SFPP_10G_FIBER 0x1
174 #define ETH_PHY_XFP_FIBER 0x2
175 #define ETH_PHY_DA_TWINAX 0x3
176 #define ETH_PHY_BASE_T 0x4
177 #define ETH_PHY_SFP_1G_FIBER 0x5
178 #define ETH_PHY_KR 0xf0
179 #define ETH_PHY_CX4 0xf1
180 #define ETH_PHY_NOT_PRESENT 0xff
181 
182  /* The address in which version is located*/
184 
186 
188 
190 
193  /* Called per phy/port init, and it configures LASI, speed, autoneg,
194  duplex, flow control negotiation, etc. */
196 
197  /* Called due to interrupt. It determines the link, speed */
199 
200  /* Called when driver is unloading. Should reset the phy */
202 
203  /* Set the loopback configuration for the phy */
205 
206  /* Format the given raw number into str up to len */
208 
209  /* Reset the phy (both ports) */
211 
212  /* Set link led mode (on/off/oper)*/
214 
215  /* PHY Specific tasks */
217 #define DISABLE_TX 1
218 #define ENABLE_TX 2
219 #define PHY_INIT 3
220 };
221 
222 /* Inputs parameters to the CLC */
223 struct link_params {
224 
226 
227  /* Default / User Configuration */
229 #define LOOPBACK_NONE 0
230 #define LOOPBACK_EMAC 1
231 #define LOOPBACK_BMAC 2
232 #define LOOPBACK_XGXS 3
233 #define LOOPBACK_EXT_PHY 4
234 #define LOOPBACK_EXT 5
235 #define LOOPBACK_UMAC 6
236 #define LOOPBACK_XMAC 7
237 
238  /* Device parameters */
240 
243 
244  u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
245 
246  /* shmem parameters */
251 #define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
252 #define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
253 #define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
254 
256 
257  /* Phy register parameter */
259 
260  /* features */
262 #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
263 #define FEATURE_CONFIG_PFC_ENABLED (1<<1)
264 #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
265 #define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
266 #define FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8)
267 #define FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
268 #define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
269 #define FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11)
270  /* Will be populated during common init */
271  struct bnx2x_phy phy[MAX_PHYS];
272 
273  /* Will be populated during common init */
275 
277 
278  /* Used to configure the EEE Tx LPI timer, has several modes of
279  * operation, according to bits 29:28 -
280  * 2'b00: Timer will be configured by nvram, output will be the value
281  * from nvram.
282  * 2'b01: Timer will be configured by nvram, output will be in
283  * microseconds.
284  * 2'b10: bits 1:0 contain an nvram value which will be used instead
285  * of the one located in the nvram. Output will be that value.
286  * 2'b11: bits 19:0 contain the idle timer in microseconds; output
287  * will be in microseconds.
288  * Bits 31:30 should be 2'b11 in order for EEE to be enabled.
289  */
291 #define EEE_MODE_NVRAM_BALANCED_TIME (0xa00)
292 #define EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100)
293 #define EEE_MODE_NVRAM_LATENCY_TIME (0x6000)
294 #define EEE_MODE_NVRAM_MASK (0x3)
295 #define EEE_MODE_TIMER_MASK (0xfffff)
296 #define EEE_MODE_OUTPUT_TIME (1<<28)
297 #define EEE_MODE_OVERRIDE_NVRAM (1<<29)
298 #define EEE_MODE_ENABLE_LPI (1<<30)
299 #define EEE_MODE_ADV_LPI (1<<31)
300 
301  u16 hw_led_mode; /* part of the hw_config read from the shmem */
303 
304  /* Device pointer passed to all callback functions */
305  struct bnx2x *bp;
306  u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
307  req_flow_ctrl is set to AUTO */
310 };
311 
312 /* Output parameters */
313 struct link_vars {
315 #define PHY_XGXS_FLAG (1<<0)
316 #define PHY_SGMII_FLAG (1<<1)
317 #define PHY_PHYSICAL_LINK_FLAG (1<<2)
318 #define PHY_HALF_OPEN_CONN_FLAG (1<<3)
319 #define PHY_OVER_CURRENT_FLAG (1<<4)
320 #define PHY_SFP_TX_FAULT_FLAG (1<<5)
321 
323 #define MAC_TYPE_NONE 0
324 #define MAC_TYPE_EMAC 1
325 #define MAC_TYPE_BMAC 2
326 #define MAC_TYPE_UMAC 3
327 #define MAC_TYPE_XMAC 4
328 
329  u8 phy_link_up; /* internal phy link indication */
331 
334 
337 
338  /* The same definitions as the shmem parameter */
344 #define PERIODIC_FLAGS_LINK_EVENT 0x0001
345 
350 };
351 
352 /***********************************************************/
353 /* Functions */
354 /***********************************************************/
355 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars);
356 
357 /* Reset the link. Should be called when driver or interface goes down
358  Before calling phy firmware upgrade, the reset_ext_phy should be set
359  to 0 */
360 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
361  u8 reset_ext_phy);
362 int bnx2x_lfa_reset(struct link_params *params, struct link_vars *vars);
363 /* bnx2x_link_update should be called upon link interrupt */
364 int bnx2x_link_update(struct link_params *params, struct link_vars *vars);
365 
366 /* use the following phy functions to read/write from external_phy
367  In order to use it to read/write internal phy registers, use
368  DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
369  the register */
370 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
371  u8 devad, u16 reg, u16 *ret_val);
372 
373 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
374  u8 devad, u16 reg, u16 val);
375 
376 /* Reads the link_status from the shmem,
377  and update the link vars accordingly */
379  struct link_vars *output);
380 /* returns string representing the fw_version of the external phy */
382  u16 len);
383 
384 /* Set/Unset the led
385  Basically, the CLC takes care of the led for the link, but in case one needs
386  to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
387  blink the led, and LED_MODE_OFF to set the led off.*/
388 int bnx2x_set_led(struct link_params *params,
389  struct link_vars *vars, u8 mode, u32 speed);
390 #define LED_MODE_OFF 0
391 #define LED_MODE_ON 1
392 #define LED_MODE_OPER 2
393 #define LED_MODE_FRONT_PANEL_OFF 3
394 
395 /* bnx2x_handle_module_detect_int should be called upon module detection
396  interrupt */
397 void bnx2x_handle_module_detect_int(struct link_params *params);
398 
399 /* Get the actual link status. In case it returns 0, link is up,
400  otherwise link is down*/
401 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
402  u8 is_serdes);
403 
404 /* One-time initialization for external phy after power up */
405 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
406  u32 shmem2_base_path[], u32 chip_id);
407 
408 /* Reset the external PHY using GPIO */
409 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
410 
411 /* Reset the external of SFX7101 */
412 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);
413 
414 /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
416  struct link_params *params, u16 addr,
417  u8 byte_cnt, u8 *o_buf);
418 
419 void bnx2x_hw_reset_phy(struct link_params *params);
420 
421 /* Checks if HW lock is required for this phy/board type */
422 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
423  u32 shmem2_base);
424 
425 /* Check swap bit and adjust PHY order */
426 u32 bnx2x_phy_selection(struct link_params *params);
427 
428 /* Probe the phys on board, and populate them in "params" */
429 int bnx2x_phy_probe(struct link_params *params);
430 
431 /* Checks if fan failure detection is required on one of the phys on board */
432 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
433  u32 shmem2_base, u8 port);
434 
435 
436 
437 /* DCBX structs */
438 
439 /* Number of maximum COS per chip */
440 #define DCBX_E2E3_MAX_NUM_COS (2)
441 #define DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
442 #define DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
443 #define DCBX_E3B0_MAX_NUM_COS ( \
444  MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
445  DCBX_E3B0_MAX_NUM_COS_PORT1))
446 
447 #define DCBX_MAX_NUM_COS ( \
448  MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
449  DCBX_E2E3_MAX_NUM_COS))
450 
451 /* PFC port configuration params */
453  /* NIG */
462  /* BRB */
465 };
466 
467 
468 /* ETS port configuration params */
471 };
472 
479 };
480 
484 };
485 
488  union {
491  } params;
492 };
493 
495  u8 num_of_cos; /* Number of valid COS entries*/
497 };
498 
499 /* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
500  * when link is already up
501  */
502 int bnx2x_update_pfc(struct link_params *params,
503  struct link_vars *vars,
504  struct bnx2x_nig_brb_pfc_port_params *pfc_params);
505 
506 
507 /* Used to configure the ETS to disable */
508 int bnx2x_ets_disabled(struct link_params *params,
509  struct link_vars *vars);
510 
511 /* Used to configure the ETS to BW limited */
512 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
513  const u32 cos1_bw);
514 
515 /* Used to configure the ETS to strict */
516 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
517 
518 
519 /* Configure the COS to ETS according to BW and SP settings.*/
520 int bnx2x_ets_e3b0_config(const struct link_params *params,
521  const struct link_vars *vars,
522  struct bnx2x_ets_params *ets_params);
523 /* Read pfc statistic*/
524 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
525  u32 pfc_frames_sent[2],
526  u32 pfc_frames_received[2]);
527 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
528  u32 chip_id, u32 shmem_base, u32 shmem2_base,
529  u8 port);
530 
531 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
532  struct link_params *params);
533 
534 void bnx2x_period_func(struct link_params *params, struct link_vars *vars);
535 
536 int bnx2x_check_half_open_conn(struct link_params *params,
537  struct link_vars *vars, u8 notify);
538 #endif /* BNX2X_LINK_H */