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board-dt-tegra20.c
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1 /*
2  * nVidia Tegra device tree board support
3  *
4  * Copyright (C) 2010 Secret Lab Technologies, Ltd.
5  * Copyright (C) 2010 Google, Inc.
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  */
17 
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of.h>
26 #include <linux/of_address.h>
27 #include <linux/of_fdt.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_platform.h>
30 #include <linux/pda_power.h>
32 #include <linux/io.h>
33 #include <linux/i2c.h>
34 #include <linux/i2c-tegra.h>
36 
37 #include <asm/hardware/gic.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
41 #include <asm/setup.h>
42 
43 #include <mach/iomap.h>
44 #include <mach/irqs.h>
45 
46 #include "board.h"
47 #include "clock.h"
48 #include "common.h"
49 
51  .operating_mode = TEGRA_USB_OTG,
52  .power_down_on_bus_suspend = 1,
53  .vbus_gpio = -1,
54 };
55 
57  .reset_gpio = -1,
58  .clk = "cdev2",
59 };
60 
62  .phy_config = &tegra_ehci2_ulpi_phy_config,
63  .operating_mode = TEGRA_USB_HOST,
64  .power_down_on_bus_suspend = 1,
65  .vbus_gpio = -1,
66 };
67 
69  .operating_mode = TEGRA_USB_HOST,
70  .power_down_on_bus_suspend = 1,
71  .vbus_gpio = -1,
72 };
73 
74 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
75  OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
76  OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
77  OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
78  OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, "sdhci-tegra.3", NULL),
79  OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL),
80  OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL),
81  OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
82  OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
83  OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra20-i2s.0", NULL),
84  OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra20-i2s.1", NULL),
85  OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra20-das", NULL),
86  OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
87  &tegra_ehci1_pdata),
88  OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
89  &tegra_ehci2_pdata),
90  OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
91  &tegra_ehci3_pdata),
92  OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
93  OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
94  {}
95 };
96 
97 static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
98  /* name parent rate enabled */
99  { "uarta", "pll_p", 216000000, true },
100  { "uartd", "pll_p", 216000000, true },
101  { "usbd", "clk_m", 12000000, false },
102  { "usb2", "clk_m", 12000000, false },
103  { "usb3", "clk_m", 12000000, false },
104  { "pll_a", "pll_p_out1", 56448000, true },
105  { "pll_a_out0", "pll_a", 11289600, true },
106  { "cdev1", NULL, 0, true },
107  { "i2s1", "pll_a_out0", 11289600, false},
108  { "i2s2", "pll_a_out0", 11289600, false},
109  { NULL, NULL, 0, 0},
110 };
111 
112 static void __init tegra_dt_init(void)
113 {
114  tegra_clk_init_from_table(tegra_dt_clk_init_table);
115 
116  /*
117  * Finished with the static registrations now; fill in the missing
118  * devices
119  */
120  of_platform_populate(NULL, of_default_bus_match_table,
121  tegra20_auxdata_lookup, NULL);
122 }
123 
124 static void __init trimslice_init(void)
125 {
126 #ifdef CONFIG_TEGRA_PCI
127  int ret;
128 
129  ret = tegra_pcie_init(true, true);
130  if (ret)
131  pr_err("tegra_pci_init() failed: %d\n", ret);
132 #endif
133 }
134 
135 static void __init harmony_init(void)
136 {
137 #ifdef CONFIG_TEGRA_PCI
138  int ret;
139 
140  ret = harmony_pcie_init();
141  if (ret)
142  pr_err("harmony_pcie_init() failed: %d\n", ret);
143 #endif
144 }
145 
146 static void __init paz00_init(void)
147 {
149 }
150 
151 static struct {
152  char *machine;
154 } board_init_funcs[] = {
155  { "compulab,trimslice", trimslice_init },
156  { "nvidia,harmony", harmony_init },
157  { "compal,paz00", paz00_init },
158 };
159 
160 static void __init tegra_dt_init_late(void)
161 {
162  int i;
163 
164  tegra_init_late();
165 
166  for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) {
167  if (of_machine_is_compatible(board_init_funcs[i].machine)) {
168  board_init_funcs[i].init();
169  break;
170  }
171  }
172 }
173 
174 static const char *tegra20_dt_board_compat[] = {
175  "nvidia,tegra20",
176  NULL
177 };
178 
179 DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
181  .smp = smp_ops(tegra_smp_ops),
182  .init_early = tegra20_init_early,
183  .init_irq = tegra_dt_init_irq,
184  .handle_irq = gic_handle_irq,
185  .timer = &tegra_sys_timer,
186  .init_machine = tegra_dt_init,
187  .init_late = tegra_dt_init_late,
189  .dt_compat = tegra20_dt_board_compat,