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Linux Kernel
3.7.1
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#include <linux/clk-provider.h>#include <linux/clkdev.h>#include <linux/list.h>#include <mach/clk.h>Go to the source code of this file.
Data Structures | |
| struct | clk_mux_sel |
| struct | clk_pll_freq_table |
| struct | clk_tegra |
| struct | clk_duplicate |
| struct | tegra_clk_init_table |
Macros | |
| #define | DIV_BUS (1 << 0) |
| #define | DIV_U71 (1 << 1) |
| #define | DIV_U71_FIXED (1 << 2) |
| #define | DIV_2 (1 << 3) |
| #define | DIV_U16 (1 << 4) |
| #define | PLL_FIXED (1 << 5) |
| #define | PLL_HAS_CPCON (1 << 6) |
| #define | MUX (1 << 7) |
| #define | PLLD (1 << 8) |
| #define | PERIPH_NO_RESET (1 << 9) |
| #define | PERIPH_NO_ENB (1 << 10) |
| #define | PERIPH_EMC_ENB (1 << 11) |
| #define | PERIPH_MANUAL_RESET (1 << 12) |
| #define | PLL_ALT_MISC_REG (1 << 13) |
| #define | PLLU (1 << 14) |
| #define | PLLX (1 << 15) |
| #define | MUX_PWM (1 << 16) |
| #define | MUX8 (1 << 17) |
| #define | DIV_U71_UART (1 << 18) |
| #define | MUX_CLK_OUT (1 << 19) |
| #define | PLLM (1 << 20) |
| #define | DIV_U71_INT (1 << 21) |
| #define | DIV_U71_IDLE (1 << 22) |
| #define | ENABLE_ON_INIT (1 << 28) |
| #define | PERIPH_ON_APB (1 << 29) |
| #define | to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw) |
Enumerations | |
| enum | clk_state { UNINITIALIZED = 0, ON, OFF } |
| #define to_clk_tegra | ( | _hw | ) | container_of(_hw, struct clk_tegra, hw) |
Definition at line 1115 of file tegra20_clocks_data.c.
Definition at line 1344 of file tegra30_clocks_data.c.
| void tegra_clk_init_from_table | ( | struct tegra_clk_init_table * | table | ) |
1.8.2