board-dt-tegra30.c

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/*
 * arch/arm/mach-tegra/board-dt-tegra30.c
 *
 * NVIDIA Tegra30 device tree board support
 *
 * Copyright (C) 2011 NVIDIA Corporation
 *
 * Derived from:
 *
 * arch/arm/mach-tegra/board-dt-tegra20.c
 *
 * Copyright (C) 2010 Secret Lab Technologies, Ltd.
 * Copyright (C) 2010 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_fdt.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>

#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>

#include <mach/iomap.h>

#include "board.h"
#include "clock.h"
#include "common.h"

struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
    OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
    OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),
    OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL),
    OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", NULL),
    OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL),
    OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL),
    OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
    OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
    OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
    OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
    OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
    OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
    {}
};

static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
    /* name     parent      rate        enabled */
    { "uarta",  "pll_p",    408000000,  true },
    { "pll_a",  "pll_p_out1",   564480000,  true },
    { "pll_a_out0", "pll_a",    11289600,   true },
    { "extern1",    "pll_a_out0",   0,      true },
    { "clk_out_1",  "extern1",  0,      true },
    { "i2s0",   "pll_a_out0",   11289600,   false},
    { "i2s1",   "pll_a_out0",   11289600,   false},
    { "i2s2",   "pll_a_out0",   11289600,   false},
    { "i2s3",   "pll_a_out0",   11289600,   false},
    { "i2s4",   "pll_a_out0",   11289600,   false},
    { NULL,     NULL,       0,      0},
};

static void __init tegra30_dt_init(void)
{
    tegra_clk_init_from_table(tegra_dt_clk_init_table);

    of_platform_populate(NULL, of_default_bus_match_table,
                tegra30_auxdata_lookup, NULL);
}

static const char *tegra30_dt_board_compat[] = {
    "nvidia,tegra30",
    NULL
};

DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
    .smp        = smp_ops(tegra_smp_ops),
    .map_io     = tegra_map_common_io,
    .init_early = tegra30_init_early,
    .init_irq   = tegra_dt_init_irq,
    .handle_irq = gic_handle_irq,
    .timer      = &tegra_sys_timer,
    .init_machine   = tegra30_dt_init,
    .init_late  = tegra_init_late,
    .restart    = tegra_assert_system_reset,
    .dt_compat  = tegra30_dt_board_compat,
MACHINE_END