Macros
#define	TILE_CHIP 10

#define	TILE_CHIP_REV 0

#define	CHIP_ARCH_NAME "tilegx"

#define	CHIP_ELF_TYPE() EM_TILEGX

#define	CHIP_COMPAT_ELF_TYPE() 0x2597

#define	CHIP_WORD_SIZE() 64

#define	CHIP_VA_WIDTH() 42

#define	CHIP_PA_WIDTH() 40

#define	CHIP_L2_CACHE_SIZE() 262144

#define	CHIP_L2_LOG_LINE_SIZE() 6

#define	CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())

#define	CHIP_L2_ASSOC() 8

#define	CHIP_L1D_CACHE_SIZE() 32768

#define	CHIP_L1D_LOG_LINE_SIZE() 6

#define	CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())

#define	CHIP_L1D_ASSOC() 2

#define	CHIP_L1I_CACHE_SIZE() 32768

#define	CHIP_L1I_LOG_LINE_SIZE() 6

#define	CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())

#define	CHIP_L1I_ASSOC() 2

#define	CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()

#define	CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()

#define	CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()

#define	CHIP_HAS_COHERENT_LOCAL_CACHE() 1

#define	CHIP_MAX_OUTSTANDING_VICTIMS() 128

#define	CHIP_HAS_NC_AND_NOALLOC_BITS() 1

#define	CHIP_HAS_CBOX_HOME_MAP() 1

#define	CHIP_CBOX_HOME_MAP_SIZE() 128

#define	CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1

#define	CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0

#define	CHIP_HAS_INV() 1

#define	CHIP_HAS_WH64() 1

#define	CHIP_HAS_DWORD_ALIGN() 0

#define	CHIP_PERFORMANCE_COUNTERS() 4

#define	CHIP_HAS_AUX_PERF_COUNTERS() 1

#define	CHIP_HAS_CBOX_MSR1() 0

#define	CHIP_HAS_TILE_RTF_HWM() 1

#define	CHIP_HAS_TILE_WRITE_PENDING() 0

#define	CHIP_HAS_PROC_STATUS_SPR() 1

#define	CHIP_HAS_DSTREAM_PF() 1

#define	CHIP_LOG_NUM_MSHIMS() 2

#define	CHIP_HAS_FIXED_INTVEC_BASE() 0

#define	CHIP_HAS_SPLIT_INTR_MASK() 0

#define	CHIP_HAS_SPLIT_CYCLE() 0

#define	CHIP_HAS_SN() 0

#define	CHIP_HAS_SN_PROC() 0

#define	CHIP_HAS_TILE_DMA() 0

#define	CHIP_HAS_REV1_XDN() 1

#define	CHIP_HAS_CMPEXCH() 1

#define	CHIP_HAS_MMIO() 1

#define	CHIP_HAS_POST_COMPLETION_INTERRUPTS() 1

#define	CHIP_HAS_SINGLE_STEP() 1

#define	CHIP_ITLB_ENTRIES() 16

#define	CHIP_DTLB_ENTRIES() 32

#define	CHIP_XAUI_MAF_ENTRIES() 32

#define	CHIP_HAS_MSHIM_SRCID_TABLE() 0

#define	CHIP_HAS_L1I_CLEAR_ON_RESET() 1

#define	CHIP_HAS_VALID_TILE_COORD_RESET() 1

#define	CHIP_HAS_UNIFIED_PACKET_FORMATS() 1

#define	CHIP_HAS_WRITE_REORDERING() 1

#define	CHIP_HAS_Y_X_ROUTING() 1

#define	CHIP_HAS_INTCTRL_3_STATUS_FIX() 1

#define	CHIP_HAS_BIG_ENDIAN_CONFIG() 1

#define	CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0

#define	CHIP_HAS_DIAG_TRACE_WAY() 0

#define	CHIP_HAS_MEM_STRIPE_CONFIG() 1

#define	CHIP_HAS_TLB_PERF() 1

#define	CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0

#define	CHIP_HAS_REV1_DMA_PACKETS() 1

#define	CHIP_HAS_IPI() 1

Macro Definition Documentation

#define CHIP_ARCH_NAME "tilegx"

The name of this architecture.

Definition at line 40 of file chip_tilegx.h.

#define CHIP_CBOX_HOME_MAP_SIZE ( ) 128

Number of entries in the chip's home map tables.

Definition at line 117 of file chip_tilegx.h.

#define CHIP_COMPAT_ELF_TYPE ( ) 0x2597

The alternate ELF e_machine type for binaries for this chip.

Definition at line 46 of file chip_tilegx.h.

#define CHIP_DTLB_ENTRIES ( ) 32

How many entries are present in the data TLB?

Definition at line 205 of file chip_tilegx.h.

#define CHIP_ELF_TYPE ( ) EM_TILEGX

The ELF e_machine type for binaries for this chip.

Definition at line 43 of file chip_tilegx.h.

#define CHIP_FINV_STRIDE ( ) CHIP_L2_LINE_SIZE()

Stride with which finv instructions must be issued.

Definition at line 102 of file chip_tilegx.h.

#define CHIP_FLUSH_STRIDE ( ) CHIP_L2_LINE_SIZE()

Stride with which flush instructions must be issued.

Definition at line 96 of file chip_tilegx.h.

#define CHIP_HAS_AUX_PERF_COUNTERS ( ) 1

Does this chip have auxiliary performance counters?

Definition at line 139 of file chip_tilegx.h.

#define CHIP_HAS_BIG_ENDIAN_CONFIG ( ) 1

Is it possible to configure the chip to be big-endian?

Definition at line 234 of file chip_tilegx.h.

#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN ( ) 0

Is the CACHE_RED_WAY_OVERRIDDEN SPR supported?

Definition at line 237 of file chip_tilegx.h.

#define CHIP_HAS_CBOX_HOME_MAP ( ) 1

Does the chip support hash-for-home caching?

Definition at line 114 of file chip_tilegx.h.

#define CHIP_HAS_CBOX_MSR1 ( ) 0

Is the CBOX_MSR1 SPR supported?

Definition at line 142 of file chip_tilegx.h.

#define CHIP_HAS_CMPEXCH ( ) 1

Does the chip have cmpexch and similar (fetchadd, exch, etc.)?

Definition at line 188 of file chip_tilegx.h.

#define CHIP_HAS_COHERENT_LOCAL_CACHE ( ) 1

Can the local cache coherently cache data that is homed elsewhere?

Definition at line 105 of file chip_tilegx.h.

#define CHIP_HAS_DIAG_TRACE_WAY ( ) 0

Is the DIAG_TRACE_WAY SPR supported?

Definition at line 240 of file chip_tilegx.h.

#define CHIP_HAS_DSTREAM_PF ( ) 1

Is the DSTREAM_PF SPR supported?

Definition at line 154 of file chip_tilegx.h.

#define CHIP_HAS_DWORD_ALIGN ( ) 0

Does this chip have a 'dword_align' instruction?

Definition at line 133 of file chip_tilegx.h.

#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS ( ) 1

Do uncacheable requests miss in the cache regardless of whether there is matching data?

Definition at line 121 of file chip_tilegx.h.

#define CHIP_HAS_FIXED_INTVEC_BASE ( ) 0

Are the bases of the interrupt vector areas fixed?

Definition at line 160 of file chip_tilegx.h.

#define CHIP_HAS_INTCTRL_3_STATUS_FIX ( ) 1

Is INTCTRL_3 managed with the correct MPL?

Definition at line 231 of file chip_tilegx.h.

#define CHIP_HAS_INV ( ) 1

Does the chip have an "inv" instruction that doesn't also flush?

Definition at line 127 of file chip_tilegx.h.

#define CHIP_HAS_IPI ( ) 1

Does the chip have an IPI shim?

Definition at line 255 of file chip_tilegx.h.

#define CHIP_HAS_L1I_CLEAR_ON_RESET ( ) 1

Does the L1 instruction cache clear on reset?

Definition at line 214 of file chip_tilegx.h.

#define CHIP_HAS_MEM_STRIPE_CONFIG ( ) 1

Is the MEM_STRIPE_CONFIG SPR supported?

Definition at line 243 of file chip_tilegx.h.

#define CHIP_HAS_MF_WAITS_FOR_VICTIMS ( ) 0

Does the mf instruction wait for victims?

Definition at line 124 of file chip_tilegx.h.

#define CHIP_HAS_MMIO ( ) 1

Does the chip have memory-mapped I/O support?

Definition at line 191 of file chip_tilegx.h.

#define CHIP_HAS_MSHIM_SRCID_TABLE ( ) 0

Does the memory shim have a source-id table?

Definition at line 211 of file chip_tilegx.h.

#define CHIP_HAS_NC_AND_NOALLOC_BITS ( ) 1

Does the TLB support the NC and NOALLOC bits?

Definition at line 111 of file chip_tilegx.h.

#define CHIP_HAS_POST_COMPLETION_INTERRUPTS ( ) 1

Does the chip have post-completion interrupts?

Definition at line 194 of file chip_tilegx.h.

#define CHIP_HAS_PROC_STATUS_SPR ( ) 1

Is the PROC_STATUS SPR supported?

Definition at line 151 of file chip_tilegx.h.

#define CHIP_HAS_REV1_DMA_PACKETS ( ) 1

Does the chip support rev1 DMA packets?

Definition at line 252 of file chip_tilegx.h.

#define CHIP_HAS_REV1_XDN ( ) 1

Does the chip have the second revision of the directly accessible dynamic networks? This encapsulates a number of characteristics, including the absence of the catch-all, the absence of inline message tags, the absence of support for network context-switching, and so on.

Definition at line 185 of file chip_tilegx.h.

#define CHIP_HAS_SINGLE_STEP ( ) 1

Does the chip have native single step support?

Definition at line 197 of file chip_tilegx.h.

#define CHIP_HAS_SN ( ) 0

Does the chip have a static network?

Definition at line 169 of file chip_tilegx.h.

#define CHIP_HAS_SN_PROC ( ) 0

Does the chip have a static network processor?

Definition at line 172 of file chip_tilegx.h.

#define CHIP_HAS_SPLIT_CYCLE ( ) 0

Is the cycle count split up into 2 SPRs?

Definition at line 166 of file chip_tilegx.h.

#define CHIP_HAS_SPLIT_INTR_MASK ( ) 0

Are the interrupt masks split up into 2 SPRs?

Definition at line 163 of file chip_tilegx.h.

#define CHIP_HAS_TILE_DMA ( ) 0

Size of the L1 static network processor instruction cache, in bytes. Does the chip have DMA support in each tile?

Definition at line 178 of file chip_tilegx.h.

#define CHIP_HAS_TILE_RTF_HWM ( ) 1

Is the TILE_RTF_HWM SPR supported?

Definition at line 145 of file chip_tilegx.h.

#define CHIP_HAS_TILE_WRITE_PENDING ( ) 0

Is the TILE_WRITE_PENDING SPR supported?

Definition at line 148 of file chip_tilegx.h.

#define CHIP_HAS_TLB_PERF ( ) 1

Are the TLB_PERF SPRs supported?

Definition at line 246 of file chip_tilegx.h.

#define CHIP_HAS_UNIFIED_PACKET_FORMATS ( ) 1

Does the chip have unified packet formats?

Definition at line 222 of file chip_tilegx.h.

#define CHIP_HAS_VALID_TILE_COORD_RESET ( ) 1

Does the chip come out of reset with valid coordinates on all tiles? Note that if defined, this also implies that the upper left is 1,1.

Definition at line 219 of file chip_tilegx.h.

#define CHIP_HAS_VDN_SNOOP_SHIM_CTL ( ) 0

Is the VDN_SNOOP_SHIM_CTL SPR supported?

Definition at line 249 of file chip_tilegx.h.

#define CHIP_HAS_WH64 ( ) 1

Does the chip have a "wh64" instruction?

Definition at line 130 of file chip_tilegx.h.

#define CHIP_HAS_WRITE_REORDERING ( ) 1

Does the chip support write reordering?

Definition at line 225 of file chip_tilegx.h.

#define CHIP_HAS_Y_X_ROUTING ( ) 1

Does the chip support Y-X routing as well as X-Y?

Definition at line 228 of file chip_tilegx.h.

#define CHIP_INV_STRIDE ( ) CHIP_L2_LINE_SIZE()

Stride with which inv instructions must be issued.

Definition at line 99 of file chip_tilegx.h.

#define CHIP_ITLB_ENTRIES ( ) 16

How many entries are present in the instruction TLB?

Definition at line 202 of file chip_tilegx.h.

#define CHIP_L1D_ASSOC ( ) 2

Associativity of the L1 data cache.

Definition at line 81 of file chip_tilegx.h.

#define CHIP_L1D_CACHE_SIZE ( ) 32768

Size of the L1 data cache, in bytes.

Definition at line 72 of file chip_tilegx.h.

#define CHIP_L1D_LINE_SIZE ( ) (1 << CHIP_L1D_LOG_LINE_SIZE())

Size of an L1 data cache line, in bytes.

Definition at line 78 of file chip_tilegx.h.

#define CHIP_L1D_LOG_LINE_SIZE ( ) 6

Log size of an L1 data cache line in bytes.

Definition at line 75 of file chip_tilegx.h.

#define CHIP_L1I_ASSOC ( ) 2

Associativity of the L1 instruction cache.

Definition at line 93 of file chip_tilegx.h.

#define CHIP_L1I_CACHE_SIZE ( ) 32768

Size of the L1 instruction cache, in bytes.

Definition at line 84 of file chip_tilegx.h.

#define CHIP_L1I_LINE_SIZE ( ) (1 << CHIP_L1I_LOG_LINE_SIZE())

Size of an L1 instruction cache line, in bytes.

Definition at line 90 of file chip_tilegx.h.

#define CHIP_L1I_LOG_LINE_SIZE ( ) 6

Log size of an L1 instruction cache line in bytes.

Definition at line 87 of file chip_tilegx.h.

#define CHIP_L2_ASSOC ( ) 8

Associativity of the L2 cache.

Definition at line 69 of file chip_tilegx.h.

#define CHIP_L2_CACHE_SIZE ( ) 262144

Size of the L2 cache, in bytes.

Definition at line 60 of file chip_tilegx.h.

#define CHIP_L2_LINE_SIZE ( ) (1 << CHIP_L2_LOG_LINE_SIZE())

Size of an L2 cache line, in bytes.

Definition at line 66 of file chip_tilegx.h.

#define CHIP_L2_LOG_LINE_SIZE ( ) 6

Log size of an L2 cache line in bytes.

Definition at line 63 of file chip_tilegx.h.

#define CHIP_LOG_NUM_MSHIMS ( ) 2

Log of the number of mshims we have.

Definition at line 157 of file chip_tilegx.h.

#define CHIP_MAX_OUTSTANDING_VICTIMS ( ) 128

How many simultaneous outstanding victims can the L2 cache have?

Definition at line 108 of file chip_tilegx.h.

#define CHIP_PA_WIDTH ( ) 40

How many bits are in a physical address?

Definition at line 57 of file chip_tilegx.h.

#define CHIP_PERFORMANCE_COUNTERS ( ) 4

Number of performance counters.

Definition at line 136 of file chip_tilegx.h.

#define CHIP_VA_WIDTH ( ) 42

How many bits of a virtual address are used. Extra bits must be the sign extension of the low bits.

Definition at line 54 of file chip_tilegx.h.

#define CHIP_WORD_SIZE ( ) 64

What is the native word size of the machine?

Definition at line 49 of file chip_tilegx.h.

#define CHIP_XAUI_MAF_ENTRIES ( ) 32

How many MAF entries does the XAUI shim have?

Definition at line 208 of file chip_tilegx.h.

#define TILE_CHIP 10

Specify chip version. When possible, prefer the CHIP_xxx symbols below for future-proofing. This is intended for cross-compiling; native compilation should use the predefined tile_chip symbol.

Definition at line 29 of file chip_tilegx.h.

#define TILE_CHIP_REV 0

Specify chip revision. This provides for the case of a respin of a particular chip type; the normal value for this symbol is "0". This is intended for cross-compiling; native compilation should use the predefined tile_chip_rev symbol.

Definition at line 37 of file chip_tilegx.h.

Macros

Macro Definition Documentation