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Linux Kernel
3.7.1
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#include <linux/clk.h>#include <linux/clkdev.h>#include <linux/err.h>#include <linux/init.h>#include <linux/io.h>#include <linux/of.h>#include <mach/common.h>#include <mach/mx28.h>#include "clk.h"Go to the source code of this file.
Macros | |
| #define | CLKCTRL MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR) |
| #define | PLL0CTRL0 (CLKCTRL + 0x0000) |
| #define | PLL1CTRL0 (CLKCTRL + 0x0020) |
| #define | PLL2CTRL0 (CLKCTRL + 0x0040) |
| #define | CPU (CLKCTRL + 0x0050) |
| #define | HBUS (CLKCTRL + 0x0060) |
| #define | XBUS (CLKCTRL + 0x0070) |
| #define | XTAL (CLKCTRL + 0x0080) |
| #define | SSP0 (CLKCTRL + 0x0090) |
| #define | SSP1 (CLKCTRL + 0x00a0) |
| #define | SSP2 (CLKCTRL + 0x00b0) |
| #define | SSP3 (CLKCTRL + 0x00c0) |
| #define | GPMI (CLKCTRL + 0x00d0) |
| #define | SPDIF (CLKCTRL + 0x00e0) |
| #define | EMI (CLKCTRL + 0x00f0) |
| #define | SAIF0 (CLKCTRL + 0x0100) |
| #define | SAIF1 (CLKCTRL + 0x0110) |
| #define | LCDIF (CLKCTRL + 0x0120) |
| #define | ETM (CLKCTRL + 0x0130) |
| #define | ENET (CLKCTRL + 0x0140) |
| #define | FLEXCAN (CLKCTRL + 0x0160) |
| #define | FRAC0 (CLKCTRL + 0x01b0) |
| #define | FRAC1 (CLKCTRL + 0x01c0) |
| #define | CLKSEQ (CLKCTRL + 0x01d0) |
| #define | BP_CPU_INTERRUPT_WAIT 12 |
| #define | BP_SAIF_DIV_FRAC_EN 16 |
| #define | BP_ENET_DIV_TIME 21 |
| #define | BP_ENET_SLEEP 31 |
| #define | BP_CLKSEQ_BYPASS_SAIF0 0 |
| #define | BP_CLKSEQ_BYPASS_SSP0 3 |
| #define | BP_FRAC0_IO1FRAC 16 |
| #define | BP_FRAC0_IO0FRAC 24 |
| #define | DIGCTRL MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR) |
| #define | BP_SAIF_CLKMUX 10 |
Enumerations | |
| enum | imx28_clk { ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, ref_pix, ref_hsadc, ref_gpmi, saif0_sel, saif1_sel, gpmi_sel, ssp0_sel, ssp1_sel, ssp2_sel, ssp3_sel, emi_sel, etm_sel, lcdif_sel, cpu, ptp_sel, cpu_pll, cpu_xtal, hbus, xbus, ssp0_div, ssp1_div, ssp2_div, ssp3_div, gpmi_div, emi_pll, emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div, clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0, ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm, fec, can0, can1, usb0, usb1, usb0_pwr, usb1_pwr, enet_out, clk_max } |
Functions | |
| int | mxs_saif_clkmux_select (unsigned int clkmux) |
| int __init | mx28_clocks_init (void) |
| #define BP_CLKSEQ_BYPASS_SAIF0 0 |
Definition at line 51 of file clk-imx28.c.
| #define BP_CLKSEQ_BYPASS_SSP0 3 |
Definition at line 52 of file clk-imx28.c.
| #define BP_CPU_INTERRUPT_WAIT 12 |
Definition at line 47 of file clk-imx28.c.
| #define BP_ENET_DIV_TIME 21 |
Definition at line 49 of file clk-imx28.c.
| #define BP_ENET_SLEEP 31 |
Definition at line 50 of file clk-imx28.c.
| #define BP_FRAC0_IO0FRAC 24 |
Definition at line 54 of file clk-imx28.c.
| #define BP_FRAC0_IO1FRAC 16 |
Definition at line 53 of file clk-imx28.c.
| #define BP_SAIF_CLKMUX 10 |
Definition at line 57 of file clk-imx28.c.
| #define BP_SAIF_DIV_FRAC_EN 16 |
Definition at line 48 of file clk-imx28.c.
| #define CLKCTRL MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR) |
Definition at line 22 of file clk-imx28.c.
| #define CLKSEQ (CLKCTRL + 0x01d0) |
Definition at line 45 of file clk-imx28.c.
| #define CPU (CLKCTRL + 0x0050) |
Definition at line 26 of file clk-imx28.c.
| #define DIGCTRL MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR) |
Definition at line 56 of file clk-imx28.c.
| #define EMI (CLKCTRL + 0x00f0) |
Definition at line 36 of file clk-imx28.c.
| #define ENET (CLKCTRL + 0x0140) |
Definition at line 41 of file clk-imx28.c.
| #define ETM (CLKCTRL + 0x0130) |
Definition at line 40 of file clk-imx28.c.
| #define FLEXCAN (CLKCTRL + 0x0160) |
Definition at line 42 of file clk-imx28.c.
| #define FRAC0 (CLKCTRL + 0x01b0) |
Definition at line 43 of file clk-imx28.c.
| #define FRAC1 (CLKCTRL + 0x01c0) |
Definition at line 44 of file clk-imx28.c.
| #define GPMI (CLKCTRL + 0x00d0) |
Definition at line 34 of file clk-imx28.c.
| #define HBUS (CLKCTRL + 0x0060) |
Definition at line 27 of file clk-imx28.c.
| #define LCDIF (CLKCTRL + 0x0120) |
Definition at line 39 of file clk-imx28.c.
| #define PLL0CTRL0 (CLKCTRL + 0x0000) |
Definition at line 23 of file clk-imx28.c.
| #define PLL1CTRL0 (CLKCTRL + 0x0020) |
Definition at line 24 of file clk-imx28.c.
| #define PLL2CTRL0 (CLKCTRL + 0x0040) |
Definition at line 25 of file clk-imx28.c.
| #define SAIF0 (CLKCTRL + 0x0100) |
Definition at line 37 of file clk-imx28.c.
| #define SAIF1 (CLKCTRL + 0x0110) |
Definition at line 38 of file clk-imx28.c.
| #define SPDIF (CLKCTRL + 0x00e0) |
Definition at line 35 of file clk-imx28.c.
| #define SSP0 (CLKCTRL + 0x0090) |
Definition at line 30 of file clk-imx28.c.
| #define SSP1 (CLKCTRL + 0x00a0) |
Definition at line 31 of file clk-imx28.c.
| #define SSP2 (CLKCTRL + 0x00b0) |
Definition at line 32 of file clk-imx28.c.
| #define SSP3 (CLKCTRL + 0x00c0) |
Definition at line 33 of file clk-imx28.c.
| #define XBUS (CLKCTRL + 0x0070) |
Definition at line 28 of file clk-imx28.c.
| #define XTAL (CLKCTRL + 0x0080) |
Definition at line 29 of file clk-imx28.c.
| enum imx28_clk |
Definition at line 134 of file clk-imx28.c.
Definition at line 154 of file clk-imx28.c.
Definition at line 70 of file clk-imx28.c.
1.8.2