#include <linux/init.h>
#include <linux/types.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <mach/common.h>
#include "clk.h"

Macros
#define	CCGR0 0x68

#define	CCGR1 0x6c

#define	CCGR2 0x70

#define	CCGR3 0x74

#define	CCGR4 0x78

#define	CCGR5 0x7c

#define	CCGR6 0x80

#define	CCGR7 0x84

#define	CLPCR 0x54

#define	BP_CLPCR_LPM 0

#define	BM_CLPCR_LPM (0x3 << 0)

#define	BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)

#define	BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)

#define	BM_CLPCR_SBYOS (0x1 << 6)

#define	BM_CLPCR_DIS_REF_OSC (0x1 << 7)

#define	BM_CLPCR_VSTBY (0x1 << 8)

#define	BP_CLPCR_STBY_COUNT 9

#define	BM_CLPCR_STBY_COUNT (0x3 << 9)

#define	BM_CLPCR_COSC_PWRDOWN (0x1 << 11)

#define	BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)

#define	BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)

#define	BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)

#define	BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)

#define	BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)

#define	BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)

#define	BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)

#define	BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)

#define	BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)

#define	BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)

Enumerations
enum	mx6q_clks { dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m, pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw, periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel, esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel, gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel, ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel, ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel, usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel, emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2, periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf, asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root, gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf, ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre, ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf, ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf, usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf, emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf, mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial, can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet, esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch, gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, clk_max }

Functions
void __init	imx6q_clock_map_io (void)

int	imx6q_set_lpm (enum mxc_cpu_pwr_mode mode)

int __init	mx6q_clocks_init (void)

Macro Definition Documentation

#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)

Definition at line 38 of file clk-imx6q.c.

#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)

Definition at line 47 of file clk-imx6q.c.

#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)

Definition at line 48 of file clk-imx6q.c.

#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)

Definition at line 37 of file clk-imx6q.c.

#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)

Definition at line 44 of file clk-imx6q.c.

#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)

Definition at line 40 of file clk-imx6q.c.

#define BM_CLPCR_LPM (0x3 << 0)

Definition at line 36 of file clk-imx6q.c.

#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)

Definition at line 49 of file clk-imx6q.c.

#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)

Definition at line 50 of file clk-imx6q.c.

#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)

Definition at line 51 of file clk-imx6q.c.

#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)

Definition at line 52 of file clk-imx6q.c.

#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)

Definition at line 54 of file clk-imx6q.c.

#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)

Definition at line 53 of file clk-imx6q.c.

#define BM_CLPCR_SBYOS (0x1 << 6)

Definition at line 39 of file clk-imx6q.c.

#define BM_CLPCR_STBY_COUNT (0x3 << 9)

Definition at line 43 of file clk-imx6q.c.

#define BM_CLPCR_VSTBY (0x1 << 8)

Definition at line 41 of file clk-imx6q.c.

#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)

Definition at line 46 of file clk-imx6q.c.

#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)

Definition at line 45 of file clk-imx6q.c.

#define BP_CLPCR_LPM 0

Definition at line 35 of file clk-imx6q.c.

#define BP_CLPCR_STBY_COUNT 9

Definition at line 42 of file clk-imx6q.c.

#define CCGR0 0x68

Definition at line 25 of file clk-imx6q.c.

#define CCGR1 0x6c

Definition at line 26 of file clk-imx6q.c.

#define CCGR2 0x70

Definition at line 27 of file clk-imx6q.c.

#define CCGR3 0x74

Definition at line 28 of file clk-imx6q.c.

#define CCGR4 0x78

Definition at line 29 of file clk-imx6q.c.

#define CCGR5 0x7c

Definition at line 30 of file clk-imx6q.c.

#define CCGR6 0x80

Definition at line 31 of file clk-imx6q.c.

#define CCGR7 0x84

Definition at line 32 of file clk-imx6q.c.

#define CLPCR 0x54

Definition at line 34 of file clk-imx6q.c.

Enumeration Type Documentation

enum mx6q_clks

Enumerator:

dummy
ckil
ckih
osc
pll2_pfd0_352m
pll2_pfd1_594m
pll2_pfd2_396m
pll3_pfd0_720m
pll3_pfd1_540m
pll3_pfd2_508m
pll3_pfd3_454m
pll2_198m
pll3_120m
pll3_80m
pll3_60m
twd
step
pll1_sw
periph_pre
periph2_pre
periph_clk2_sel
periph2_clk2_sel
axi_sel
esai_sel
asrc_sel
spdif_sel
gpu2d_axi
gpu3d_axi
gpu2d_core_sel
gpu3d_core_sel
gpu3d_shader_sel
ipu1_sel
ipu2_sel
ldb_di0_sel
ldb_di1_sel
ipu1_di0_pre_sel
ipu1_di1_pre_sel
ipu2_di0_pre_sel
ipu2_di1_pre_sel
ipu1_di0_sel
ipu1_di1_sel
ipu2_di0_sel
ipu2_di1_sel
hsi_tx_sel
pcie_axi_sel
ssi1_sel
ssi2_sel
ssi3_sel
usdhc1_sel
usdhc2_sel
usdhc3_sel
usdhc4_sel
enfc_sel
emi_sel
emi_slow_sel
vdo_axi_sel
vpu_axi_sel
cko1_sel
periph
periph2
periph_clk2
periph2_clk2
ipg
ipg_per
esai_pred
esai_podf
asrc_pred
asrc_podf
spdif_pred
spdif_podf
can_root
ecspi_root
gpu2d_core_podf
gpu3d_core_podf
gpu3d_shader
ipu1_podf
ipu2_podf
ldb_di0_podf
ldb_di1_podf
ipu1_di0_pre
ipu1_di1_pre
ipu2_di0_pre
ipu2_di1_pre
hsi_tx_podf
ssi1_pred
ssi1_podf
ssi2_pred
ssi2_podf
ssi3_pred
ssi3_podf
uart_serial_podf
usdhc1_podf
usdhc2_podf
usdhc3_podf
usdhc4_podf
enfc_pred
enfc_podf
emi_podf
emi_slow_podf
vpu_axi_podf
cko1_podf
axi
mmdc_ch0_axi_podf
mmdc_ch1_axi_podf
arm
ahb
apbh_dma
asrc
can1_ipg
can1_serial
can2_ipg
can2_serial
ecspi1
ecspi2
ecspi3
ecspi4
ecspi5
enet
esai
gpt_ipg
gpt_ipg_per
gpu2d_core
gpu3d_core
hdmi_iahb
hdmi_isfr
i2c1
i2c2
i2c3
iim
enfc
ipu1
ipu1_di0
ipu1_di1
ipu2
ipu2_di0
ldb_di0
ldb_di1
ipu2_di1
hsi_tx
mlb
mmdc_ch0_axi
mmdc_ch1_axi
ocram
openvg_axi
pcie_axi
pwm1
pwm2
pwm3
pwm4
per1_bch
gpmi_bch_apb
gpmi_bch
gpmi_io
gpmi_apb
sata
sdma
spba
ssi1
ssi2
ssi3
uart_ipg
uart_serial
usboh3
usdhc1
usdhc2
usdhc3
usdhc4
vdo_axi
vpu_axi
cko1
pll1_sys
pll2_bus
pll3_usb_otg
pll4_audio
pll5_video
pll6_mlb
pll7_usb_host
pll8_enet
ssi1_ipg
ssi2_ipg
ssi3_ipg
rom
usbphy1
usbphy2
ldb_di0_div_3_5
ldb_di1_div_3_5
clk_max

Definition at line 125 of file clk-imx6q.c.

Function Documentation

void __init imx6q_clock_map_io ( void )

Definition at line 58 of file clk-imx6q.c.

int imx6q_set_lpm ( enum mxc_cpu_pwr_mode mode )

Definition at line 60 of file clk-imx6q.c.

int __init mx6q_clocks_init ( void )

Definition at line 166 of file clk-imx6q.c.

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation