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clk-imx6q.c
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1 /*
2  * Copyright 2011 Freescale Semiconductor, Inc.
3  * Copyright 2011 Linaro Ltd.
4  *
5  * The code contained herein is licensed under the GNU General Public
6  * License. You may obtain a copy of the GNU General Public License
7  * Version 2 or later at the following locations:
8  *
9  * http://www.opensource.org/licenses/gpl-license.html
10  * http://www.gnu.org/copyleft/gpl.html
11  */
12 
13 #include <linux/init.h>
14 #include <linux/types.h>
15 #include <linux/clk.h>
16 #include <linux/clkdev.h>
17 #include <linux/err.h>
18 #include <linux/io.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <mach/common.h>
23 #include "clk.h"
24 
25 #define CCGR0 0x68
26 #define CCGR1 0x6c
27 #define CCGR2 0x70
28 #define CCGR3 0x74
29 #define CCGR4 0x78
30 #define CCGR5 0x7c
31 #define CCGR6 0x80
32 #define CCGR7 0x84
33 
34 #define CLPCR 0x54
35 #define BP_CLPCR_LPM 0
36 #define BM_CLPCR_LPM (0x3 << 0)
37 #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
38 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
39 #define BM_CLPCR_SBYOS (0x1 << 6)
40 #define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
41 #define BM_CLPCR_VSTBY (0x1 << 8)
42 #define BP_CLPCR_STBY_COUNT 9
43 #define BM_CLPCR_STBY_COUNT (0x3 << 9)
44 #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
45 #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
46 #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
47 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
48 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
49 #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
50 #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
51 #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
52 #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
53 #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
54 #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
55 
56 static void __iomem *ccm_base;
57 
58 void __init imx6q_clock_map_io(void) { }
59 
60 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
61 {
62  u32 val = readl_relaxed(ccm_base + CLPCR);
63 
64  val &= ~BM_CLPCR_LPM;
65  switch (mode) {
66  case WAIT_CLOCKED:
67  break;
68  case WAIT_UNCLOCKED:
69  val |= 0x1 << BP_CLPCR_LPM;
70  break;
71  case STOP_POWER_ON:
72  val |= 0x2 << BP_CLPCR_LPM;
73  break;
74  case WAIT_UNCLOCKED_POWER_OFF:
75  val |= 0x1 << BP_CLPCR_LPM;
76  val &= ~BM_CLPCR_VSTBY;
77  val &= ~BM_CLPCR_SBYOS;
78  break;
79  case STOP_POWER_OFF:
80  val |= 0x2 << BP_CLPCR_LPM;
81  val |= 0x3 << BP_CLPCR_STBY_COUNT;
82  val |= BM_CLPCR_VSTBY;
83  val |= BM_CLPCR_SBYOS;
84  break;
85  default:
86  return -EINVAL;
87  }
88 
89  writel_relaxed(val, ccm_base + CLPCR);
90 
91  return 0;
92 }
93 
94 static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
95 static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
96 static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
97 static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", };
98 static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
99 static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
100 static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
101 static const char *audio_sels[] = { "pll4_audio", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
102 static const char *gpu_axi_sels[] = { "axi", "ahb", };
103 static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
104 static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
105 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };
106 static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
107 static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
108 static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
109 static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
110 static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
111 static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
112 static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
113 static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", };
114 static const char *pcie_axi_sels[] = { "axi", "ahb", };
115 static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio", };
116 static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
117 static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
118 static const char *emi_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
119 static const char *vdo_axi_sels[] = { "axi", "ahb", };
120 static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
121 static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video",
122  "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
123  "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio", };
124 
125 enum mx6q_clks {
126  dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
127  pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
128  pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
129  periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
130  esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
131  gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
132  ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
133  ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
134  ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
135  usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
136  emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
137  periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
138  asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
139  gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
140  ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
141  ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
142  ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
143  usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
144  emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
145  mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
146  can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
147  esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
148  hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
149  ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
150  mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
151  gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
152  ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
153  usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
154  pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
155  ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
156  clk_max
157 };
158 
159 static struct clk *clk[clk_max];
160 static struct clk_onecell_data clk_data;
161 
162 static enum mx6q_clks const clks_init_on[] __initconst = {
163  mmdc_ch0_axi, rom,
164 };
165 
166 int __init mx6q_clocks_init(void)
167 {
168  struct device_node *np;
169  void __iomem *base;
170  int i, irq;
171 
172  clk[dummy] = imx_clk_fixed("dummy", 0);
173 
174  /* retrieve the freqency of fixed clocks from device tree */
175  for_each_compatible_node(np, NULL, "fixed-clock") {
176  u32 rate;
177  if (of_property_read_u32(np, "clock-frequency", &rate))
178  continue;
179 
180  if (of_device_is_compatible(np, "fsl,imx-ckil"))
181  clk[ckil] = imx_clk_fixed("ckil", rate);
182  else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
183  clk[ckih] = imx_clk_fixed("ckih", rate);
184  else if (of_device_is_compatible(np, "fsl,imx-osc"))
185  clk[osc] = imx_clk_fixed("osc", rate);
186  }
187 
188  np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
189  base = of_iomap(np, 0);
190  WARN_ON(!base);
191 
192  /* type name parent_name base gate_mask div_mask */
193  clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x2000, 0x7f);
194  clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x2000, 0x1);
195  clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x2000, 0x3);
196  clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x2000, 0x7f);
197  clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x2000, 0x7f);
198  clk[pll6_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll6_mlb", "osc", base + 0xd0, 0x2000, 0x0);
199  clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3);
200  clk[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3);
201 
202  clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
203  clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
204 
205  /* name parent_name reg idx */
206  clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
207  clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
208  clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
209  clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
210  clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
211  clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
212  clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
213 
214  /* name parent_name mult div */
215  clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
216  clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
217  clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
218  clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
219  clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
220 
221  np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
222  base = of_iomap(np, 0);
223  WARN_ON(!base);
224  ccm_base = base;
225 
226  /* name reg shift width parent_names num_parents */
227  clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
228  clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
229  clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
230  clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
231  clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
232  clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
233  clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
234  clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
235  clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
236  clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
237  clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
238  clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
239  clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
240  clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
241  clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
242  clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
243  clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
244  clk[ldb_di0_sel] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
245  clk[ldb_di1_sel] = imx_clk_mux("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
246  clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
247  clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
248  clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
249  clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
250  clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
251  clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
252  clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
253  clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
254  clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
255  clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
256  clk[ssi1_sel] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
257  clk[ssi2_sel] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
258  clk[ssi3_sel] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
259  clk[usdhc1_sel] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
260  clk[usdhc2_sel] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
261  clk[usdhc3_sel] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
262  clk[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
263  clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
264  clk[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels));
265  clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels));
266  clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
267  clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
268  clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
269 
270  /* name reg shift width busy: reg, shift parent_names num_parents */
271  clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
272  clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
273 
274  /* name parent_name reg shift width */
275  clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
276  clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
277  clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
278  clk[ipg_per] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6);
279  clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
280  clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
281  clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
282  clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
283  clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
284  clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
285  clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6);
286  clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
287  clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
288  clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
289  clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
290  clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
291  clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
292  clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
293  clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1);
294  clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
295  clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1);
296  clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
297  clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
298  clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
299  clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
300  clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
301  clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
302  clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
303  clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
304  clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
305  clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
306  clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
307  clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
308  clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
309  clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
310  clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
311  clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
312  clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
313  clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
314  clk[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3);
315  clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3);
316  clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
317  clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
318 
319  /* name parent_name reg shift width busy: reg, shift */
320  clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
321  clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
322  clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
323  clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
324  clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
325 
326  /* name parent_name reg shift */
327  clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
328  clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
329  clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
330  clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
331  clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
332  clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
333  clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
334  clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
335  clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
336  clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
337  clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
338  clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
339  clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16);
340  clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
341  clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
342  clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
343  clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
344  clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
345  clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
346  clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
347  clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
348  clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
349  clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
350  clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
351  clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
352  clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
353  clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
354  clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
355  clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
356  clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
357  clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
358  clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
359  clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
360  clk[mlb] = imx_clk_gate2("mlb", "pll6_mlb", base + 0x74, 18);
361  clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
362  clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
363  clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
364  clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
365  clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
366  clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
367  clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
368  clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
369  clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
370  clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
371  clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
372  clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
373  clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
374  clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
375  clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
376  clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
377  clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
378  clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
379  clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
380  clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
381  clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
382  clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
383  clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
384  clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
385  clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
386  clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
387  clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
388  clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
389  clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
390  clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
391  clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
392 
393  for (i = 0; i < ARRAY_SIZE(clk); i++)
394  if (IS_ERR(clk[i]))
395  pr_err("i.MX6q clk %d: register failed with %ld\n",
396  i, PTR_ERR(clk[i]));
397 
398  clk_data.clks = clk;
399  clk_data.clk_num = ARRAY_SIZE(clk);
400  of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
401 
402  clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
403  clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
404  clk_register_clkdev(clk[twd], NULL, "smp_twd");
405  clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
406  clk_register_clkdev(clk[ahb], "ahb", NULL);
407  clk_register_clkdev(clk[cko1], "cko1", NULL);
408 
409  /*
410  * The gpmi needs 100MHz frequency in the EDO/Sync mode,
411  * We can not get the 100MHz from the pll2_pfd0_352m.
412  * So choose pll2_pfd2_396m as enfc_sel's parent.
413  */
414  clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
415 
416  for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
417  clk_prepare_enable(clk[clks_init_on[i]]);
418 
419  np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
420  base = of_iomap(np, 0);
421  WARN_ON(!base);
422  irq = irq_of_parse_and_map(np, 0);
423  mxc_timer_init(base, irq);
424 
425  return 0;
426 }
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