#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/gameport.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <sound/core.h>
#include <sound/info.h>
#include <sound/control.h>
#include <sound/pcm.h>
#include <sound/rawmidi.h>
#include <sound/mpu401.h>
#include <sound/opl3.h>
#include <sound/sb.h>
#include <sound/asoundef.h>
#include <sound/initval.h>

Data Structures
struct	cmipci_pcm

struct	cmipci_mixer_auto_switches

struct	cmipci

struct	cmipci_sb_reg

struct	cmipci_switch_args

Macros
#define	CM_REG_FUNCTRL0 0x00

#define	CM_RST_CH1 0x00080000

#define	CM_RST_CH0 0x00040000

#define	CM_CHEN1 0x00020000 /* ch1: enable */

#define	CM_CHEN0 0x00010000 /* ch0: enable */

#define	CM_PAUSE1 0x00000008 /* ch1: pause */

#define	CM_PAUSE0 0x00000004 /* ch0: pause */

#define	CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */

#define	CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */

#define	CM_REG_FUNCTRL1 0x04

#define	CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */

#define	CM_DSFC_SHIFT 13

#define	CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */

#define	CM_ASFC_SHIFT 10

#define	CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */

#define	CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */

#define	CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */

#define	CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */

#define	CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */

#define	CM_BREQ 0x00000010 /* bus master enabled */

#define	CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */

#define	CM_UART_EN 0x00000004 /* legacy UART */

#define	CM_JYSTK_EN 0x00000002 /* legacy joystick */

#define	CM_ZVPORT 0x00000001 /* ZVPORT */

#define	CM_REG_CHFORMAT 0x08

#define	CM_CHB3D5C 0x80000000 /* 5,6 channels */

#define	CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */

#define	CM_CHB3D 0x20000000 /* 4 channels */

#define	CM_CHIP_MASK1 0x1f000000

#define	CM_CHIP_037 0x01000000

#define	CM_SETLAT48 0x00800000 /* set latency timer 48h */

#define	CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */

#define	CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */

#define	CM_AC3EN1 0x00100000 /* enable AC3: model 037 */

#define	CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */

#define	CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */

#define	CM_ADCBITLEN_MASK 0x0000C000

#define	CM_ADCBITLEN_16 0x00000000

#define	CM_ADCBITLEN_15 0x00004000

#define	CM_ADCBITLEN_14 0x00008000

#define	CM_ADCBITLEN_13 0x0000C000

#define	CM_ADCDACLEN_MASK 0x00003000 /* model 037 */

#define	CM_ADCDACLEN_060 0x00000000

#define	CM_ADCDACLEN_066 0x00001000

#define	CM_ADCDACLEN_130 0x00002000

#define	CM_ADCDACLEN_280 0x00003000

#define	CM_ADCDLEN_MASK 0x00003000 /* model 039 */

#define	CM_ADCDLEN_ORIGINAL 0x00000000

#define	CM_ADCDLEN_EXTRA 0x00001000

#define	CM_ADCDLEN_24K 0x00002000

#define	CM_ADCDLEN_WEIGHT 0x00003000

#define	CM_CH1_SRATE_176K 0x00000800

#define	CM_CH1_SRATE_96K 0x00000800 /* model 055? */

#define	CM_CH1_SRATE_88K 0x00000400

#define	CM_CH0_SRATE_176K 0x00000200

#define	CM_CH0_SRATE_96K 0x00000200 /* model 055? */

#define	CM_CH0_SRATE_88K 0x00000100

#define	CM_CH0_SRATE_128K 0x00000300

#define	CM_CH0_SRATE_MASK 0x00000300

#define	CM_SPDIF_INVERSE2 0x00000080 /* model 055? */

#define	CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */

#define	CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */

#define	CM_SPDLOCKED 0x00000010

#define	CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */

#define	CM_CH1FMT_SHIFT 2

#define	CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */

#define	CM_CH0FMT_SHIFT 0

#define	CM_REG_INT_HLDCLR 0x0C

#define	CM_CHIP_MASK2 0xff000000

#define	CM_CHIP_8768 0x20000000

#define	CM_CHIP_055 0x08000000

#define	CM_CHIP_039 0x04000000

#define	CM_CHIP_039_6CH 0x01000000

#define	CM_UNKNOWN_INT_EN 0x00080000 /* ? */

#define	CM_TDMA_INT_EN 0x00040000

#define	CM_CH1_INT_EN 0x00020000

#define	CM_CH0_INT_EN 0x00010000

#define	CM_REG_INT_STATUS 0x10

#define	CM_INTR 0x80000000

#define	CM_VCO 0x08000000 /* Voice Control? CMI8738 */

#define	CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */

#define	CM_UARTINT 0x00010000

#define	CM_LTDMAINT 0x00008000

#define	CM_HTDMAINT 0x00004000

#define	CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */

#define	CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */

#define	CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */

#define	CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */

#define	CM_CH1BUSY 0x00000008

#define	CM_CH0BUSY 0x00000004

#define	CM_CHINT1 0x00000002

#define	CM_CHINT0 0x00000001

#define	CM_REG_LEGACY_CTRL 0x14

#define	CM_NXCHG 0x80000000 /* don't map base reg dword->sample */

#define	CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */

#define	CM_VMPU_330 0x00000000

#define	CM_VMPU_320 0x20000000

#define	CM_VMPU_310 0x40000000

#define	CM_VMPU_300 0x60000000

#define	CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */

#define	CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */

#define	CM_VSBSEL_220 0x00000000

#define	CM_VSBSEL_240 0x04000000

#define	CM_VSBSEL_260 0x08000000

#define	CM_VSBSEL_280 0x0C000000

#define	CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */

#define	CM_FMSEL_388 0x00000000

#define	CM_FMSEL_3C8 0x01000000

#define	CM_FMSEL_3E0 0x02000000

#define	CM_FMSEL_3E8 0x03000000

#define	CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */

#define	CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */

#define	CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */

#define	CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */

#define	CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */

#define	CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */

#define	CM_C_EECS 0x00040000

#define	CM_C_EEDI46 0x00020000

#define	CM_C_EECK46 0x00010000

#define	CM_CHB3D6C 0x00008000 /* 5.1 channels support */

#define	CM_CENTR2LIN 0x00004000 /* line-in as center out */

#define	CM_BASE2LIN 0x00002000 /* line-in as bass out */

#define	CM_EXBASEN 0x00001000 /* external bass input enable */

#define	CM_REG_MISC_CTRL 0x18

#define	CM_PWD 0x80000000 /* power down */

#define	CM_RESET 0x40000000

#define	CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */

#define	CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */

#define	CM_TXVX 0x08000000 /* model 037? */

#define	CM_N4SPK3D 0x04000000 /* copy front to rear */

#define	CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */

#define	CM_SPDIF48K 0x01000000 /* write */

#define	CM_SPATUS48K 0x01000000 /* read */

#define	CM_ENDBDAC 0x00800000 /* enable double dac */

#define	CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */

#define	CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */

#define	CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */

#define	CM_FM_EN 0x00080000 /* enable legacy FM */

#define	CM_AC3EN2 0x00040000 /* enable AC3: model 039 */

#define	CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */

#define	CM_VIDWPDSB 0x00010000 /* model 037? */

#define	CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */

#define	CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */

#define	CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */

#define	CM_VIDWPPRT 0x00002000 /* model 037? */

#define	CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */

#define	CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */

#define	CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */

#define	CM_ENCENTER 0x00000080

#define	CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */

#define	CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */

#define	CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */

#define	CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */

#define	CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */

#define	CM_UPDDMA_2048 0x00000000

#define	CM_UPDDMA_1024 0x00000004

#define	CM_UPDDMA_512 0x00000008

#define	CM_UPDDMA_256 0x0000000C

#define	CM_TWAIT_MASK 0x00000003 /* model 037 */

#define	CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */

#define	CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */

#define	CM_REG_TDMA_POSITION 0x1C

#define	CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */

#define	CM_TDMA_ADR_MASK 0x0000FFFF /* current address */

#define	CM_REG_MIXER0 0x20

#define	CM_REG_SBVR 0x20 /* write: sb16 version */

#define	CM_REG_DEV 0x20 /* read: hardware device version */

#define	CM_REG_MIXER21 0x21

#define	CM_UNKNOWN_21_MASK 0x78 /* ? */

#define	CM_X_ADPCM 0x04 /* SB16 ADPCM enable */

#define	CM_PROINV 0x02 /* SBPro left/right channel switching */

#define	CM_X_SB16 0x01 /* SB16 compatible */

#define	CM_REG_SB16_DATA 0x22

#define	CM_REG_SB16_ADDR 0x23

#define	CM_REFFREQ_XIN (31510001000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */

#define	CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */

#define	CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */

#define	CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */

#define	CM_REG_MIXER1 0x24

#define	CM_FMMUTE 0x80 /* mute FM */

#define	CM_FMMUTE_SHIFT 7

#define	CM_WSMUTE 0x40 /* mute PCM */

#define	CM_WSMUTE_SHIFT 6

#define	CM_REAR2LIN 0x20 /* lin-in -> rear line out */

#define	CM_REAR2LIN_SHIFT 5

#define	CM_REAR2FRONT 0x10 /* exchange rear/front */

#define	CM_REAR2FRONT_SHIFT 4

#define	CM_WAVEINL 0x08 /* digital wave rec. left chan */

#define	CM_WAVEINL_SHIFT 3

#define	CM_WAVEINR 0x04 /* digical wave rec. right */

#define	CM_WAVEINR_SHIFT 2

#define	CM_X3DEN 0x02 /* 3D surround enable */

#define	CM_X3DEN_SHIFT 1

#define	CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */

#define	CM_CDPLAY_SHIFT 0

#define	CM_REG_MIXER2 0x25

#define	CM_RAUXREN 0x80 /* AUX right capture */

#define	CM_RAUXREN_SHIFT 7

#define	CM_RAUXLEN 0x40 /* AUX left capture */

#define	CM_RAUXLEN_SHIFT 6

#define	CM_VAUXRM 0x20 /* AUX right mute */

#define	CM_VAUXRM_SHIFT 5

#define	CM_VAUXLM 0x10 /* AUX left mute */

#define	CM_VAUXLM_SHIFT 4

#define	CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */

#define	CM_VADMIC_SHIFT 1

#define	CM_MICGAINZ 0x01 /* mic boost */

#define	CM_MICGAINZ_SHIFT 0

#define	CM_REG_MIXER3 0x24

#define	CM_REG_AUX_VOL 0x26

#define	CM_VAUXL_MASK 0xf0

#define	CM_VAUXR_MASK 0x0f

#define	CM_REG_MISC 0x27

#define	CM_UNKNOWN_27_MASK 0xd8 /* ? */

#define	CM_XGPO1 0x20

#define	CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */

#define	CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */

#define	CM_SPDVALID 0x02 /* spdif input valid check */

#define	CM_DMAUTO 0x01 /* SB16 DMA auto detect */

#define	CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */

#define	CM_REG_EXTERN_CODEC CM_REG_AC97

#define	CM_REG_MPU_PCI 0x40

#define	CM_REG_FM_PCI 0x50

#define	CM_REG_EXTENT_IND 0xf0

#define	CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */

#define	CM_VPHONE_SHIFT 5

#define	CM_VPHOM 0x10 /* Phone mute control */

#define	CM_VSPKM 0x08 /* Speaker mute control, default high */

#define	CM_RLOOPREN 0x04 /* Rec. R-channel enable */

#define	CM_RLOOPLEN 0x02 /* Rec. L-channel enable */

#define	CM_VADMIC3 0x01 /* Mic record boost */

#define	CM_REG_PLL 0xf8

#define	CM_REG_CH0_FRAME1 0x80 /* write: base address */

#define	CM_REG_CH0_FRAME2 0x84 /* read: current address */

#define	CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */

#define	CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */

#define	CM_REG_EXT_MISC 0x90

#define	CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */

#define	CM_CHB3D8C 0x00200000 /* 7.1 channels support */

#define	CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */

#define	CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */

#define	CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */

#define	CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */

#define	CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */

#define	CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */

#define	CM_EXTENT_CODEC 0x100

#define	CM_EXTENT_MIDI 0x2

#define	CM_EXTENT_SYNTH 0x4

#define	CM_CH_PLAY 0

#define	CM_CH_CAPT 1

#define	CM_OPEN_NONE 0

#define	CM_OPEN_CH_MASK 0x01

#define	CM_OPEN_DAC 0x10

#define	CM_OPEN_ADC 0x20

#define	CM_OPEN_SPDIF 0x40

#define	CM_OPEN_MCHAN 0x80

#define	CM_OPEN_PLAYBACK (CM_CH_PLAY \| CM_OPEN_DAC)

#define	CM_OPEN_PLAYBACK2 (CM_CH_CAPT \| CM_OPEN_DAC)

#define	CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY \| CM_OPEN_DAC \| CM_OPEN_MCHAN)

#define	CM_OPEN_CAPTURE (CM_CH_CAPT \| CM_OPEN_ADC)

#define	CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY \| CM_OPEN_DAC \| CM_OPEN_SPDIF)

#define	CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT \| CM_OPEN_ADC \| CM_OPEN_SPDIF)

#define	CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K

#define	CM_PLAYBACK_SPDF CM_SPDF_0

#define	CM_CAPTURE_SPDF CM_SPDF_1

#define	CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)

#define	COMPOSE_SB_REG(lreg, rreg, lshift, rshift, mask, invert, stereo) ((lreg) \| ((rreg) << 8) \| (lshift << 16) \| (rshift << 19) \| (mask << 24) \| (invert << 22) \| (stereo << 23))

#define	CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo)

#define	CMIPCI_SB_VOL_STEREO(xname, reg, shift, mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)

#define	CMIPCI_SB_VOL_MONO(xname, reg, shift, mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)

#define	CMIPCI_SB_SW_STEREO(xname, lshift, rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)

#define	CMIPCI_SB_SW_MONO(xname, shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)

#define	CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift)

#define	CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert)

#define	CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert)

#define	CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask)

#define	CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask)

#define	snd_cmipci_uswitch_info snd_ctl_boolean_mono_info

#define	DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3)

#define	DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)

#define	DEFINE_SWITCH(sname, stype, sarg)

#define	DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)

#define	DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)

#define	SND_CMIPCI_PM_OPS NULL

Functions
	MODULE_AUTHOR ("Takashi Iwai <[email protected]>")

	MODULE_DESCRIPTION ("C-Media CMI8x38 PCI")

	MODULE_LICENSE ("GPL")

	MODULE_SUPPORTED_DEVICE ("{{C-Media,CMI8738},""{C-Media,CMI8738B},""{C-Media,CMI8338A},""{C-Media,CMI8338B}}")

	module_param_array (index, int, NULL, 0444)

	MODULE_PARM_DESC (index,"Index value for C-Media PCI soundcard.")

	module_param_array (id, charp, NULL, 0444)

	MODULE_PARM_DESC (id,"ID string for C-Media PCI soundcard.")

	module_param_array (enable, bool, NULL, 0444)

	MODULE_PARM_DESC (enable,"Enable C-Media PCI soundcard.")

	module_param_array (mpu_port, long, NULL, 0444)

	MODULE_PARM_DESC (mpu_port,"MPU-401 port.")

	module_param_array (fm_port, long, NULL, 0444)

	MODULE_PARM_DESC (fm_port,"FM port.")

	module_param_array (soft_ac3, bool, NULL, 0444)

	MODULE_PARM_DESC (soft_ac3,"Software-conversion of raw SPDIF packets (model 033 only).")

	DEFINE_BIT_SWITCH_ARG (spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0)

	DEFINE_BIT_SWITCH_ARG (spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0)

	DEFINE_BIT_SWITCH_ARG (spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0)

	DEFINE_BIT_SWITCH_ARG (spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1)

	DEFINE_BIT_SWITCH_ARG (spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0)

	DEFINE_BIT_SWITCH_ARG (spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0)

	DEFINE_BIT_SWITCH_ARG (spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1)

	DEFINE_SWITCH_ARG (spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0)

	DEFINE_BIT_SWITCH_ARG (spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1)

	DEFINE_BIT_SWITCH_ARG (spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0)

	DEFINE_BIT_SWITCH_ARG (spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0)

	DEFINE_BIT_SWITCH_ARG (spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0)

	DEFINE_SWITCH_ARG (exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0)

	DEFINE_BIT_SWITCH_ARG (fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0)

	DEFINE_SWITCH_ARG (modem, CM_REG_MISC_CTRL, CM_FLINKON\|CM_FLINKOFF, CM_FLINKON, 0, 0)

	MODULE_DEVICE_TABLE (pci, snd_cmipci_ids)

	module_pci_driver (cmipci_driver)

Macro Definition Documentation

#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */

Definition at line 123 of file cmipci.c.

#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */

Definition at line 239 of file cmipci.c.

#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */

Definition at line 380 of file cmipci.c.

#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */

Definition at line 377 of file cmipci.c.

#define CM_ADCBITLEN_13 0x0000C000

Definition at line 132 of file cmipci.c.

#define CM_ADCBITLEN_14 0x00008000

Definition at line 131 of file cmipci.c.

#define CM_ADCBITLEN_15 0x00004000

Definition at line 130 of file cmipci.c.

#define CM_ADCBITLEN_16 0x00000000

Definition at line 129 of file cmipci.c.

#define CM_ADCBITLEN_MASK 0x0000C000

Definition at line 128 of file cmipci.c.

#define CM_ADCDACLEN_060 0x00000000

Definition at line 135 of file cmipci.c.

#define CM_ADCDACLEN_066 0x00001000

Definition at line 136 of file cmipci.c.

#define CM_ADCDACLEN_130 0x00002000

Definition at line 137 of file cmipci.c.

#define CM_ADCDACLEN_280 0x00003000

Definition at line 138 of file cmipci.c.

#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */

Definition at line 134 of file cmipci.c.

#define CM_ADCDLEN_24K 0x00002000

Definition at line 143 of file cmipci.c.

#define CM_ADCDLEN_EXTRA 0x00001000

Definition at line 142 of file cmipci.c.

#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */

Definition at line 140 of file cmipci.c.

#define CM_ADCDLEN_ORIGINAL 0x00000000

Definition at line 141 of file cmipci.c.

#define CM_ADCDLEN_WEIGHT 0x00003000

Definition at line 144 of file cmipci.c.

#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */

Definition at line 282 of file cmipci.c.

#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */

Definition at line 99 of file cmipci.c.

#define CM_ASFC_SHIFT 10

Definition at line 100 of file cmipci.c.

#define CM_BASE2LIN 0x00002000 /* line-in as bass out */

Definition at line 221 of file cmipci.c.

#define CM_BREQ 0x00000010 /* bus master enabled */

Definition at line 106 of file cmipci.c.

#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */

Definition at line 215 of file cmipci.c.

#define CM_C_EECK46 0x00010000

Definition at line 218 of file cmipci.c.

#define CM_C_EECS 0x00040000

Definition at line 216 of file cmipci.c.

#define CM_C_EEDI46 0x00020000

Definition at line 217 of file cmipci.c.

#define CM_CAPTURE_SPDF CM_SPDF_1

Definition at line 424 of file cmipci.c.

#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */

Definition at line 301 of file cmipci.c.

#define CM_CDPLAY_SHIFT 0

Definition at line 302 of file cmipci.c.

#define CM_CENTR2LIN 0x00004000 /* line-in as center out */

Definition at line 220 of file cmipci.c.

#define CM_CH0_INT_EN 0x00010000

Definition at line 174 of file cmipci.c.

#define CM_CH0_SRATE_128K 0x00000300

Definition at line 152 of file cmipci.c.

#define CM_CH0_SRATE_176K 0x00000200

Definition at line 149 of file cmipci.c.

#define CM_CH0_SRATE_88K 0x00000100

Definition at line 151 of file cmipci.c.

#define CM_CH0_SRATE_96K 0x00000200 /* model 055? */

Definition at line 150 of file cmipci.c.

#define CM_CH0_SRATE_MASK 0x00000300

Definition at line 153 of file cmipci.c.

#define CM_CH0BUSY 0x00000004

Definition at line 188 of file cmipci.c.

#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */

Definition at line 162 of file cmipci.c.

#define CM_CH0FMT_SHIFT 0

Definition at line 163 of file cmipci.c.

#define CM_CH1_INT_EN 0x00020000

Definition at line 173 of file cmipci.c.

#define CM_CH1_SRATE_176K 0x00000800

Definition at line 146 of file cmipci.c.

#define CM_CH1_SRATE_88K 0x00000400

Definition at line 148 of file cmipci.c.

#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */

Definition at line 147 of file cmipci.c.

#define CM_CH1BUSY 0x00000008

Definition at line 187 of file cmipci.c.

#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */

Definition at line 160 of file cmipci.c.

#define CM_CH1FMT_SHIFT 2

Definition at line 161 of file cmipci.c.

#define CM_CH_CAPT 1

Definition at line 398 of file cmipci.c.

#define CM_CH_PLAY 0

Definition at line 397 of file cmipci.c.

#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */

Definition at line 94 of file cmipci.c.

#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */

Definition at line 93 of file cmipci.c.

#define CM_CHB3D 0x20000000 /* 4 channels */

Definition at line 116 of file cmipci.c.

#define CM_CHB3D5C 0x80000000 /* 5,6 channels */

Definition at line 114 of file cmipci.c.

#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */

Definition at line 219 of file cmipci.c.

#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */

Definition at line 378 of file cmipci.c.

#define CM_CHEN0 0x00010000 /* ch0: enable */

Definition at line 90 of file cmipci.c.

#define CM_CHEN1 0x00020000 /* ch1: enable */

Definition at line 89 of file cmipci.c.

#define CM_CHINT0 0x00000001

Definition at line 190 of file cmipci.c.

#define CM_CHINT1 0x00000002

Definition at line 189 of file cmipci.c.

#define CM_CHIP_037 0x01000000

Definition at line 119 of file cmipci.c.

#define CM_CHIP_039 0x04000000

Definition at line 169 of file cmipci.c.

#define CM_CHIP_039_6CH 0x01000000

Definition at line 170 of file cmipci.c.

#define CM_CHIP_055 0x08000000

Definition at line 168 of file cmipci.c.

#define CM_CHIP_8768 0x20000000

Definition at line 167 of file cmipci.c.

#define CM_CHIP_MASK1 0x1f000000

Definition at line 118 of file cmipci.c.

#define CM_CHIP_MASK2 0xff000000

Definition at line 166 of file cmipci.c.

#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */

Definition at line 212 of file cmipci.c.

#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */

Definition at line 156 of file cmipci.c.

#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */

Definition at line 330 of file cmipci.c.

#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */

Definition at line 97 of file cmipci.c.

#define CM_DSFC_SHIFT 13

Definition at line 98 of file cmipci.c.

#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */

Definition at line 121 of file cmipci.c.

#define CM_ENCENTER 0x00000080

Definition at line 249 of file cmipci.c.

#define CM_ENDBDAC 0x00800000 /* enable double dac */

Definition at line 234 of file cmipci.c.

#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */

Definition at line 210 of file cmipci.c.

#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */

Definition at line 199 of file cmipci.c.

#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */

Definition at line 240 of file cmipci.c.

#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */

Definition at line 244 of file cmipci.c.

#define CM_EXBASEN 0x00001000 /* external bass input enable */

Definition at line 222 of file cmipci.c.

#define CM_EXTENT_CODEC 0x100

Definition at line 389 of file cmipci.c.

#define CM_EXTENT_MIDI 0x2

Definition at line 390 of file cmipci.c.

#define CM_EXTENT_SYNTH 0x4

Definition at line 391 of file cmipci.c.

#define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */

Definition at line 252 of file cmipci.c.

#define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */

Definition at line 250 of file cmipci.c.

#define CM_FM_EN 0x00080000 /* enable legacy FM */

Definition at line 238 of file cmipci.c.

#define CM_FMMUTE 0x80 /* mute FM */

Definition at line 287 of file cmipci.c.

#define CM_FMMUTE_SHIFT 7

Definition at line 288 of file cmipci.c.

#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */

Definition at line 115 of file cmipci.c.

#define CM_FMSEL_388 0x00000000

Definition at line 206 of file cmipci.c.

#define CM_FMSEL_3C8 0x01000000

Definition at line 207 of file cmipci.c.

#define CM_FMSEL_3E0 0x02000000

Definition at line 208 of file cmipci.c.

#define CM_FMSEL_3E8 0x03000000

Definition at line 209 of file cmipci.c.

#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */

Definition at line 205 of file cmipci.c.

#define CM_HTDMAINT 0x00004000

Definition at line 182 of file cmipci.c.

#define CM_INTR 0x80000000

Definition at line 177 of file cmipci.c.

#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */

Definition at line 105 of file cmipci.c.

#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */

Definition at line 213 of file cmipci.c.

#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */

Definition at line 383 of file cmipci.c.

#define CM_JYSTK_EN 0x00000002 /* legacy joystick */

Definition at line 109 of file cmipci.c.

#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */

Definition at line 185 of file cmipci.c.

#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */

Definition at line 186 of file cmipci.c.

#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */

Definition at line 184 of file cmipci.c.

#define CM_LTDMAINT 0x00008000

Definition at line 181 of file cmipci.c.

#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */

Definition at line 243 of file cmipci.c.

#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */

Definition at line 284 of file cmipci.c.

#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */

Definition at line 179 of file cmipci.c.

#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */

Definition at line 327 of file cmipci.c.

#define CM_MICGAINZ 0x01 /* mic boost */

Definition at line 315 of file cmipci.c.

#define CM_MICGAINZ_SHIFT 0

Definition at line 316 of file cmipci.c.

#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */

Definition at line 253 of file cmipci.c.

#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */

Definition at line 247 of file cmipci.c.

#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */

Definition at line 251 of file cmipci.c.

#define CM_N4SPK3D 0x04000000 /* copy front to rear */

Definition at line 230 of file cmipci.c.

#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */

Definition at line 193 of file cmipci.c.

#define CM_OPEN_ADC 0x20

Definition at line 406 of file cmipci.c.

#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)

Definition at line 412 of file cmipci.c.

#define CM_OPEN_CH_MASK 0x01

Definition at line 404 of file cmipci.c.

#define CM_OPEN_DAC 0x10

Definition at line 405 of file cmipci.c.

#define CM_OPEN_MCHAN 0x80

Definition at line 408 of file cmipci.c.

#define CM_OPEN_NONE 0

Definition at line 403 of file cmipci.c.

#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)

Definition at line 409 of file cmipci.c.

#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)

Definition at line 410 of file cmipci.c.

#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)

Definition at line 411 of file cmipci.c.

#define CM_OPEN_SPDIF 0x40

Definition at line 407 of file cmipci.c.

#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)

Definition at line 414 of file cmipci.c.

#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)

Definition at line 413 of file cmipci.c.

#define CM_PAUSE0 0x00000004 /* ch0: pause */

Definition at line 92 of file cmipci.c.

#define CM_PAUSE1 0x00000008 /* ch1: pause */

Definition at line 91 of file cmipci.c.

#define CM_PLAYBACK_SPDF CM_SPDF_0

Definition at line 423 of file cmipci.c.

#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K

Definition at line 422 of file cmipci.c.

#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */

Definition at line 157 of file cmipci.c.

#define CM_PROINV 0x02 /* SBPro left/right channel switching */

Definition at line 275 of file cmipci.c.

#define CM_PWD 0x80000000 /* power down */

Definition at line 225 of file cmipci.c.

#define CM_RAUXLEN 0x40 /* AUX left capture */

Definition at line 307 of file cmipci.c.

#define CM_RAUXLEN_SHIFT 6

Definition at line 308 of file cmipci.c.

#define CM_RAUXREN 0x80 /* AUX right capture */

Definition at line 305 of file cmipci.c.

#define CM_RAUXREN_SHIFT 7

Definition at line 306 of file cmipci.c.

#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */

Definition at line 382 of file cmipci.c.

#define CM_REAR2FRONT 0x10 /* exchange rear/front */

Definition at line 293 of file cmipci.c.

#define CM_REAR2FRONT_SHIFT 4

Definition at line 294 of file cmipci.c.

#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */

Definition at line 291 of file cmipci.c.

#define CM_REAR2LIN_SHIFT 5

Definition at line 292 of file cmipci.c.

#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */

Definition at line 281 of file cmipci.c.

#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */

Definition at line 332 of file cmipci.c.

#define CM_REG_AUX_VOL 0x26

Definition at line 319 of file cmipci.c.

#define CM_REG_CH0_FRAME1 0x80 /* write: base address */

Definition at line 371 of file cmipci.c.

#define CM_REG_CH0_FRAME2 0x84 /* read: current address */

Definition at line 372 of file cmipci.c.

#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */

Definition at line 373 of file cmipci.c.

#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */

Definition at line 374 of file cmipci.c.

#define CM_REG_CHFORMAT 0x08

Definition at line 112 of file cmipci.c.

#define CM_REG_DEV 0x20 /* read: hardware device version */

Definition at line 270 of file cmipci.c.

#define CM_REG_EXT_MISC 0x90

Definition at line 376 of file cmipci.c.

#define CM_REG_EXTENT_IND 0xf0

Definition at line 352 of file cmipci.c.

#define CM_REG_EXTERN_CODEC CM_REG_AC97

Definition at line 337 of file cmipci.c.

#define CM_REG_FM_PCI 0x50

Definition at line 347 of file cmipci.c.

#define CM_REG_FUNCTRL0 0x00

Definition at line 86 of file cmipci.c.

#define CM_REG_FUNCTRL1 0x04

Definition at line 96 of file cmipci.c.

#define CM_REG_INT_HLDCLR 0x0C

Definition at line 165 of file cmipci.c.

#define CM_REG_INT_STATUS 0x10

Definition at line 176 of file cmipci.c.

#define CM_REG_LEGACY_CTRL 0x14

Definition at line 192 of file cmipci.c.

#define CM_REG_MISC 0x27

Definition at line 323 of file cmipci.c.

#define CM_REG_MISC_CTRL 0x18

Definition at line 224 of file cmipci.c.

#define CM_REG_MIXER0 0x20

Definition at line 268 of file cmipci.c.

#define CM_REG_MIXER1 0x24

Definition at line 286 of file cmipci.c.

#define CM_REG_MIXER2 0x25

Definition at line 304 of file cmipci.c.

#define CM_REG_MIXER21 0x21

Definition at line 272 of file cmipci.c.

#define CM_REG_MIXER3 0x24

Definition at line 318 of file cmipci.c.

#define CM_REG_MPU_PCI 0x40

Definition at line 342 of file cmipci.c.

#define CM_REG_PLL 0xf8

Definition at line 366 of file cmipci.c.

#define CM_REG_SB16_ADDR 0x23

Definition at line 279 of file cmipci.c.

#define CM_REG_SB16_DATA 0x22

Definition at line 278 of file cmipci.c.

#define CM_REG_SBVR 0x20 /* write: sb16 version */

Definition at line 269 of file cmipci.c.

#define CM_REG_TDMA_POSITION 0x1C

Definition at line 263 of file cmipci.c.

#define CM_RESET 0x40000000

Definition at line 226 of file cmipci.c.

#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */

Definition at line 358 of file cmipci.c.

#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */

Definition at line 357 of file cmipci.c.

#define CM_RST_CH0 0x00040000

Definition at line 88 of file cmipci.c.

#define CM_RST_CH1 0x00080000

Definition at line 87 of file cmipci.c.

#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)

Definition at line 456 of file cmipci.c.

#define CM_SETLAT48 0x00800000 /* set latency timer 48h */

Definition at line 120 of file cmipci.c.

#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */

Definition at line 214 of file cmipci.c.

#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */

Definition at line 227 of file cmipci.c.

#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */

Definition at line 246 of file cmipci.c.

#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */

Definition at line 381 of file cmipci.c.

#define CM_SPATUS48K 0x01000000 /* read */

Definition at line 233 of file cmipci.c.

#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */

Definition at line 125 of file cmipci.c.

#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */

Definition at line 122 of file cmipci.c.

#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */

Definition at line 379 of file cmipci.c.

#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */

Definition at line 236 of file cmipci.c.

#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */

Definition at line 211 of file cmipci.c.

#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */

Definition at line 102 of file cmipci.c.

#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */

Definition at line 101 of file cmipci.c.

#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */

Definition at line 242 of file cmipci.c.

#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */

Definition at line 103 of file cmipci.c.

#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */

Definition at line 237 of file cmipci.c.

#define CM_SPDIF48K 0x01000000 /* write */

Definition at line 232 of file cmipci.c.

#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */

Definition at line 328 of file cmipci.c.

#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */

Definition at line 155 of file cmipci.c.

#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */

Definition at line 124 of file cmipci.c.

#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */

Definition at line 248 of file cmipci.c.

#define CM_SPDLOCKED 0x00000010

Definition at line 158 of file cmipci.c.

#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */

Definition at line 104 of file cmipci.c.

#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */

Definition at line 231 of file cmipci.c.

#define CM_SPDVALID 0x02 /* spdif input valid check */

Definition at line 329 of file cmipci.c.

#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */

Definition at line 265 of file cmipci.c.

#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */

Definition at line 264 of file cmipci.c.

#define CM_TDMA_INT_EN 0x00040000

Definition at line 172 of file cmipci.c.

#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */

Definition at line 283 of file cmipci.c.

#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */

Definition at line 261 of file cmipci.c.

#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */

Definition at line 260 of file cmipci.c.

#define CM_TWAIT_MASK 0x00000003 /* model 037 */

Definition at line 259 of file cmipci.c.

#define CM_TXVX 0x08000000 /* model 037? */

Definition at line 229 of file cmipci.c.

#define CM_UART_EN 0x00000004 /* legacy UART */

Definition at line 108 of file cmipci.c.

#define CM_UARTINT 0x00010000

Definition at line 180 of file cmipci.c.

#define CM_UNKNOWN_21_MASK 0x78 /* ? */

Definition at line 273 of file cmipci.c.

#define CM_UNKNOWN_27_MASK 0xd8 /* ? */

Definition at line 324 of file cmipci.c.

#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */

Definition at line 384 of file cmipci.c.

#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */

Definition at line 171 of file cmipci.c.

#define CM_UPDDMA_1024 0x00000004

Definition at line 256 of file cmipci.c.

#define CM_UPDDMA_2048 0x00000000

Definition at line 255 of file cmipci.c.

#define CM_UPDDMA_256 0x0000000C

Definition at line 258 of file cmipci.c.

#define CM_UPDDMA_512 0x00000008

Definition at line 257 of file cmipci.c.

#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */

Definition at line 254 of file cmipci.c.

#define CM_VADMIC3 0x01 /* Mic record boost */

Definition at line 359 of file cmipci.c.

#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */

Definition at line 313 of file cmipci.c.

#define CM_VADMIC_SHIFT 1

Definition at line 314 of file cmipci.c.

#define CM_VAUXL_MASK 0xf0

Definition at line 320 of file cmipci.c.

#define CM_VAUXLM 0x10 /* AUX left mute */

Definition at line 311 of file cmipci.c.

#define CM_VAUXLM_SHIFT 4

Definition at line 312 of file cmipci.c.

#define CM_VAUXR_MASK 0x0f

Definition at line 321 of file cmipci.c.

#define CM_VAUXRM 0x20 /* AUX right mute */

Definition at line 309 of file cmipci.c.

#define CM_VAUXRM_SHIFT 5

Definition at line 310 of file cmipci.c.

#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */

Definition at line 178 of file cmipci.c.

#define CM_VIDWPDSB 0x00010000 /* model 037? */

Definition at line 241 of file cmipci.c.

#define CM_VIDWPPRT 0x00002000 /* model 037? */

Definition at line 245 of file cmipci.c.

#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */

Definition at line 228 of file cmipci.c.

#define CM_VMPU_300 0x60000000

Definition at line 198 of file cmipci.c.

#define CM_VMPU_310 0x40000000

Definition at line 197 of file cmipci.c.

#define CM_VMPU_320 0x20000000

Definition at line 196 of file cmipci.c.

#define CM_VMPU_330 0x00000000

Definition at line 195 of file cmipci.c.

#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */

Definition at line 194 of file cmipci.c.

#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */

Definition at line 107 of file cmipci.c.

#define CM_VPHOM 0x10 /* Phone mute control */

Definition at line 355 of file cmipci.c.

#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */

Definition at line 353 of file cmipci.c.

#define CM_VPHONE_SHIFT 5

Definition at line 354 of file cmipci.c.

#define CM_VSBSEL_220 0x00000000

Definition at line 201 of file cmipci.c.

#define CM_VSBSEL_240 0x04000000

Definition at line 202 of file cmipci.c.

#define CM_VSBSEL_260 0x08000000

Definition at line 203 of file cmipci.c.

#define CM_VSBSEL_280 0x0C000000

Definition at line 204 of file cmipci.c.

#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */

Definition at line 200 of file cmipci.c.

#define CM_VSPKM 0x08 /* Speaker mute control, default high */

Definition at line 356 of file cmipci.c.

#define CM_WAVEINL 0x08 /* digital wave rec. left chan */

Definition at line 295 of file cmipci.c.

#define CM_WAVEINL_SHIFT 3

Definition at line 296 of file cmipci.c.

#define CM_WAVEINR 0x04 /* digical wave rec. right */

Definition at line 297 of file cmipci.c.

#define CM_WAVEINR_SHIFT 2

Definition at line 298 of file cmipci.c.

#define CM_WSMUTE 0x40 /* mute PCM */

Definition at line 289 of file cmipci.c.

#define CM_WSMUTE_SHIFT 6

Definition at line 290 of file cmipci.c.

#define CM_X3DEN 0x02 /* 3D surround enable */

Definition at line 299 of file cmipci.c.

#define CM_X3DEN_SHIFT 1

Definition at line 300 of file cmipci.c.

#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */

Definition at line 274 of file cmipci.c.

#define CM_X_SB16 0x01 /* SB16 compatible */

Definition at line 276 of file cmipci.c.

#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */

Definition at line 235 of file cmipci.c.

#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */

Definition at line 183 of file cmipci.c.

#define CM_XGPO1 0x20

Definition at line 325 of file cmipci.c.

#define CM_ZVPORT 0x00000001 /* ZVPORT */

Definition at line 110 of file cmipci.c.

#define CMIPCI_DOUBLE	(	xname,
		left_reg,
		right_reg,
		left_shift,
		right_shift,
		mask,
		invert,
		stereo
	)

Value:

{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  .info = snd_cmipci_info_volume, \
  .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
  .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
}

Definition at line 2012 of file cmipci.c.

#define CMIPCI_MIXER_SW_MONO	(	xname,
		reg,
		shift,
		invert
	)

Value:

{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  .info = snd_cmipci_info_native_mixer, \
  .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
  .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
}

Definition at line 2185 of file cmipci.c.

#define CMIPCI_MIXER_SW_STEREO	(	xname,
		reg,
		lshift,
		rshift,
		invert
	)

Value:

{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  .info = snd_cmipci_info_native_mixer, \
  .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
  .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
}

Definition at line 2178 of file cmipci.c.

#define CMIPCI_MIXER_VOL_MONO	(	xname,
		reg,
		shift,
		mask
	)

Value:

{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  .info = snd_cmipci_info_native_mixer, \
  .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
  .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
}

Definition at line 2199 of file cmipci.c.

#define CMIPCI_MIXER_VOL_STEREO	(	xname,
		reg,
		lshift,
		rshift,
		mask
	)

Value:

{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  .info = snd_cmipci_info_native_mixer, \
  .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
  .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
}

Definition at line 2192 of file cmipci.c.

#define CMIPCI_SB_INPUT_SW	(	xname,
		left_shift,
		right_shift
	)

Value:

{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  .info = snd_cmipci_info_input_sw, \
  .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
  .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
}

Definition at line 2113 of file cmipci.c.

#define CMIPCI_SB_SW_MONO	(	xname,
		shift
	)	CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)

Definition at line 2022 of file cmipci.c.

#define CMIPCI_SB_SW_STEREO	(	xname,
		lshift,
		rshift
	)	CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)

Definition at line 2021 of file cmipci.c.

#define CMIPCI_SB_VOL_MONO	(	xname,
		reg,
		shift,
		mask
	)	CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)

Definition at line 2020 of file cmipci.c.

#define CMIPCI_SB_VOL_STEREO	(	xname,
		reg,
		shift,
		mask
	)	CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)

Definition at line 2019 of file cmipci.c.

#define COMPOSE_SB_REG	(	lreg,
		rreg,
		lshift,
		rshift,
		mask,
		invert,
		stereo
	)	((lreg) \| ((rreg) << 8) \| (lshift << 16) \| (rshift << 19) \| (mask << 24) \| (invert << 22) \| (stereo << 23))

Definition at line 2009 of file cmipci.c.

#define DEFINE_BIT_SWITCH_ARG	(	sname,
		xreg,
		xmask,
		xis_byte,
		xac3
	)	DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)

Definition at line 2433 of file cmipci.c.

#define DEFINE_CARD_SWITCH	(	sname,
		sarg
	)	DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)

Definition at line 2474 of file cmipci.c.

#define DEFINE_MIXER_SWITCH	(	sname,
		sarg
	)	DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)

Definition at line 2475 of file cmipci.c.

#define DEFINE_SWITCH	(	sname,
		stype,
		sarg
	)

Value:

{ .name = sname, \
  .iface = stype, \
  .info = snd_cmipci_uswitch_info, \
  .get = snd_cmipci_uswitch_get, \
  .put = snd_cmipci_uswitch_put, \
  .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
}

Definition at line 2465 of file cmipci.c.

#define DEFINE_SWITCH_ARG	(	sname,
		xreg,
		xmask,
		xmask_on,
		xis_byte,
		xac3
	)

Value:

static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
  .reg = xreg, \
  .mask = xmask, \
  .mask_on = xmask_on, \
  .is_byte = xis_byte, \
  .ac3_sensitive = xac3, \
}

Definition at line 2424 of file cmipci.c.

#define SND_CMIPCI_PM_OPS NULL

Definition at line 3411 of file cmipci.c.

#define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info

Definition at line 2345 of file cmipci.c.

Function Documentation

DEFINE_BIT_SWITCH_ARG	(	spdif_in_sel1	,
		CM_REG_CHFORMAT	,
		CM_SPDIF_SELECT1	,
		0	,
		0
	)

DEFINE_BIT_SWITCH_ARG	(	spdif_in_sel2	,
		CM_REG_MISC_CTRL	,
		CM_SPDIF_SELECT2	,
		0	,
		0
	)

DEFINE_BIT_SWITCH_ARG	(	spdif_enable	,
		CM_REG_LEGACY_CTRL	,
		CM_ENSPDOUT	,
		0	,
		0
	)

DEFINE_BIT_SWITCH_ARG	(	spdo2dac	,
		CM_REG_FUNCTRL1	,
		CM_SPDO2DAC	,
		0	,
		1
	)

DEFINE_BIT_SWITCH_ARG	(	spdi_valid	,
		CM_REG_MISC	,
		CM_SPDVALID	,
		1	,
		0
	)

DEFINE_BIT_SWITCH_ARG	(	spdif_copyright	,
		CM_REG_LEGACY_CTRL	,
		CM_SPDCOPYRHT	,
		0	,
		0
	)

DEFINE_BIT_SWITCH_ARG	(	spdif_dac_out	,
		CM_REG_LEGACY_CTRL	,
		CM_DAC2SPDO	,
		0	,
		1
	)

DEFINE_BIT_SWITCH_ARG	(	spdif_loop	,
		CM_REG_FUNCTRL1	,
		CM_SPDFLOOP	,
		0	,
		1
	)

DEFINE_BIT_SWITCH_ARG	(	spdi_monitor	,
		CM_REG_MIXER1	,
		CM_CDPLAY	,
		1	,
		0
	)

DEFINE_BIT_SWITCH_ARG	(	spdi_phase	,
		CM_REG_MISC	,
		CM_SPDIF_INVERSE	,
		1	,
		0
	)

DEFINE_BIT_SWITCH_ARG	(	spdi_phase2	,
		CM_REG_CHFORMAT	,
		CM_SPDIF_INVERSE2	,
		0	,
		0
	)

DEFINE_BIT_SWITCH_ARG	(	fourch	,
		CM_REG_MISC_CTRL	,
		CM_N4SPK3D	,
		0	,
		0
	)

DEFINE_SWITCH_ARG	(	spdo_5v	,
		CM_REG_MISC_CTRL	,
		CM_SPDO5V	,
		0	,
		0	,
		0
	)

DEFINE_SWITCH_ARG	(	exchange_dac	,
		CM_REG_MISC_CTRL	,
		CM_XCHGDAC	,
		CM_XCHGDAC	,
		0	,
		0
	)

DEFINE_SWITCH_ARG	(	modem	,
		CM_REG_MISC_CTRL	,
		CM_FLINKON\|	CM_FLINKOFF,
		CM_FLINKON	,
		0	,
		0
	)

MODULE_AUTHOR ( "Takashi Iwai <[email protected]>" )

MODULE_DESCRIPTION ( "C-Media CMI8x38 PCI" )

MODULE_DEVICE_TABLE	(	pci	,
		snd_cmipci_ids
	)

MODULE_LICENSE ( "GPL" )

module_param_array	(	index	,
		int	,
		NULL	,
		0444
	)

module_param_array	(	id	,
		charp	,
		NULL	,
		0444
	)

module_param_array	(	enable	,
		bool	,
		NULL	,
		0444
	)

module_param_array	(	mpu_port	,
		long	,
		NULL	,
		0444
	)

module_param_array	(	fm_port	,
		long	,
		NULL	,
		0444
	)

module_param_array	(	soft_ac3	,
		bool	,
		NULL	,
		0444
	)

MODULE_PARM_DESC	(	index	,
		"Index value for C-Media PCI soundcard."
	)

MODULE_PARM_DESC	(	id	,
		"ID string for C-Media PCI soundcard."
	)

MODULE_PARM_DESC	(	enable	,
		"Enable C-Media PCI soundcard."
	)

MODULE_PARM_DESC	(	mpu_port	,
		"MPU-401 port."
	)

MODULE_PARM_DESC	(	fm_port	,
		"FM port."
	)

MODULE_PARM_DESC	(	soft_ac3	,
		"Software-conversion of raw SPDIF packets (model 033 only)."
	)

module_pci_driver ( cmipci_driver )

MODULE_SUPPORTED_DEVICE ( "{{C-Media,CMI8738},""{C-Media,CMI8738B},""{C-Media,CMI8338A},""{C-Media,CMI8338B}}" )

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation