coh901318.h File Reference

#include <linux/device.h>
#include <linux/dmaengine.h>

Go to the source code of this file.

Data Structures
struct	coh901318_lli
struct	coh901318_params
struct	coh_dma_channel
struct	powersave
struct	coh901318_platform

Macros
#define	MAX_DMA_PACKET_SIZE_SHIFT   11
#define	MAX_DMA_PACKET_SIZE   (1 << MAX_DMA_PACKET_SIZE_SHIFT)

: ascii name of dma channel
struct coh_dma_channel - dma channel base : channel id number : number of preallocated descriptors : prio of channel, 0 low otherwise high. Parameters configuration parameters : physical address of periphal connected to channel
#define	COH901318_MOD32_MASK   (0x1F)
#define	COH901318_WORD_MASK   (0xFFFFFFFF)
#define	COH901318_INT_STATUS1   (0x0000)
#define	COH901318_INT_STATUS2   (0x0004)
#define	COH901318_TC_INT_STATUS1   (0x0008)
#define	COH901318_TC_INT_STATUS2   (0x000C)
#define	COH901318_TC_INT_CLEAR1   (0x0010)
#define	COH901318_TC_INT_CLEAR2   (0x0014)
#define	COH901318_RAW_TC_INT_STATUS1   (0x0018)
#define	COH901318_RAW_TC_INT_STATUS2   (0x001C)
#define	COH901318_BE_INT_STATUS1   (0x0020)
#define	COH901318_BE_INT_STATUS2   (0x0024)
#define	COH901318_BE_INT_CLEAR1   (0x0028)
#define	COH901318_BE_INT_CLEAR2   (0x002C)
#define	COH901318_RAW_BE_INT_STATUS1   (0x0030)
#define	COH901318_RAW_BE_INT_STATUS2   (0x0034)
#define	COH901318_CX_CFG   (0x0100)
#define	COH901318_CX_CFG_SPACING   (0x04)
#define	COH901318_CX_CFG_CH_ENABLE   (0x00000001)
#define	COH901318_CX_CFG_CH_DISABLE   (0x00000000)
#define	COH901318_CX_CFG_RM_MASK   (0x00000006)
#define	COH901318_CX_CFG_RM_MEMORY_TO_MEMORY   (0x0 << 1)
#define	COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY   (0x1 << 1)
#define	COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY   (0x1 << 1)
#define	COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY   (0x3 << 1)
#define	COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY   (0x3 << 1)
#define	COH901318_CX_CFG_LCRF_SHIFT   3
#define	COH901318_CX_CFG_LCRF_MASK   (0x000001F8)
#define	COH901318_CX_CFG_LCR_DISABLE   (0x00000000)
#define	COH901318_CX_CFG_TC_IRQ_ENABLE   (0x00000200)
#define	COH901318_CX_CFG_TC_IRQ_DISABLE   (0x00000000)
#define	COH901318_CX_CFG_BE_IRQ_ENABLE   (0x00000400)
#define	COH901318_CX_CFG_BE_IRQ_DISABLE   (0x00000000)
#define	COH901318_CX_STAT   (0x0200)
#define	COH901318_CX_STAT_SPACING   (0x04)
#define	COH901318_CX_STAT_RBE_IRQ_IND   (0x00000008)
#define	COH901318_CX_STAT_RTC_IRQ_IND   (0x00000004)
#define	COH901318_CX_STAT_ACTIVE   (0x00000002)
#define	COH901318_CX_STAT_ENABLED   (0x00000001)
#define	COH901318_CX_CTRL   (0x0400)
#define	COH901318_CX_CTRL_SPACING   (0x10)
#define	COH901318_CX_CTRL_TC_ENABLE   (0x00001000)
#define	COH901318_CX_CTRL_TC_DISABLE   (0x00000000)
#define	COH901318_CX_CTRL_TC_VALUE_MASK   (0x00000FFF)
#define	COH901318_CX_CTRL_BURST_COUNT_MASK   (0x0000E000)
#define	COH901318_CX_CTRL_BURST_COUNT_64_BYTES   (0x7 << 13)
#define	COH901318_CX_CTRL_BURST_COUNT_48_BYTES   (0x6 << 13)
#define	COH901318_CX_CTRL_BURST_COUNT_32_BYTES   (0x5 << 13)
#define	COH901318_CX_CTRL_BURST_COUNT_16_BYTES   (0x4 << 13)
#define	COH901318_CX_CTRL_BURST_COUNT_8_BYTES   (0x3 << 13)
#define	COH901318_CX_CTRL_BURST_COUNT_4_BYTES   (0x2 << 13)
#define	COH901318_CX_CTRL_BURST_COUNT_2_BYTES   (0x1 << 13)
#define	COH901318_CX_CTRL_BURST_COUNT_1_BYTE   (0x0 << 13)
#define	COH901318_CX_CTRL_SRC_BUS_SIZE_MASK   (0x00030000)
#define	COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS   (0x2 << 16)
#define	COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS   (0x1 << 16)
#define	COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS   (0x0 << 16)
#define	COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE   (0x00040000)
#define	COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE   (0x00000000)
#define	COH901318_CX_CTRL_DST_BUS_SIZE_MASK   (0x00180000)
#define	COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS   (0x2 << 19)
#define	COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS   (0x1 << 19)
#define	COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS   (0x0 << 19)
#define	COH901318_CX_CTRL_DST_ADDR_INC_ENABLE   (0x00200000)
#define	COH901318_CX_CTRL_DST_ADDR_INC_DISABLE   (0x00000000)
#define	COH901318_CX_CTRL_MASTER_MODE_MASK   (0x00C00000)
#define	COH901318_CX_CTRL_MASTER_MODE_M2R_M1W   (0x3 << 22)
#define	COH901318_CX_CTRL_MASTER_MODE_M1R_M2W   (0x2 << 22)
#define	COH901318_CX_CTRL_MASTER_MODE_M2RW   (0x1 << 22)
#define	COH901318_CX_CTRL_MASTER_MODE_M1RW   (0x0 << 22)
#define	COH901318_CX_CTRL_TCP_ENABLE   (0x01000000)
#define	COH901318_CX_CTRL_TCP_DISABLE   (0x00000000)
#define	COH901318_CX_CTRL_TC_IRQ_ENABLE   (0x02000000)
#define	COH901318_CX_CTRL_TC_IRQ_DISABLE   (0x00000000)
#define	COH901318_CX_CTRL_HSP_ENABLE   (0x04000000)
#define	COH901318_CX_CTRL_HSP_DISABLE   (0x00000000)
#define	COH901318_CX_CTRL_HSS_ENABLE   (0x08000000)
#define	COH901318_CX_CTRL_HSS_DISABLE   (0x00000000)
#define	COH901318_CX_CTRL_DDMA_MASK   (0x30000000)
#define	COH901318_CX_CTRL_DDMA_LEGACY   (0x0 << 28)
#define	COH901318_CX_CTRL_DDMA_DEMAND_DMA1   (0x1 << 28)
#define	COH901318_CX_CTRL_DDMA_DEMAND_DMA2   (0x2 << 28)
#define	COH901318_CX_CTRL_PRDD_MASK   (0x40000000)
#define	COH901318_CX_CTRL_PRDD_DEST   (0x1 << 30)
#define	COH901318_CX_CTRL_PRDD_SOURCE   (0x0 << 30)
#define	COH901318_CX_SRC_ADDR   (0x0404)
#define	COH901318_CX_SRC_ADDR_SPACING   (0x10)
#define	COH901318_CX_DST_ADDR   (0x0408)
#define	COH901318_CX_DST_ADDR_SPACING   (0x10)
#define	COH901318_CX_LNK_ADDR   (0x040C)
#define	COH901318_CX_LNK_ADDR_SPACING   (0x10)
#define	COH901318_CX_LNK_LINK_IMMEDIATE   (0x00000001)
typedef void(*	dma_access_memory_state_t )(struct device *dev, bool active)

Macro Definition Documentation

#define COH901318_BE_INT_CLEAR1   (0x0028)

Definition at line 144 of file coh901318.h.

#define COH901318_BE_INT_CLEAR2   (0x002C)

Definition at line 145 of file coh901318.h.

#define COH901318_BE_INT_STATUS1   (0x0020)

Definition at line 141 of file coh901318.h.

#define COH901318_BE_INT_STATUS2   (0x0024)

Definition at line 142 of file coh901318.h.

#define COH901318_CX_CFG   (0x0100)

Definition at line 153 of file coh901318.h.

#define COH901318_CX_CFG_BE_IRQ_DISABLE   (0x00000000)

Definition at line 174 of file coh901318.h.

#define COH901318_CX_CFG_BE_IRQ_ENABLE   (0x00000400)

Definition at line 173 of file coh901318.h.

#define COH901318_CX_CFG_CH_DISABLE   (0x00000000)

Definition at line 157 of file coh901318.h.

#define COH901318_CX_CFG_CH_ENABLE   (0x00000001)

Definition at line 156 of file coh901318.h.

#define COH901318_CX_CFG_LCR_DISABLE   (0x00000000)

Definition at line 168 of file coh901318.h.

#define COH901318_CX_CFG_LCRF_MASK   (0x000001F8)

Definition at line 167 of file coh901318.h.

#define COH901318_CX_CFG_LCRF_SHIFT   3

Definition at line 166 of file coh901318.h.

#define COH901318_CX_CFG_RM_MASK   (0x00000006)

Definition at line 159 of file coh901318.h.

#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY   (0x0 << 1)

Definition at line 160 of file coh901318.h.

#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY   (0x1 << 1)

Definition at line 162 of file coh901318.h.

#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY   (0x1 << 1)

Definition at line 161 of file coh901318.h.

#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY   (0x3 << 1)

Definition at line 163 of file coh901318.h.

#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY   (0x3 << 1)

Definition at line 164 of file coh901318.h.

#define COH901318_CX_CFG_SPACING   (0x04)

Definition at line 154 of file coh901318.h.

#define COH901318_CX_CFG_TC_IRQ_DISABLE   (0x00000000)

Definition at line 171 of file coh901318.h.

#define COH901318_CX_CFG_TC_IRQ_ENABLE   (0x00000200)

Definition at line 170 of file coh901318.h.

#define COH901318_CX_CTRL   (0x0400)

Definition at line 189 of file coh901318.h.

#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES   (0x4 << 13)

Definition at line 201 of file coh901318.h.

#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE   (0x0 << 13)

Definition at line 205 of file coh901318.h.

#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES   (0x1 << 13)

Definition at line 204 of file coh901318.h.

#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES   (0x5 << 13)

Definition at line 200 of file coh901318.h.

#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES   (0x6 << 13)

Definition at line 199 of file coh901318.h.

#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES   (0x2 << 13)

Definition at line 203 of file coh901318.h.

#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES   (0x7 << 13)

Definition at line 198 of file coh901318.h.

#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES   (0x3 << 13)

Definition at line 202 of file coh901318.h.

#define COH901318_CX_CTRL_BURST_COUNT_MASK   (0x0000E000)

Definition at line 197 of file coh901318.h.

#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1   (0x1 << 28)

Definition at line 242 of file coh901318.h.

#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2   (0x2 << 28)

Definition at line 243 of file coh901318.h.

#define COH901318_CX_CTRL_DDMA_LEGACY   (0x0 << 28)

Definition at line 241 of file coh901318.h.

#define COH901318_CX_CTRL_DDMA_MASK   (0x30000000)

Definition at line 240 of file coh901318.h.

#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE   (0x00000000)

Definition at line 221 of file coh901318.h.

#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE   (0x00200000)

Definition at line 220 of file coh901318.h.

#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS   (0x1 << 19)

Definition at line 217 of file coh901318.h.

#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS   (0x2 << 19)

Definition at line 216 of file coh901318.h.

#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS   (0x0 << 19)

Definition at line 218 of file coh901318.h.

#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK   (0x00180000)

Definition at line 215 of file coh901318.h.

#define COH901318_CX_CTRL_HSP_DISABLE   (0x00000000)

Definition at line 236 of file coh901318.h.

#define COH901318_CX_CTRL_HSP_ENABLE   (0x04000000)

Definition at line 235 of file coh901318.h.

#define COH901318_CX_CTRL_HSS_DISABLE   (0x00000000)

Definition at line 238 of file coh901318.h.

#define COH901318_CX_CTRL_HSS_ENABLE   (0x08000000)

Definition at line 237 of file coh901318.h.

#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W   (0x2 << 22)

Definition at line 225 of file coh901318.h.

#define COH901318_CX_CTRL_MASTER_MODE_M1RW   (0x0 << 22)

Definition at line 227 of file coh901318.h.

#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W   (0x3 << 22)

Definition at line 224 of file coh901318.h.

#define COH901318_CX_CTRL_MASTER_MODE_M2RW   (0x1 << 22)

Definition at line 226 of file coh901318.h.

#define COH901318_CX_CTRL_MASTER_MODE_MASK   (0x00C00000)

Definition at line 223 of file coh901318.h.

#define COH901318_CX_CTRL_PRDD_DEST   (0x1 << 30)

Definition at line 246 of file coh901318.h.

#define COH901318_CX_CTRL_PRDD_MASK   (0x40000000)

Definition at line 245 of file coh901318.h.

#define COH901318_CX_CTRL_PRDD_SOURCE   (0x0 << 30)

Definition at line 247 of file coh901318.h.

#define COH901318_CX_CTRL_SPACING   (0x10)

Definition at line 190 of file coh901318.h.

#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE   (0x00000000)

Definition at line 213 of file coh901318.h.

#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE   (0x00040000)

Definition at line 212 of file coh901318.h.

#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS   (0x1 << 16)

Definition at line 209 of file coh901318.h.

#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS   (0x2 << 16)

Definition at line 208 of file coh901318.h.

#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS   (0x0 << 16)

Definition at line 210 of file coh901318.h.

#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK   (0x00030000)

Definition at line 207 of file coh901318.h.

#define COH901318_CX_CTRL_TC_DISABLE   (0x00000000)

Definition at line 193 of file coh901318.h.

#define COH901318_CX_CTRL_TC_ENABLE   (0x00001000)

Definition at line 192 of file coh901318.h.

#define COH901318_CX_CTRL_TC_IRQ_DISABLE   (0x00000000)

Definition at line 233 of file coh901318.h.

#define COH901318_CX_CTRL_TC_IRQ_ENABLE   (0x02000000)

Definition at line 232 of file coh901318.h.

#define COH901318_CX_CTRL_TC_VALUE_MASK   (0x00000FFF)

Definition at line 195 of file coh901318.h.

#define COH901318_CX_CTRL_TCP_DISABLE   (0x00000000)

Definition at line 230 of file coh901318.h.

#define COH901318_CX_CTRL_TCP_ENABLE   (0x01000000)

Definition at line 229 of file coh901318.h.

#define COH901318_CX_DST_ADDR   (0x0408)

Definition at line 258 of file coh901318.h.

#define COH901318_CX_DST_ADDR_SPACING   (0x10)

Definition at line 259 of file coh901318.h.

#define COH901318_CX_LNK_ADDR   (0x040C)

Definition at line 264 of file coh901318.h.

#define COH901318_CX_LNK_ADDR_SPACING   (0x10)

Definition at line 265 of file coh901318.h.

#define COH901318_CX_LNK_LINK_IMMEDIATE   (0x00000001)

Definition at line 266 of file coh901318.h.

#define COH901318_CX_SRC_ADDR   (0x0404)

Definition at line 252 of file coh901318.h.

#define COH901318_CX_SRC_ADDR_SPACING   (0x10)

Definition at line 253 of file coh901318.h.

#define COH901318_CX_STAT   (0x0200)

Definition at line 179 of file coh901318.h.

#define COH901318_CX_STAT_ACTIVE   (0x00000002)

Definition at line 183 of file coh901318.h.

#define COH901318_CX_STAT_ENABLED   (0x00000001)

Definition at line 184 of file coh901318.h.

#define COH901318_CX_STAT_RBE_IRQ_IND   (0x00000008)

Definition at line 181 of file coh901318.h.

#define COH901318_CX_STAT_RTC_IRQ_IND   (0x00000004)

Definition at line 182 of file coh901318.h.

#define COH901318_CX_STAT_SPACING   (0x04)

Definition at line 180 of file coh901318.h.

#define COH901318_INT_STATUS1   (0x0000)

Definition at line 129 of file coh901318.h.

#define COH901318_INT_STATUS2   (0x0004)

Definition at line 130 of file coh901318.h.

#define COH901318_MOD32_MASK   (0x1F)

Definition at line 126 of file coh901318.h.

#define COH901318_RAW_BE_INT_STATUS1   (0x0030)

Definition at line 147 of file coh901318.h.

#define COH901318_RAW_BE_INT_STATUS2   (0x0034)

Definition at line 148 of file coh901318.h.

#define COH901318_RAW_TC_INT_STATUS1   (0x0018)

Definition at line 138 of file coh901318.h.

#define COH901318_RAW_TC_INT_STATUS2   (0x001C)

Definition at line 139 of file coh901318.h.

#define COH901318_TC_INT_CLEAR1   (0x0010)

Definition at line 135 of file coh901318.h.

#define COH901318_TC_INT_CLEAR2   (0x0014)

Definition at line 136 of file coh901318.h.

#define COH901318_TC_INT_STATUS1   (0x0008)

Definition at line 132 of file coh901318.h.

#define COH901318_TC_INT_STATUS2   (0x000C)

Definition at line 133 of file coh901318.h.

#define COH901318_WORD_MASK   (0xFFFFFFFF)

Definition at line 127 of file coh901318.h.

#define MAX_DMA_PACKET_SIZE   (1 << MAX_DMA_PACKET_SIZE_SHIFT)

Definition at line 19 of file coh901318.h.

#define MAX_DMA_PACKET_SIZE_SHIFT   11

Definition at line 18 of file coh901318.h.

Typedef Documentation

typedef void(* dma_access_memory_state_t)(struct device *dev, bool active)

dma_access_memory_state_t - register dma for memory access

: The dma device : 1 means dma intends to access memory 0 means dma wont access memory

Definition at line 77 of file coh901318.h.