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core_titan.h
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1 #ifndef __ALPHA_TITAN__H__
2 #define __ALPHA_TITAN__H__
3 
4 #include <linux/types.h>
5 #include <asm/compiler.h>
6 
7 /*
8  * TITAN is the internal names for a core logic chipset which provides
9  * memory controller and PCI/AGP access for 21264 based systems.
10  *
11  * This file is based on:
12  *
13  * Titan Chipset Engineering Specification
14  * Revision 0.12
15  * 13 July 1999
16  *
17  */
18 
19 /* XXX: Do we need to conditionalize on this? */
20 #ifdef USE_48_BIT_KSEG
21 #define TI_BIAS 0x80000000000UL
22 #else
23 #define TI_BIAS 0x10000000000UL
24 #endif
25 
26 /*
27  * CChip, DChip, and PChip registers
28  */
29 
30 typedef struct {
31  volatile unsigned long csr __attribute__((aligned(64)));
32 } titan_64;
33 
34 typedef struct {
35  titan_64 csc;
36  titan_64 mtr;
37  titan_64 misc;
38  titan_64 mpd;
39  titan_64 aar0;
40  titan_64 aar1;
41  titan_64 aar2;
42  titan_64 aar3;
43  titan_64 dim0;
44  titan_64 dim1;
45  titan_64 dir0;
46  titan_64 dir1;
47  titan_64 drir;
48  titan_64 prben;
49  titan_64 iic0;
50  titan_64 iic1;
51  titan_64 mpr0;
52  titan_64 mpr1;
53  titan_64 mpr2;
54  titan_64 mpr3;
55  titan_64 rsvd[2];
56  titan_64 ttr;
57  titan_64 tdr;
58  titan_64 dim2;
59  titan_64 dim3;
60  titan_64 dir2;
61  titan_64 dir3;
62  titan_64 iic2;
63  titan_64 iic3;
64  titan_64 pwr;
65  titan_64 reserved[17];
66  titan_64 cmonctla;
67  titan_64 cmonctlb;
68  titan_64 cmoncnt01;
69  titan_64 cmoncnt23;
70  titan_64 cpen;
71 } titan_cchip;
72 
73 typedef struct {
74  titan_64 dsc;
75  titan_64 str;
76  titan_64 drev;
77  titan_64 dsc2;
78 } titan_dchip;
79 
80 typedef struct {
81  titan_64 wsba[4];
82  titan_64 wsm[4];
83  titan_64 tba[4];
84  titan_64 pctl;
85  titan_64 plat;
86  titan_64 reserved0[2];
87  union {
88  struct {
89  titan_64 serror;
90  titan_64 serren;
91  titan_64 serrset;
92  titan_64 reserved0;
93  titan_64 gperror;
94  titan_64 gperren;
95  titan_64 gperrset;
96  titan_64 reserved1;
97  titan_64 gtlbiv;
98  titan_64 gtlbia;
99  titan_64 reserved2[2];
100  titan_64 sctl;
101  titan_64 reserved3[3];
102  } g;
103  struct {
104  titan_64 agperror;
105  titan_64 agperren;
106  titan_64 agperrset;
107  titan_64 agplastwr;
108  titan_64 aperror;
109  titan_64 aperren;
110  titan_64 aperrset;
111  titan_64 reserved0;
112  titan_64 atlbiv;
113  titan_64 atlbia;
114  titan_64 reserved1[6];
115  } a;
116  } port_specific;
117  titan_64 sprst;
118  titan_64 reserved1[31];
119 } titan_pachip_port;
120 
121 typedef struct {
122  titan_pachip_port g_port;
123  titan_pachip_port a_port;
124 } titan_pachip;
125 
126 #define TITAN_cchip ((titan_cchip *)(IDENT_ADDR+TI_BIAS+0x1A0000000UL))
127 #define TITAN_dchip ((titan_dchip *)(IDENT_ADDR+TI_BIAS+0x1B0000800UL))
128 #define TITAN_pachip0 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x180000000UL))
129 #define TITAN_pachip1 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x380000000UL))
130 extern unsigned TITAN_agp;
131 extern int TITAN_bootcpu;
132 
133 /*
134  * TITAN PA-chip Window Space Base Address register.
135  * (WSBA[0-2])
136  */
137 #define wsba_m_ena 0x1
138 #define wsba_m_sg 0x2
139 #define wsba_m_addr 0xFFF00000
140 #define wmask_k_sz1gb 0x3FF00000
141 union TPAchipWSBA {
142  struct {
143  unsigned wsba_v_ena : 1;
144  unsigned wsba_v_sg : 1;
145  unsigned wsba_v_rsvd1 : 18;
146  unsigned wsba_v_addr : 12;
147  unsigned wsba_v_rsvd2 : 32;
148  } wsba_r_bits;
149  int wsba_q_whole [2];
150 };
151 
152 /*
153  * TITAN PA-chip Control Register
154  * This definition covers both the G-Port GPCTL and the A-PORT APCTL.
155  * Bits <51:0> are the same in both cases. APCTL<63:52> are only
156  * applicable to AGP.
157  */
158 #define pctl_m_fbtb 0x00000001
159 #define pctl_m_thdis 0x00000002
160 #define pctl_m_chaindis 0x00000004
161 #define pctl_m_tgtlat 0x00000018
162 #define pctl_m_hole 0x00000020
163 #define pctl_m_mwin 0x00000040
164 #define pctl_m_arbena 0x00000080
165 #define pctl_m_prigrp 0x0000FF00
166 #define pctl_m_ppri 0x00010000
167 #define pctl_m_pcispd66 0x00020000
168 #define pctl_m_cngstlt 0x003C0000
169 #define pctl_m_ptpdesten 0x3FC00000
170 #define pctl_m_dpcen 0x40000000
171 #define pctl_m_apcen 0x0000000080000000UL
172 #define pctl_m_dcrtv 0x0000000300000000UL
173 #define pctl_m_en_stepping 0x0000000400000000UL
174 #define apctl_m_rsvd1 0x000FFFF800000000UL
175 #define apctl_m_agp_rate 0x0030000000000000UL
176 #define apctl_m_agp_sba_en 0x0040000000000000UL
177 #define apctl_m_agp_en 0x0080000000000000UL
178 #define apctl_m_rsvd2 0x0100000000000000UL
179 #define apctl_m_agp_present 0x0200000000000000UL
180 #define apctl_agp_hp_rd 0x1C00000000000000UL
181 #define apctl_agp_lp_rd 0xE000000000000000UL
182 #define gpctl_m_rsvd 0xFFFFFFF800000000UL
183 union TPAchipPCTL {
184  struct {
185  unsigned pctl_v_fbtb : 1; /* A/G [0] */
186  unsigned pctl_v_thdis : 1; /* A/G [1] */
187  unsigned pctl_v_chaindis : 1; /* A/G [2] */
188  unsigned pctl_v_tgtlat : 2; /* A/G [4:3] */
189  unsigned pctl_v_hole : 1; /* A/G [5] */
190  unsigned pctl_v_mwin : 1; /* A/G [6] */
191  unsigned pctl_v_arbena : 1; /* A/G [7] */
192  unsigned pctl_v_prigrp : 8; /* A/G [15:8] */
193  unsigned pctl_v_ppri : 1; /* A/G [16] */
194  unsigned pctl_v_pcispd66 : 1; /* A/G [17] */
195  unsigned pctl_v_cngstlt : 4; /* A/G [21:18] */
196  unsigned pctl_v_ptpdesten : 8; /* A/G [29:22] */
197  unsigned pctl_v_dpcen : 1; /* A/G [30] */
198  unsigned pctl_v_apcen : 1; /* A/G [31] */
199  unsigned pctl_v_dcrtv : 2; /* A/G [33:32] */
200  unsigned pctl_v_en_stepping :1; /* A/G [34] */
201  unsigned apctl_v_rsvd1 : 17; /* A [51:35] */
202  unsigned apctl_v_agp_rate : 2; /* A [53:52] */
203  unsigned apctl_v_agp_sba_en : 1; /* A [54] */
204  unsigned apctl_v_agp_en : 1; /* A [55] */
205  unsigned apctl_v_rsvd2 : 1; /* A [56] */
206  unsigned apctl_v_agp_present : 1; /* A [57] */
207  unsigned apctl_v_agp_hp_rd : 3; /* A [60:58] */
208  unsigned apctl_v_agp_lp_rd : 3; /* A [63:61] */
209  } pctl_r_bits;
210  unsigned int pctl_l_whole [2];
211  unsigned long pctl_q_whole;
212 };
213 
214 /*
215  * SERROR / SERREN / SERRSET
216  */
217 union TPAchipSERR {
218  struct {
219  unsigned serr_v_lost_uecc : 1; /* [0] */
220  unsigned serr_v_uecc : 1; /* [1] */
221  unsigned serr_v_cre : 1; /* [2] */
222  unsigned serr_v_nxio : 1; /* [3] */
223  unsigned serr_v_lost_cre : 1; /* [4] */
224  unsigned serr_v_rsvd0 : 10; /* [14:5] */
225  unsigned serr_v_addr : 32; /* [46:15] */
226  unsigned serr_v_rsvd1 : 5; /* [51:47] */
227  unsigned serr_v_source : 2; /* [53:52] */
228  unsigned serr_v_cmd : 2; /* [55:54] */
229  unsigned serr_v_syn : 8; /* [63:56] */
230  } serr_r_bits;
231  unsigned int serr_l_whole[2];
232  unsigned long serr_q_whole;
233 };
234 
235 /*
236  * GPERROR / APERROR / GPERREN / APERREN / GPERRSET / APERRSET
237  */
238 union TPAchipPERR {
239  struct {
240  unsigned long perr_v_lost : 1; /* [0] */
241  unsigned long perr_v_serr : 1; /* [1] */
242  unsigned long perr_v_perr : 1; /* [2] */
243  unsigned long perr_v_dcrto : 1; /* [3] */
244  unsigned long perr_v_sge : 1; /* [4] */
245  unsigned long perr_v_ape : 1; /* [5] */
246  unsigned long perr_v_ta : 1; /* [6] */
247  unsigned long perr_v_dpe : 1; /* [7] */
248  unsigned long perr_v_nds : 1; /* [8] */
249  unsigned long perr_v_iptpr : 1; /* [9] */
250  unsigned long perr_v_iptpw : 1; /* [10] */
251  unsigned long perr_v_rsvd0 : 3; /* [13:11] */
252  unsigned long perr_v_addr : 33; /* [46:14] */
253  unsigned long perr_v_dac : 1; /* [47] */
254  unsigned long perr_v_mwin : 1; /* [48] */
255  unsigned long perr_v_rsvd1 : 3; /* [51:49] */
256  unsigned long perr_v_cmd : 4; /* [55:52] */
257  unsigned long perr_v_rsvd2 : 8; /* [63:56] */
258  } perr_r_bits;
259  unsigned int perr_l_whole[2];
260  unsigned long perr_q_whole;
261 };
262 
263 /*
264  * AGPERROR / AGPERREN / AGPERRSET
265  */
266 union TPAchipAGPERR {
267  struct {
268  unsigned agperr_v_lost : 1; /* [0] */
269  unsigned agperr_v_lpqfull : 1; /* [1] */
270  unsigned apgerr_v_hpqfull : 1; /* [2] */
271  unsigned agperr_v_rescmd : 1; /* [3] */
272  unsigned agperr_v_ipte : 1; /* [4] */
273  unsigned agperr_v_ptp : 1; /* [5] */
274  unsigned agperr_v_nowindow : 1; /* [6] */
275  unsigned agperr_v_rsvd0 : 8; /* [14:7] */
276  unsigned agperr_v_addr : 32; /* [46:15] */
277  unsigned agperr_v_rsvd1 : 1; /* [47] */
278  unsigned agperr_v_dac : 1; /* [48] */
279  unsigned agperr_v_mwin : 1; /* [49] */
280  unsigned agperr_v_cmd : 3; /* [52:50] */
281  unsigned agperr_v_length : 6; /* [58:53] */
282  unsigned agperr_v_fence : 1; /* [59] */
283  unsigned agperr_v_rsvd2 : 4; /* [63:60] */
284  } agperr_r_bits;
285  unsigned int agperr_l_whole[2];
286  unsigned long agperr_q_whole;
287 };
288 /*
289  * Memory spaces:
290  * Hose numbers are assigned as follows:
291  * 0 - pachip 0 / G Port
292  * 1 - pachip 1 / G Port
293  * 2 - pachip 0 / A Port
294  * 3 - pachip 1 / A Port
295  */
296 #define TITAN_HOSE_SHIFT (33)
297 #define TITAN_HOSE(h) (((unsigned long)(h)) << TITAN_HOSE_SHIFT)
298 #define TITAN_BASE (IDENT_ADDR + TI_BIAS)
299 #define TITAN_MEM(h) (TITAN_BASE+TITAN_HOSE(h)+0x000000000UL)
300 #define _TITAN_IACK_SC(h) (TITAN_BASE+TITAN_HOSE(h)+0x1F8000000UL)
301 #define TITAN_IO(h) (TITAN_BASE+TITAN_HOSE(h)+0x1FC000000UL)
302 #define TITAN_CONF(h) (TITAN_BASE+TITAN_HOSE(h)+0x1FE000000UL)
303 
304 #define TITAN_HOSE_MASK TITAN_HOSE(3)
305 #define TITAN_IACK_SC _TITAN_IACK_SC(0) /* hack! */
306 
307 /*
308  * The canonical non-remaped I/O and MEM addresses have these values
309  * subtracted out. This is arranged so that folks manipulating ISA
310  * devices can use their familiar numbers and have them map to bus 0.
311  */
312 
313 #define TITAN_IO_BIAS TITAN_IO(0)
314 #define TITAN_MEM_BIAS TITAN_MEM(0)
315 
316 /* The IO address space is larger than 0xffff */
317 #define TITAN_IO_SPACE (TITAN_CONF(0) - TITAN_IO(0))
318 
319 /* TIG Space */
320 #define TITAN_TIG_SPACE (TITAN_BASE + 0x100000000UL)
321 
322 /* Offset between ram physical addresses and pci64 DAC bus addresses. */
323 /* ??? Just a guess. Ought to confirm it hasn't been moved. */
324 #define TITAN_DAC_OFFSET (1UL << 40)
325 
326 /*
327  * Data structure for handling TITAN machine checks:
328  */
329 #define SCB_Q_SYSERR 0x620
330 #define SCB_Q_PROCERR 0x630
331 #define SCB_Q_SYSMCHK 0x660
332 #define SCB_Q_PROCMCHK 0x670
333 #define SCB_Q_SYSEVENT 0x680 /* environmental / system management */
334 struct el_TITAN_sysdata_mcheck {
335  u64 summary; /* 0x00 */
336  u64 c_dirx; /* 0x08 */
337  u64 c_misc; /* 0x10 */
338  u64 p0_serror; /* 0x18 */
339  u64 p0_gperror; /* 0x20 */
340  u64 p0_aperror; /* 0x28 */
341  u64 p0_agperror;/* 0x30 */
342  u64 p1_serror; /* 0x38 */
343  u64 p1_gperror; /* 0x40 */
344  u64 p1_aperror; /* 0x48 */
345  u64 p1_agperror;/* 0x50 */
346 };
347 
348 /*
349  * System area for a privateer 680 environmental/system management mcheck
350  */
351 struct el_PRIVATEER_envdata_mcheck {
352  u64 summary; /* 0x00 */
353  u64 c_dirx; /* 0x08 */
354  u64 smir; /* 0x10 */
355  u64 cpuir; /* 0x18 */
356  u64 psir; /* 0x20 */
357  u64 fault; /* 0x28 */
358  u64 sys_doors; /* 0x30 */
359  u64 temp_warn; /* 0x38 */
360  u64 fan_ctrl; /* 0x40 */
361  u64 code; /* 0x48 */
362  u64 reserved; /* 0x50 */
363 };
364 
365 #ifdef __KERNEL__
366 
367 #ifndef __EXTERN_INLINE
368 #define __EXTERN_INLINE extern inline
369 #define __IO_EXTERN_INLINE
370 #endif
371 
372 /*
373  * I/O functions:
374  *
375  * TITAN, a 21??? PCI/memory support chipset for the EV6 (21264)
376  * can only use linear accesses to get at PCI/AGP memory and I/O spaces.
377  */
378 
379 /*
380  * Memory functions. all accesses are done through linear space.
381  */
382 extern void __iomem *titan_ioportmap(unsigned long addr);
383 extern void __iomem *titan_ioremap(unsigned long addr, unsigned long size);
384 extern void titan_iounmap(volatile void __iomem *addr);
385 
386 __EXTERN_INLINE int titan_is_ioaddr(unsigned long addr)
387 {
388  return addr >= TITAN_BASE;
389 }
390 
391 extern int titan_is_mmio(const volatile void __iomem *addr);
392 
393 #undef __IO_PREFIX
394 #define __IO_PREFIX titan
395 #define titan_trivial_rw_bw 1
396 #define titan_trivial_rw_lq 1
397 #define titan_trivial_io_bw 1
398 #define titan_trivial_io_lq 1
399 #define titan_trivial_iounmap 0
400 #include <asm/io_trivial.h>
401 
402 #ifdef __IO_EXTERN_INLINE
403 #undef __EXTERN_INLINE
404 #undef __IO_EXTERN_INLINE
405 #endif
406 
407 #endif /* __KERNEL__ */
408 
409 #endif /* __ALPHA_TITAN__H__ */
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