#include <asm/barrier.h>
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#define CPACC_DISABLE |
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(0 << (n * 2)) |
#define CPACC_FULL |
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(3 << (n * 2)) |
#define CPACC_SVC |
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(1 << (n * 2)) |
#define CR_B (1 << 7) /* Big endian */ |
#define CR_C (1 << 2) /* Dcache enable */ |
#define CR_EE (1 << 25) /* Exception (Big) Endian */ |
#define CR_F (1 << 10) /* Implementation defined */ |
#define CR_I (1 << 12) /* Icache enable */ |
#define CR_L (1 << 6) /* Implementation defined */ |
#define CR_L4 (1 << 15) /* LDR pc can set T bit */ |
#define CR_M (1 << 0) /* MMU enable */ |
Definition at line 9 of file cp15.h.
#define CR_R (1 << 9) /* ROM MMU protection */ |
#define CR_RR (1 << 14) /* Round Robin cache replacement */ |
#define CR_S (1 << 8) /* System MMU protection */ |
#define CR_TRE (1 << 28) /* TEX remap enable */ |
#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ |
#define CR_VE (1 << 24) /* Vectored interrupts */ |
#define CR_XP (1 << 23) /* Extended page tables */ |
#define CR_Z (1 << 11) /* Implementation defined */ |
#define vectors_high |
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(0) |
unsigned long cr_alignment |
unsigned long cr_no_alignment |