|
| #define | OpNone 0ull |
| |
| #define | OpImplicit 1ull /* No generic decode */ |
| |
| #define | OpReg 2ull /* Register */ |
| |
| #define | OpMem 3ull /* Memory */ |
| |
| #define | OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ |
| |
| #define | OpDI 5ull /* ES:DI/EDI/RDI */ |
| |
| #define | OpMem64 6ull /* Memory, 64-bit */ |
| |
| #define | OpImmUByte 7ull /* Zero-extended 8-bit immediate */ |
| |
| #define | OpDX 8ull /* DX register */ |
| |
| #define | OpCL 9ull /* CL register (for shifts) */ |
| |
| #define | OpImmByte 10ull /* 8-bit sign extended immediate */ |
| |
| #define | OpOne 11ull /* Implied 1 */ |
| |
| #define | OpImm 12ull /* Sign extended immediate */ |
| |
| #define | OpMem16 13ull /* Memory operand (16-bit). */ |
| |
| #define | OpMem32 14ull /* Memory operand (32-bit). */ |
| |
| #define | OpImmU 15ull /* Immediate operand, zero extended */ |
| |
| #define | OpSI 16ull /* SI/ESI/RSI */ |
| |
| #define | OpImmFAddr 17ull /* Immediate far address */ |
| |
| #define | OpMemFAddr 18ull /* Far address in memory */ |
| |
| #define | OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ |
| |
| #define | OpES 20ull /* ES */ |
| |
| #define | OpCS 21ull /* CS */ |
| |
| #define | OpSS 22ull /* SS */ |
| |
| #define | OpDS 23ull /* DS */ |
| |
| #define | OpFS 24ull /* FS */ |
| |
| #define | OpGS 25ull /* GS */ |
| |
| #define | OpMem8 26ull /* 8-bit zero extended memory operand */ |
| |
| #define | OpBits 5 /* Width of operand field */ |
| |
| #define | OpMask ((1ull << OpBits) - 1) |
| |
| #define | ByteOp (1<<0) /* 8-bit operands. */ |
| |
| #define | DstShift 1 |
| |
| #define | ImplicitOps (OpImplicit << DstShift) |
| |
| #define | DstReg (OpReg << DstShift) |
| |
| #define | DstMem (OpMem << DstShift) |
| |
| #define | DstAcc (OpAcc << DstShift) |
| |
| #define | DstDI (OpDI << DstShift) |
| |
| #define | DstMem64 (OpMem64 << DstShift) |
| |
| #define | DstImmUByte (OpImmUByte << DstShift) |
| |
| #define | DstDX (OpDX << DstShift) |
| |
| #define | DstMask (OpMask << DstShift) |
| |
| #define | SrcShift 6 |
| |
| #define | SrcNone (OpNone << SrcShift) |
| |
| #define | SrcReg (OpReg << SrcShift) |
| |
| #define | SrcMem (OpMem << SrcShift) |
| |
| #define | SrcMem16 (OpMem16 << SrcShift) |
| |
| #define | SrcMem32 (OpMem32 << SrcShift) |
| |
| #define | SrcImm (OpImm << SrcShift) |
| |
| #define | SrcImmByte (OpImmByte << SrcShift) |
| |
| #define | SrcOne (OpOne << SrcShift) |
| |
| #define | SrcImmUByte (OpImmUByte << SrcShift) |
| |
| #define | SrcImmU (OpImmU << SrcShift) |
| |
| #define | SrcSI (OpSI << SrcShift) |
| |
| #define | SrcImmFAddr (OpImmFAddr << SrcShift) |
| |
| #define | SrcMemFAddr (OpMemFAddr << SrcShift) |
| |
| #define | SrcAcc (OpAcc << SrcShift) |
| |
| #define | SrcImmU16 (OpImmU16 << SrcShift) |
| |
| #define | SrcDX (OpDX << SrcShift) |
| |
| #define | SrcMem8 (OpMem8 << SrcShift) |
| |
| #define | SrcMask (OpMask << SrcShift) |
| |
| #define | BitOp (1<<11) |
| |
| #define | MemAbs (1<<12) /* Memory operand is absolute displacement */ |
| |
| #define | String (1<<13) /* String instruction (rep capable) */ |
| |
| #define | Stack (1<<14) /* Stack instruction (push/pop) */ |
| |
| #define | GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ |
| |
| #define | Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ |
| |
| #define | GroupDual (2<<15) /* Alternate decoding of mod == 3 */ |
| |
| #define | Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ |
| |
| #define | RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ |
| |
| #define | Sse (1<<18) /* SSE Vector instruction */ |
| |
| #define | ModRM (1<<19) |
| |
| #define | Mov (1<<20) |
| |
| #define | Prot (1<<21) /* instruction generates #UD if not in prot-mode */ |
| |
| #define | VendorSpecific (1<<22) /* Vendor specific instruction */ |
| |
| #define | NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
| |
| #define | Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
| |
| #define | Undefined (1<<25) /* No Such Instruction */ |
| |
| #define | Lock (1<<26) /* lock prefix is allowed for the instruction */ |
| |
| #define | Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
| |
| #define | No64 (1<<28) |
| |
| #define | PageTable (1 << 29) /* instruction used to write page table */ |
| |
| #define | Src2Shift (30) |
| |
| #define | Src2None (OpNone << Src2Shift) |
| |
| #define | Src2CL (OpCL << Src2Shift) |
| |
| #define | Src2ImmByte (OpImmByte << Src2Shift) |
| |
| #define | Src2One (OpOne << Src2Shift) |
| |
| #define | Src2Imm (OpImm << Src2Shift) |
| |
| #define | Src2ES (OpES << Src2Shift) |
| |
| #define | Src2CS (OpCS << Src2Shift) |
| |
| #define | Src2SS (OpSS << Src2Shift) |
| |
| #define | Src2DS (OpDS << Src2Shift) |
| |
| #define | Src2FS (OpFS << Src2Shift) |
| |
| #define | Src2GS (OpGS << Src2Shift) |
| |
| #define | Src2Mask (OpMask << Src2Shift) |
| |
| #define | Mmx ((u64)1 << 40) /* MMX Vector instruction */ |
| |
| #define | Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ |
| |
| #define | Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */ |
| |
| #define | Avx ((u64)1 << 43) /* Advanced Vector Extensions */ |
| |
| #define | X2(x...) x, x |
| |
| #define | X3(x...) X2(x), x |
| |
| #define | X4(x...) X2(x), X2(x) |
| |
| #define | X5(x...) X4(x), x |
| |
| #define | X6(x...) X4(x), X2(x) |
| |
| #define | X7(x...) X4(x), X3(x) |
| |
| #define | X8(x...) X4(x), X4(x) |
| |
| #define | X16(x...) X8(x), X8(x) |
| |
| #define | EFLG_ID (1<<21) |
| |
| #define | EFLG_VIP (1<<20) |
| |
| #define | EFLG_VIF (1<<19) |
| |
| #define | EFLG_AC (1<<18) |
| |
| #define | EFLG_VM (1<<17) |
| |
| #define | EFLG_RF (1<<16) |
| |
| #define | EFLG_IOPL (3<<12) |
| |
| #define | EFLG_NT (1<<14) |
| |
| #define | EFLG_OF (1<<11) |
| |
| #define | EFLG_DF (1<<10) |
| |
| #define | EFLG_IF (1<<9) |
| |
| #define | EFLG_TF (1<<8) |
| |
| #define | EFLG_SF (1<<7) |
| |
| #define | EFLG_ZF (1<<6) |
| |
| #define | EFLG_AF (1<<4) |
| |
| #define | EFLG_PF (1<<2) |
| |
| #define | EFLG_CF (1<<0) |
| |
| #define | EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
| |
| #define | EFLG_RESERVED_ONE_MASK 2 |
| |
| #define | EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) |
| |
| #define | _PRE_EFLAGS(_sav, _msk, _tmp) |
| |
| #define | _POST_EFLAGS(_sav, _msk, _tmp) |
| |
| #define | ON64(x) |
| |
| #define | ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) |
| |
| #define | __emulate_2op_nobyte(ctxt, _op, _wx, _wy, _lx, _ly, _qx, _qy) |
| |
| #define | __emulate_2op(ctxt, _op, _bx, _by, _wx, _wy, _lx, _ly, _qx, _qy) |
| |
| #define | emulate_2op_SrcB(ctxt, _op) __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c") |
| |
| #define | emulate_2op_SrcV(ctxt, _op) __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r") |
| |
| #define | emulate_2op_SrcV_nobyte(ctxt, _op) __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r") |
| |
| #define | __emulate_2op_cl(ctxt, _op, _suffix, _type) |
| |
| #define | emulate_2op_cl(ctxt, _op) |
| |
| #define | __emulate_1op(ctxt, _op, _suffix) |
| |
| #define | emulate_1op(ctxt, _op) |
| |
| #define | __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) |
| |
| #define | emulate_1op_rax_rdx(ctxt, _op, _ex) |
| |
| #define | insn_fetch(_type, _ctxt) |
| |
| #define | insn_fetch_arr(_arr, _size, _ctxt) |
| |
| #define | D(_y) { .flags = (_y) } |
| |
| #define | DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i } |
| |
| #define | DIP(_y, _i, _p) |
| |
| #define | N D(0) |
| |
| #define | EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } |
| |
| #define | G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } |
| |
| #define | GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } |
| |
| #define | I(_f, _e) { .flags = (_f), .u.execute = (_e) } |
| |
| #define | II(_f, _e, _i) { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i } |
| |
| #define | IIP(_f, _e, _i, _p) |
| |
| #define | GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } |
| |
| #define | D2bv(_f) D((_f) | ByteOp), D(_f) |
| |
| #define | D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) |
| |
| #define | I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) |
| |
| #define | I2bvIP(_f, _e, _i, _p) IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) |
| |
| #define | I6ALU(_f, _e) |
| |
1.8.2