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Macros
def_LPBlackfin.h File Reference
#include <mach/anomaly.h>
#include <linux/types.h>

Go to the source code of this file.

Macros

#define MK_BMSK_(x)   (1<<x)
 
#define BFIN_DEPOSIT(mask, x)   (((x) << __ffs(mask)) & (mask))
 
#define BFIN_EXTRACT(mask, x)   (((x) & (mask)) >> __ffs(mask))
 
#define NOP_PAD_ANOMALY_05000198
 
#define _bfin_readX(addr, size, asm_size, asm_ext)
 
#define _bfin_writeX(addr, val, size, asm_size)
 
#define bfin_read8(addr)   _bfin_readX(addr, 8, b, (z))
 
#define bfin_read16(addr)   _bfin_readX(addr, 16, w, (z))
 
#define bfin_read32(addr)   _bfin_readX(addr, 32, , )
 
#define bfin_write8(addr, val)   _bfin_writeX(addr, val, 8, b)
 
#define bfin_write16(addr, val)   _bfin_writeX(addr, val, 16, w)
 
#define bfin_write32(addr, val)   _bfin_writeX(addr, val, 32, )
 
#define bfin_read(addr)
 
#define bfin_write(addr, val)
 
#define bfin_write_or(addr, bits)
 
#define bfin_write_and(addr, bits)
 
#define ASTAT_AZ_P   0x00000000
 
#define ASTAT_AN_P   0x00000001
 
#define ASTAT_CC_P   0x00000005
 
#define ASTAT_AQ_P   0x00000006
 
#define ASTAT_RND_MOD_P   0x00000008
 
#define ASTAT_AC0_P   0x0000000C
 
#define ASTAT_AC0_COPY_P   0x00000002
 
#define ASTAT_AC1_P   0x0000000D
 
#define ASTAT_AV0_P   0x00000010
 
#define ASTAT_AV0S_P   0x00000011
 
#define ASTAT_AV1_P   0x00000012
 
#define ASTAT_AV1S_P   0x00000013
 
#define ASTAT_V_P   0x00000018
 
#define ASTAT_V_COPY_P   0x00000003
 
#define ASTAT_VS_P   0x00000019
 
#define ASTAT_AZ   MK_BMSK_(ASTAT_AZ_P)
 
#define ASTAT_AN   MK_BMSK_(ASTAT_AN_P)
 
#define ASTAT_AC0   MK_BMSK_(ASTAT_AC0_P)
 
#define ASTAT_AC0_COPY   MK_BMSK_(ASTAT_AC0_COPY_P)
 
#define ASTAT_AC1   MK_BMSK_(ASTAT_AC1_P)
 
#define ASTAT_AV0   MK_BMSK_(ASTAT_AV0_P)
 
#define ASTAT_AV1   MK_BMSK_(ASTAT_AV1_P)
 
#define ASTAT_CC   MK_BMSK_(ASTAT_CC_P)
 
#define ASTAT_AQ   MK_BMSK_(ASTAT_AQ_P)
 
#define ASTAT_RND_MOD   MK_BMSK_(ASTAT_RND_MOD_P)
 
#define ASTAT_V   MK_BMSK_(ASTAT_V_P)
 
#define ASTAT_V_COPY   MK_BMSK_(ASTAT_V_COPY_P)
 
#define SEQSTAT_EXCAUSE0_P   0x00000000 /* Last exception cause bit 0 */
 
#define SEQSTAT_EXCAUSE1_P   0x00000001 /* Last exception cause bit 1 */
 
#define SEQSTAT_EXCAUSE2_P   0x00000002 /* Last exception cause bit 2 */
 
#define SEQSTAT_EXCAUSE3_P   0x00000003 /* Last exception cause bit 3 */
 
#define SEQSTAT_EXCAUSE4_P   0x00000004 /* Last exception cause bit 4 */
 
#define SEQSTAT_EXCAUSE5_P   0x00000005 /* Last exception cause bit 5 */
 
#define SEQSTAT_IDLE_REQ_P
 
#define SEQSTAT_SFTRESET_P
 
#define SEQSTAT_HWERRCAUSE0_P   0x0000000E /* Last hw error cause bit 0 */
 
#define SEQSTAT_HWERRCAUSE1_P   0x0000000F /* Last hw error cause bit 1 */
 
#define SEQSTAT_HWERRCAUSE2_P   0x00000010 /* Last hw error cause bit 2 */
 
#define SEQSTAT_HWERRCAUSE3_P   0x00000011 /* Last hw error cause bit 3 */
 
#define SEQSTAT_HWERRCAUSE4_P   0x00000012 /* Last hw error cause bit 4 */
 
#define SEQSTAT_EXCAUSE
 
#define SEQSTAT_SFTRESET   (MK_BMSK_(SEQSTAT_SFTRESET_P))
 
#define SEQSTAT_HWERRCAUSE
 
#define SEQSTAT_HWERRCAUSE_SHIFT   (14)
 
#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR   (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
 
#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR   (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
 
#define SEQSTAT_HWERRCAUSE_PERF_FLOW   (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
 
#define SEQSTAT_HWERRCAUSE_RAISE_5   (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
 
#define SYSCFG_SSSTEP_P
 
#define SYSCFG_CCEN_P   0x00000001 /* Enable cycle counter (=1) */
 
#define SYSCFG_SNEN_P   0x00000002 /* Self nesting Interrupt Enable */
 
#define SYSCFG_SSSTEP   MK_BMSK_(SYSCFG_SSSTEP_P )
 
#define SYSCFG_CCEN   MK_BMSK_(SYSCFG_CCEN_P )
 
#define SYSCFG_SNEN   MK_BMSK_(SYSCFG_SNEN_P)
 
#define SYSCFG_SSSSTEP   SYSCFG_SSSTEP
 
#define SYSCFG_CCCEN   SYSCFG_CCEN
 
#define SRAM_BASE_ADDRESS   0xFFE00000 /* SRAM Base Address Register */
 
#define DMEM_CONTROL   0xFFE00004 /* Data memory control */
 
#define DCPLB_STATUS
 
#define DCPLB_FAULT_STATUS   0xFFE00008 /* "" (older define) */
 
#define DCPLB_FAULT_ADDR
 
#define DCPLB_ADDR0
 
#define DCPLB_ADDR1
 
#define DCPLB_ADDR2
 
#define DCPLB_ADDR3
 
#define DCPLB_ADDR4
 
#define DCPLB_ADDR5
 
#define DCPLB_ADDR6
 
#define DCPLB_ADDR7
 
#define DCPLB_ADDR8
 
#define DCPLB_ADDR9
 
#define DCPLB_ADDR10
 
#define DCPLB_ADDR11
 
#define DCPLB_ADDR12
 
#define DCPLB_ADDR13
 
#define DCPLB_ADDR14
 
#define DCPLB_ADDR15
 
#define DCPLB_DATA0   0xFFE00200 /* Data Cache 0 Status */
 
#define DCPLB_DATA1   0xFFE00204 /* Data Cache 1 Status */
 
#define DCPLB_DATA2   0xFFE00208 /* Data Cache 2 Status */
 
#define DCPLB_DATA3   0xFFE0020C /* Data Cache 3 Status */
 
#define DCPLB_DATA4   0xFFE00210 /* Data Cache 4 Status */
 
#define DCPLB_DATA5   0xFFE00214 /* Data Cache 5 Status */
 
#define DCPLB_DATA6   0xFFE00218 /* Data Cache 6 Status */
 
#define DCPLB_DATA7   0xFFE0021C /* Data Cache 7 Status */
 
#define DCPLB_DATA8   0xFFE00220 /* Data Cache 8 Status */
 
#define DCPLB_DATA9   0xFFE00224 /* Data Cache 9 Status */
 
#define DCPLB_DATA10   0xFFE00228 /* Data Cache 10 Status */
 
#define DCPLB_DATA11   0xFFE0022C /* Data Cache 11 Status */
 
#define DCPLB_DATA12   0xFFE00230 /* Data Cache 12 Status */
 
#define DCPLB_DATA13   0xFFE00234 /* Data Cache 13 Status */
 
#define DCPLB_DATA14   0xFFE00238 /* Data Cache 14 Status */
 
#define DCPLB_DATA15   0xFFE0023C /* Data Cache 15 Status */
 
#define DCPLB_DATA16   0xFFE00240 /* Extra Dummy entry */
 
#define DTEST_COMMAND   0xFFE00300 /* Data Test Command Register */
 
#define DTEST_DATA0   0xFFE00400 /* Data Test Data Register */
 
#define DTEST_DATA1   0xFFE00404 /* Data Test Data Register */
 
#define IMEM_CONTROL   0xFFE01004 /* Instruction Memory Control */
 
#define ICPLB_STATUS   0xFFE01008 /* Instruction Cache miss status */
 
#define CODE_FAULT_STATUS   0xFFE01008 /* "" (older define) */
 
#define ICPLB_FAULT_ADDR   0xFFE0100C /* Instruction Cache miss address */
 
#define CODE_FAULT_ADDR   0xFFE0100C /* "" (older define) */
 
#define ICPLB_ADDR0
 
#define ICPLB_ADDR1
 
#define ICPLB_ADDR2
 
#define ICPLB_ADDR3
 
#define ICPLB_ADDR4
 
#define ICPLB_ADDR5
 
#define ICPLB_ADDR6
 
#define ICPLB_ADDR7
 
#define ICPLB_ADDR8
 
#define ICPLB_ADDR9
 
#define ICPLB_ADDR10
 
#define ICPLB_ADDR11
 
#define ICPLB_ADDR12
 
#define ICPLB_ADDR13
 
#define ICPLB_ADDR14
 
#define ICPLB_ADDR15
 
#define ICPLB_DATA0   0xFFE01200 /* Instruction Cache 0 Status */
 
#define ICPLB_DATA1   0xFFE01204 /* Instruction Cache 1 Status */
 
#define ICPLB_DATA2   0xFFE01208 /* Instruction Cache 2 Status */
 
#define ICPLB_DATA3   0xFFE0120C /* Instruction Cache 3 Status */
 
#define ICPLB_DATA4   0xFFE01210 /* Instruction Cache 4 Status */
 
#define ICPLB_DATA5   0xFFE01214 /* Instruction Cache 5 Status */
 
#define ICPLB_DATA6   0xFFE01218 /* Instruction Cache 6 Status */
 
#define ICPLB_DATA7   0xFFE0121C /* Instruction Cache 7 Status */
 
#define ICPLB_DATA8   0xFFE01220 /* Instruction Cache 8 Status */
 
#define ICPLB_DATA9   0xFFE01224 /* Instruction Cache 9 Status */
 
#define ICPLB_DATA10   0xFFE01228 /* Instruction Cache 10 Status */
 
#define ICPLB_DATA11   0xFFE0122C /* Instruction Cache 11 Status */
 
#define ICPLB_DATA12   0xFFE01230 /* Instruction Cache 12 Status */
 
#define ICPLB_DATA13   0xFFE01234 /* Instruction Cache 13 Status */
 
#define ICPLB_DATA14   0xFFE01238 /* Instruction Cache 14 Status */
 
#define ICPLB_DATA15   0xFFE0123C /* Instruction Cache 15 Status */
 
#define ITEST_COMMAND   0xFFE01300 /* Instruction Test Command Register */
 
#define ITEST_DATA0   0xFFE01400 /* Instruction Test Data Register */
 
#define ITEST_DATA1   0xFFE01404 /* Instruction Test Data Register */
 
#define EVT0   0xFFE02000 /* Event Vector 0 ESR Address */
 
#define EVT1   0xFFE02004 /* Event Vector 1 ESR Address */
 
#define EVT2   0xFFE02008 /* Event Vector 2 ESR Address */
 
#define EVT3   0xFFE0200C /* Event Vector 3 ESR Address */
 
#define EVT4   0xFFE02010 /* Event Vector 4 ESR Address */
 
#define EVT5   0xFFE02014 /* Event Vector 5 ESR Address */
 
#define EVT6   0xFFE02018 /* Event Vector 6 ESR Address */
 
#define EVT7   0xFFE0201C /* Event Vector 7 ESR Address */
 
#define EVT8   0xFFE02020 /* Event Vector 8 ESR Address */
 
#define EVT9   0xFFE02024 /* Event Vector 9 ESR Address */
 
#define EVT10   0xFFE02028 /* Event Vector 10 ESR Address */
 
#define EVT11   0xFFE0202C /* Event Vector 11 ESR Address */
 
#define EVT12   0xFFE02030 /* Event Vector 12 ESR Address */
 
#define EVT13   0xFFE02034 /* Event Vector 13 ESR Address */
 
#define EVT14   0xFFE02038 /* Event Vector 14 ESR Address */
 
#define EVT15   0xFFE0203C /* Event Vector 15 ESR Address */
 
#define EVT_OVERRIDE   0xFFE02100 /* Event Vector Override Register */
 
#define IMASK   0xFFE02104 /* Interrupt Mask Register */
 
#define IPEND   0xFFE02108 /* Interrupt Pending Register */
 
#define ILAT   0xFFE0210C /* Interrupt Latch Register */
 
#define IPRIO   0xFFE02110 /* Core Interrupt Priority Register */
 
#define TCNTL   0xFFE03000 /* Core Timer Control Register */
 
#define TPERIOD   0xFFE03004 /* Core Timer Period Register */
 
#define TSCALE   0xFFE03008 /* Core Timer Scale Register */
 
#define TCOUNT   0xFFE0300C /* Core Timer Count Register */
 
#define DSPID
 
#define DBGSTAT   0xFFE05008 /* Debug Status Register */
 
#define TBUFCTL   0xFFE06000 /* Trace Buffer Control Register */
 
#define TBUFSTAT   0xFFE06004 /* Trace Buffer Status Register */
 
#define TBUF   0xFFE06100 /* Trace Buffer */
 
#define WPIACTL   0xFFE07000
 
#define WPIA0   0xFFE07040
 
#define WPIA1   0xFFE07044
 
#define WPIA2   0xFFE07048
 
#define WPIA3   0xFFE0704C
 
#define WPIA4   0xFFE07050
 
#define WPIA5   0xFFE07054
 
#define WPIACNT0   0xFFE07080
 
#define WPIACNT1   0xFFE07084
 
#define WPIACNT2   0xFFE07088
 
#define WPIACNT3   0xFFE0708C
 
#define WPIACNT4   0xFFE07090
 
#define WPIACNT5   0xFFE07094
 
#define WPDACTL   0xFFE07100
 
#define WPDA0   0xFFE07140
 
#define WPDA1   0xFFE07144
 
#define WPDACNT0   0xFFE07180
 
#define WPDACNT1   0xFFE07184
 
#define WPSTAT   0xFFE07200
 
#define PFCTL   0xFFE08000
 
#define PFCNTR0   0xFFE08100
 
#define PFCNTR1   0xFFE08104
 
#define EVT_EMU_P   0x00000000 /* Emulator interrupt bit position */
 
#define EVT_RST_P   0x00000001 /* Reset interrupt bit position */
 
#define EVT_NMI_P   0x00000002 /* Non Maskable interrupt bit position */
 
#define EVT_EVX_P   0x00000003 /* Exception bit position */
 
#define EVT_IRPTEN_P   0x00000004 /* Global interrupt enable bit position */
 
#define EVT_IVHW_P   0x00000005 /* Hardware Error interrupt bit position */
 
#define EVT_IVTMR_P   0x00000006 /* Timer interrupt bit position */
 
#define EVT_IVG7_P   0x00000007 /* IVG7 interrupt bit position */
 
#define EVT_IVG8_P   0x00000008 /* IVG8 interrupt bit position */
 
#define EVT_IVG9_P   0x00000009 /* IVG9 interrupt bit position */
 
#define EVT_IVG10_P   0x0000000a /* IVG10 interrupt bit position */
 
#define EVT_IVG11_P   0x0000000b /* IVG11 interrupt bit position */
 
#define EVT_IVG12_P   0x0000000c /* IVG12 interrupt bit position */
 
#define EVT_IVG13_P   0x0000000d /* IVG13 interrupt bit position */
 
#define EVT_IVG14_P   0x0000000e /* IVG14 interrupt bit position */
 
#define EVT_IVG15_P   0x0000000f /* IVG15 interrupt bit position */
 
#define EVT_EMU   MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
 
#define EVT_RST   MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
 
#define EVT_NMI   MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
 
#define EVT_EVX   MK_BMSK_(EVT_EVX_P ) /* Exception mask */
 
#define EVT_IRPTEN   MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
 
#define EVT_IVHW   MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
 
#define EVT_IVTMR   MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
 
#define EVT_IVG7   MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
 
#define EVT_IVG8   MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
 
#define EVT_IVG9   MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
 
#define EVT_IVG10   MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
 
#define EVT_IVG11   MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
 
#define EVT_IVG12   MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
 
#define EVT_IVG13   MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
 
#define EVT_IVG14   MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
 
#define EVT_IVG15   MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
 
#define ENDM_P
 
#define DMCTL_ENDM_P   ENDM_P /* "" (older define) */
 
#define ENDCPLB_P   0x01 /* Enable DCPLBS */
 
#define DMCTL_ENDCPLB_P   ENDCPLB_P /* "" (older define) */
 
#define DMC0_P   0x02 /* L1 Data Memory Configure bit 0 */
 
#define DMCTL_DMC0_P   DMC0_P /* "" (older define) */
 
#define DMC1_P   0x03 /* L1 Data Memory Configure bit 1 */
 
#define DMCTL_DMC1_P   DMC1_P /* "" (older define) */
 
#define DCBS_P   0x04 /* L1 Data Cache Bank Select */
 
#define PORT_PREF0_P   0x12 /* DAG0 Port Preference */
 
#define PORT_PREF1_P   0x13 /* DAG1 Port Preference */
 
#define ENDM
 
#define ENDCPLB   0x00000002 /* Enable DCPLB */
 
#define ASRAM_BSRAM   0x00000000
 
#define ACACHE_BSRAM   0x00000008
 
#define ACACHE_BCACHE   0x0000000C
 
#define DCBS   0x00000010 /* L1 Data Cache Bank Select */
 
#define PORT_PREF0   0x00001000 /* DAG0 Port Preference */
 
#define PORT_PREF1   0x00002000 /* DAG1 Port Preference */
 
#define ENIM_P   0x00 /* Enable L1 Code Memory */
 
#define IMCTL_ENIM_P   0x00 /* "" (older define) */
 
#define ENICPLB_P   0x01 /* Enable ICPLB */
 
#define IMCTL_ENICPLB_P   0x01 /* "" (older define) */
 
#define IMC_P   0x02 /* Enable */
 
#define IMCTL_IMC_P
 
#define ILOC0_P   0x03 /* Lock Way 0 */
 
#define ILOC1_P   0x04 /* Lock Way 1 */
 
#define ILOC2_P   0x05 /* Lock Way 2 */
 
#define ILOC3_P   0x06 /* Lock Way 3 */
 
#define LRUPRIORST_P
 
#define ENIM   0x00000001 /* Enable L1 Code Memory */
 
#define ENICPLB   0x00000002 /* Enable ICPLB */
 
#define IMC
 
#define ILOC0   0x00000008 /* Lock Way 0 */
 
#define ILOC1   0x00000010 /* Lock Way 1 */
 
#define ILOC2   0x00000020 /* Lock Way 2 */
 
#define ILOC3   0x00000040 /* Lock Way 3 */
 
#define LRUPRIORST
 
#define TMPWR
 
#define TMREN   0x00000002 /* Timer enable, 0=disable, 1=enable */
 
#define TAUTORLD   0x00000004 /* Timer auto reload */
 
#define TINT
 
#define CPLB_VALID_P   0x00000000 /* 0=invalid entry, 1=valid entry */
 
#define CPLB_LOCK_P
 
#define CPLB_USER_RD_P
 
#define CPLB_VALID   0x00000001 /* 0=invalid entry, 1=valid entry */
 
#define CPLB_LOCK
 
#define CPLB_USER_RD
 
#define PAGE_SIZE_1KB   0x00000000 /* 1 KB page size */
 
#define PAGE_SIZE_4KB   0x00010000 /* 4 KB page size */
 
#define PAGE_SIZE_1MB   0x00020000 /* 1 MB page size */
 
#define PAGE_SIZE_4MB   0x00030000 /* 4 MB page size */
 
#define PAGE_SIZE_16KB   0x00040000 /* 16 KB page size */
 
#define PAGE_SIZE_64KB   0x00050000 /* 64 KB page size */
 
#define PAGE_SIZE_16MB   0x00060000 /* 16 MB page size */
 
#define PAGE_SIZE_64MB   0x00070000 /* 64 MB page size */
 
#define CPLB_L1SRAM
 
#define CPLB_PORTPRIO
 
#define CPLB_L1_CHBL
 
#define CPLB_LRUPRIO
 
#define CPLB_USER_WR
 
#define CPLB_SUPV_WR
 
#define CPLB_DIRTY   0x00000080 /* 1=dirty, 0=clean */
 
#define CPLB_L1_AOW
 
#define CPLB_WT   0x00004000 /* 0=write-back, 1=write-through */
 
#define CPLB_ALL_ACCESS   CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
 
#define TBUFPWR   0x0001
 
#define TBUFEN   0x0002
 
#define TBUFOVF   0x0004
 
#define TBUFCMPLP_SINGLE   0x0008
 
#define TBUFCMPLP_DOUBLE   0x0010
 
#define TBUFCMPLP   (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
 
#define TBUFCNT   0x001F
 
#define TEST_READ   0x00000000 /* Read Access */
 
#define TEST_WRITE   0x00000002 /* Write Access */
 
#define TEST_TAG   0x00000000 /* Access TAG */
 
#define TEST_DATA   0x00000004 /* Access DATA */
 
#define TEST_DW0   0x00000000 /* Select Double Word 0 */
 
#define TEST_DW1   0x00000008 /* Select Double Word 1 */
 
#define TEST_DW2   0x00000010 /* Select Double Word 2 */
 
#define TEST_DW3   0x00000018 /* Select Double Word 3 */
 
#define TEST_MB0   0x00000000 /* Select Mini-Bank 0 */
 
#define TEST_MB1   0x00010000 /* Select Mini-Bank 1 */
 
#define TEST_MB2   0x00020000 /* Select Mini-Bank 2 */
 
#define TEST_MB3   0x00030000 /* Select Mini-Bank 3 */
 
#define TEST_SET(x)   ((x << 5) & 0x03E0) /* Set Index 0->31 */
 
#define TEST_WAY0   0x00000000 /* Access Way0 */
 
#define TEST_WAY1   0x04000000 /* Access Way1 */
 
#define TEST_WAY2   0x08000000 /* Access Way2 */
 
#define TEST_WAY3   0x0C000000 /* Access Way3 */
 
#define TEST_BNKSELA   0x00000000 /* Access SuperBank A */
 
#define TEST_BNKSELB   0x00800000 /* Access SuperBank B */
 

Macro Definition Documentation

#define _bfin_readX (   addr,
  size,
  asm_size,
  asm_ext 
)
Value:
({ \
u32 __v; \
__asm__ __volatile__( \
NOP_PAD_ANOMALY_05000198 \
"%0 = " #asm_size "[%1]" #asm_ext ";" \
: "=d" (__v) \
: "a" (addr) \
); \
__v; })

Definition at line 28 of file def_LPBlackfin.h.

#define _bfin_writeX (   addr,
  val,
  size,
  asm_size 
)
Value:
__asm__ __volatile__( \
NOP_PAD_ANOMALY_05000198 \
#asm_size "[%0] = %1;" \
: \
: "a" (addr), "d" ((u##size)(val)) \
: "memory" \
)

Definition at line 37 of file def_LPBlackfin.h.

#define ACACHE_BCACHE   0x0000000C

Definition at line 473 of file def_LPBlackfin.h.

#define ACACHE_BSRAM   0x00000008

Definition at line 472 of file def_LPBlackfin.h.

#define ASRAM_BSRAM   0x00000000

Definition at line 471 of file def_LPBlackfin.h.

#define ASTAT_AC0   MK_BMSK_(ASTAT_AC0_P)

Definition at line 132 of file def_LPBlackfin.h.

#define ASTAT_AC0_COPY   MK_BMSK_(ASTAT_AC0_COPY_P)

Definition at line 134 of file def_LPBlackfin.h.

#define ASTAT_AC0_COPY_P   0x00000002

Definition at line 107 of file def_LPBlackfin.h.

#define ASTAT_AC0_P   0x0000000C

Definition at line 105 of file def_LPBlackfin.h.

#define ASTAT_AC1   MK_BMSK_(ASTAT_AC1_P)

Definition at line 136 of file def_LPBlackfin.h.

#define ASTAT_AC1_P   0x0000000D

Definition at line 109 of file def_LPBlackfin.h.

#define ASTAT_AN   MK_BMSK_(ASTAT_AN_P)

Definition at line 130 of file def_LPBlackfin.h.

#define ASTAT_AN_P   0x00000001

Definition at line 97 of file def_LPBlackfin.h.

#define ASTAT_AQ   MK_BMSK_(ASTAT_AQ_P)

Definition at line 144 of file def_LPBlackfin.h.

#define ASTAT_AQ_P   0x00000006

Definition at line 101 of file def_LPBlackfin.h.

#define ASTAT_AV0   MK_BMSK_(ASTAT_AV0_P)

Definition at line 138 of file def_LPBlackfin.h.

#define ASTAT_AV0_P   0x00000010

Definition at line 111 of file def_LPBlackfin.h.

#define ASTAT_AV0S_P   0x00000011

Definition at line 113 of file def_LPBlackfin.h.

#define ASTAT_AV1   MK_BMSK_(ASTAT_AV1_P)

Definition at line 140 of file def_LPBlackfin.h.

#define ASTAT_AV1_P   0x00000012

Definition at line 115 of file def_LPBlackfin.h.

#define ASTAT_AV1S_P   0x00000013

Definition at line 117 of file def_LPBlackfin.h.

#define ASTAT_AZ   MK_BMSK_(ASTAT_AZ_P)

Definition at line 128 of file def_LPBlackfin.h.

#define ASTAT_AZ_P   0x00000000

Definition at line 95 of file def_LPBlackfin.h.

#define ASTAT_CC   MK_BMSK_(ASTAT_CC_P)

Definition at line 142 of file def_LPBlackfin.h.

#define ASTAT_CC_P   0x00000005

Definition at line 99 of file def_LPBlackfin.h.

#define ASTAT_RND_MOD   MK_BMSK_(ASTAT_RND_MOD_P)

Definition at line 146 of file def_LPBlackfin.h.

#define ASTAT_RND_MOD_P   0x00000008

Definition at line 103 of file def_LPBlackfin.h.

#define ASTAT_V   MK_BMSK_(ASTAT_V_P)

Definition at line 148 of file def_LPBlackfin.h.

#define ASTAT_V_COPY   MK_BMSK_(ASTAT_V_COPY_P)

Definition at line 150 of file def_LPBlackfin.h.

#define ASTAT_V_COPY_P   0x00000003

Definition at line 121 of file def_LPBlackfin.h.

#define ASTAT_V_P   0x00000018

Definition at line 119 of file def_LPBlackfin.h.

#define ASTAT_VS_P   0x00000019

Definition at line 123 of file def_LPBlackfin.h.

#define BFIN_DEPOSIT (   mask,
  x 
)    (((x) << __ffs(mask)) & (mask))

Definition at line 15 of file def_LPBlackfin.h.

#define BFIN_EXTRACT (   mask,
  x 
)    (((x) & (mask)) >> __ffs(mask))

Definition at line 16 of file def_LPBlackfin.h.

#define bfin_read (   addr)
Value:
({ \
sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
({ BUG(); 0; }); \
})

Definition at line 53 of file def_LPBlackfin.h.

#define bfin_read16 (   addr)    _bfin_readX(addr, 16, w, (z))

Definition at line 47 of file def_LPBlackfin.h.

#define bfin_read32 (   addr)    _bfin_readX(addr, 32, , )

Definition at line 48 of file def_LPBlackfin.h.

#define bfin_read8 (   addr)    _bfin_readX(addr, 8, b, (z))

Definition at line 46 of file def_LPBlackfin.h.

#define bfin_write (   addr,
  val 
)
Value:
do { \
switch (sizeof(*(addr))) { \
case 1: bfin_write8(addr, val); break; \
case 2: bfin_write16(addr, val); break; \
case 4: bfin_write32(addr, val); break; \
default: BUG(); \
} \
} while (0)

Definition at line 60 of file def_LPBlackfin.h.

#define bfin_write16 (   addr,
  val 
)    _bfin_writeX(addr, val, 16, w)

Definition at line 50 of file def_LPBlackfin.h.

#define bfin_write32 (   addr,
  val 
)    _bfin_writeX(addr, val, 32, )

Definition at line 51 of file def_LPBlackfin.h.

#define bfin_write8 (   addr,
  val 
)    _bfin_writeX(addr, val, 8, b)

Definition at line 49 of file def_LPBlackfin.h.

#define bfin_write_and (   addr,
  bits 
)
Value:
do { \
typeof(addr) __addr = (addr); \
bfin_write(__addr, bfin_read(__addr) & (bits)); \
} while (0)

Definition at line 76 of file def_LPBlackfin.h.

#define bfin_write_or (   addr,
  bits 
)
Value:
do { \
typeof(addr) __addr = (addr); \
bfin_write(__addr, bfin_read(__addr) | (bits)); \
} while (0)

Definition at line 70 of file def_LPBlackfin.h.

#define CODE_FAULT_ADDR   0xFFE0100C /* "" (older define) */

Definition at line 278 of file def_LPBlackfin.h.

#define CODE_FAULT_STATUS   0xFFE01008 /* "" (older define) */

Definition at line 276 of file def_LPBlackfin.h.

#define CPLB_ALL_ACCESS   CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR

Definition at line 537 of file def_LPBlackfin.h.

#define CPLB_DIRTY   0x00000080 /* 1=dirty, 0=clean */

Definition at line 533 of file def_LPBlackfin.h.

#define CPLB_L1_AOW
Value:
0x00008000 /* 0=do not allocate cache lines on
* write-through writes,
* 1= allocate cache lines on
* write-through writes.
*/

Definition at line 534 of file def_LPBlackfin.h.

#define CPLB_L1_CHBL
Value:
0x00001000 /* 0=non-cacheable in L1, 1=cacheable
* in L1
*/

Definition at line 527 of file def_LPBlackfin.h.

#define CPLB_L1SRAM
Value:
0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
* mapped to L1
*/

Definition at line 525 of file def_LPBlackfin.h.

#define CPLB_LOCK
Value:
0x00000002 /* 0=entry may be replaced, 1=entry
* locked
*/

Definition at line 514 of file def_LPBlackfin.h.

#define CPLB_LOCK_P
Value:
0x00000001 /* 0=entry may be replaced, 1=entry
* locked
*/

Definition at line 510 of file def_LPBlackfin.h.

#define CPLB_LRUPRIO
Value:
0x00000100 /* 0=can be replaced by any line,
* 1=priority for non-replacement
*/

Definition at line 529 of file def_LPBlackfin.h.

#define CPLB_PORTPRIO
Value:
0x00000200 /* 0=low priority port, 1= high
* priority port
*/

Definition at line 526 of file def_LPBlackfin.h.

#define CPLB_SUPV_WR
Value:
0x00000010 /* 0=no write access, 0=write
* access allowed (supervisor mode)
*/

Definition at line 532 of file def_LPBlackfin.h.

#define CPLB_USER_RD
Value:
0x00000004 /* 0=no read access, 1=read access
* allowed (user mode)
*/

Definition at line 515 of file def_LPBlackfin.h.

#define CPLB_USER_RD_P
Value:
0x00000002 /* 0=no read access, 1=read access
* allowed (user mode)
*/

Definition at line 511 of file def_LPBlackfin.h.

#define CPLB_USER_WR
Value:
0x00000008 /* 0=no write access, 0=write
* access allowed (user mode)
*/

Definition at line 531 of file def_LPBlackfin.h.

#define CPLB_VALID   0x00000001 /* 0=invalid entry, 1=valid entry */

Definition at line 513 of file def_LPBlackfin.h.

#define CPLB_VALID_P   0x00000000 /* 0=invalid entry, 1=valid entry */

Definition at line 509 of file def_LPBlackfin.h.

#define CPLB_WT   0x00004000 /* 0=write-back, 1=write-through */

Definition at line 535 of file def_LPBlackfin.h.

#define DBGSTAT   0xFFE05008 /* Debug Status Register */

Definition at line 349 of file def_LPBlackfin.h.

#define DCBS   0x00000010 /* L1 Data Cache Bank Select */

Definition at line 474 of file def_LPBlackfin.h.

#define DCBS_P   0x04 /* L1 Data Cache Bank Select */

Definition at line 464 of file def_LPBlackfin.h.

#define DCPLB_ADDR0
Value:
0xFFE00100 /* Data Cache Protection Lookaside
* Buffer 0
*/

Definition at line 234 of file def_LPBlackfin.h.

#define DCPLB_ADDR1
Value:
0xFFE00104 /* Data Cache Protection Lookaside
* Buffer 1
*/

Definition at line 235 of file def_LPBlackfin.h.

#define DCPLB_ADDR10
Value:
0xFFE00128 /* Data Cacheability Protection
* Lookaside Buffer 10
*/

Definition at line 244 of file def_LPBlackfin.h.

#define DCPLB_ADDR11
Value:
0xFFE0012C /* Data Cacheability Protection
* Lookaside Buffer 11
*/

Definition at line 245 of file def_LPBlackfin.h.

#define DCPLB_ADDR12
Value:
0xFFE00130 /* Data Cacheability Protection
* Lookaside Buffer 12
*/

Definition at line 246 of file def_LPBlackfin.h.

#define DCPLB_ADDR13
Value:
0xFFE00134 /* Data Cacheability Protection
* Lookaside Buffer 13
*/

Definition at line 247 of file def_LPBlackfin.h.

#define DCPLB_ADDR14
Value:
0xFFE00138 /* Data Cacheability Protection
* Lookaside Buffer 14
*/

Definition at line 248 of file def_LPBlackfin.h.

#define DCPLB_ADDR15
Value:
0xFFE0013C /* Data Cacheability Protection
* Lookaside Buffer 15
*/

Definition at line 249 of file def_LPBlackfin.h.

#define DCPLB_ADDR2
Value:
0xFFE00108 /* Data Cache Protection Lookaside
* Buffer 2
*/

Definition at line 236 of file def_LPBlackfin.h.

#define DCPLB_ADDR3
Value:
0xFFE0010C /* Data Cacheability Protection
* Lookaside Buffer 3
*/

Definition at line 237 of file def_LPBlackfin.h.

#define DCPLB_ADDR4
Value:
0xFFE00110 /* Data Cacheability Protection
* Lookaside Buffer 4
*/

Definition at line 238 of file def_LPBlackfin.h.

#define DCPLB_ADDR5
Value:
0xFFE00114 /* Data Cacheability Protection
* Lookaside Buffer 5
*/

Definition at line 239 of file def_LPBlackfin.h.

#define DCPLB_ADDR6
Value:
0xFFE00118 /* Data Cacheability Protection
* Lookaside Buffer 6
*/

Definition at line 240 of file def_LPBlackfin.h.

#define DCPLB_ADDR7
Value:
0xFFE0011C /* Data Cacheability Protection
* Lookaside Buffer 7
*/

Definition at line 241 of file def_LPBlackfin.h.

#define DCPLB_ADDR8
Value:
0xFFE00120 /* Data Cacheability Protection
* Lookaside Buffer 8
*/

Definition at line 242 of file def_LPBlackfin.h.

#define DCPLB_ADDR9
Value:
0xFFE00124 /* Data Cacheability Protection
* Lookaside Buffer 9
*/

Definition at line 243 of file def_LPBlackfin.h.

#define DCPLB_DATA0   0xFFE00200 /* Data Cache 0 Status */

Definition at line 250 of file def_LPBlackfin.h.

#define DCPLB_DATA1   0xFFE00204 /* Data Cache 1 Status */

Definition at line 251 of file def_LPBlackfin.h.

#define DCPLB_DATA10   0xFFE00228 /* Data Cache 10 Status */

Definition at line 260 of file def_LPBlackfin.h.

#define DCPLB_DATA11   0xFFE0022C /* Data Cache 11 Status */

Definition at line 261 of file def_LPBlackfin.h.

#define DCPLB_DATA12   0xFFE00230 /* Data Cache 12 Status */

Definition at line 262 of file def_LPBlackfin.h.

#define DCPLB_DATA13   0xFFE00234 /* Data Cache 13 Status */

Definition at line 263 of file def_LPBlackfin.h.

#define DCPLB_DATA14   0xFFE00238 /* Data Cache 14 Status */

Definition at line 264 of file def_LPBlackfin.h.

#define DCPLB_DATA15   0xFFE0023C /* Data Cache 15 Status */

Definition at line 265 of file def_LPBlackfin.h.

#define DCPLB_DATA16   0xFFE00240 /* Extra Dummy entry */

Definition at line 266 of file def_LPBlackfin.h.

#define DCPLB_DATA2   0xFFE00208 /* Data Cache 2 Status */

Definition at line 252 of file def_LPBlackfin.h.

#define DCPLB_DATA3   0xFFE0020C /* Data Cache 3 Status */

Definition at line 253 of file def_LPBlackfin.h.

#define DCPLB_DATA4   0xFFE00210 /* Data Cache 4 Status */

Definition at line 254 of file def_LPBlackfin.h.

#define DCPLB_DATA5   0xFFE00214 /* Data Cache 5 Status */

Definition at line 255 of file def_LPBlackfin.h.

#define DCPLB_DATA6   0xFFE00218 /* Data Cache 6 Status */

Definition at line 256 of file def_LPBlackfin.h.

#define DCPLB_DATA7   0xFFE0021C /* Data Cache 7 Status */

Definition at line 257 of file def_LPBlackfin.h.

#define DCPLB_DATA8   0xFFE00220 /* Data Cache 8 Status */

Definition at line 258 of file def_LPBlackfin.h.

#define DCPLB_DATA9   0xFFE00224 /* Data Cache 9 Status */

Definition at line 259 of file def_LPBlackfin.h.

#define DCPLB_FAULT_ADDR
Value:
0xFFE0000C /* Data Cache Programmable Look-Aside
* Buffer Fault Address
*/

Definition at line 233 of file def_LPBlackfin.h.

#define DCPLB_FAULT_STATUS   0xFFE00008 /* "" (older define) */

Definition at line 232 of file def_LPBlackfin.h.

#define DCPLB_STATUS
Value:
0xFFE00008 /* Data Cache Programmable Look-Aside
* Buffer Status
*/

Definition at line 231 of file def_LPBlackfin.h.

#define DMC0_P   0x02 /* L1 Data Memory Configure bit 0 */

Definition at line 460 of file def_LPBlackfin.h.

#define DMC1_P   0x03 /* L1 Data Memory Configure bit 1 */

Definition at line 462 of file def_LPBlackfin.h.

#define DMCTL_DMC0_P   DMC0_P /* "" (older define) */

Definition at line 461 of file def_LPBlackfin.h.

#define DMCTL_DMC1_P   DMC1_P /* "" (older define) */

Definition at line 463 of file def_LPBlackfin.h.

#define DMCTL_ENDCPLB_P   ENDCPLB_P /* "" (older define) */

Definition at line 459 of file def_LPBlackfin.h.

#define DMCTL_ENDM_P   ENDM_P /* "" (older define) */

Definition at line 456 of file def_LPBlackfin.h.

#define DMEM_CONTROL   0xFFE00004 /* Data memory control */

Definition at line 230 of file def_LPBlackfin.h.

#define DSPID
Value:
0xFFE05000 /* DSP Processor ID Register for
* MP implementations
*/

Definition at line 347 of file def_LPBlackfin.h.

#define DTEST_COMMAND   0xFFE00300 /* Data Test Command Register */

Definition at line 268 of file def_LPBlackfin.h.

#define DTEST_DATA0   0xFFE00400 /* Data Test Data Register */

Definition at line 269 of file def_LPBlackfin.h.

#define DTEST_DATA1   0xFFE00404 /* Data Test Data Register */

Definition at line 270 of file def_LPBlackfin.h.

#define ENDCPLB   0x00000002 /* Enable DCPLB */

Definition at line 470 of file def_LPBlackfin.h.

#define ENDCPLB_P   0x01 /* Enable DCPLBS */

Definition at line 458 of file def_LPBlackfin.h.

#define ENDM
Value:
0x00000001 /* (doesn't really exist) Enable
* Data Memory L1
*/

Definition at line 469 of file def_LPBlackfin.h.

#define ENDM_P
Value:
0x00 /* (doesn't really exist) Enable
*Data Memory L1
*/

Definition at line 455 of file def_LPBlackfin.h.

#define ENICPLB   0x00000002 /* Enable ICPLB */

Definition at line 493 of file def_LPBlackfin.h.

#define ENICPLB_P   0x01 /* Enable ICPLB */

Definition at line 482 of file def_LPBlackfin.h.

#define ENIM   0x00000001 /* Enable L1 Code Memory */

Definition at line 492 of file def_LPBlackfin.h.

#define ENIM_P   0x00 /* Enable L1 Code Memory */

Definition at line 480 of file def_LPBlackfin.h.

#define EVT0   0xFFE02000 /* Event Vector 0 ESR Address */

Definition at line 317 of file def_LPBlackfin.h.

#define EVT1   0xFFE02004 /* Event Vector 1 ESR Address */

Definition at line 318 of file def_LPBlackfin.h.

#define EVT10   0xFFE02028 /* Event Vector 10 ESR Address */

Definition at line 327 of file def_LPBlackfin.h.

#define EVT11   0xFFE0202C /* Event Vector 11 ESR Address */

Definition at line 328 of file def_LPBlackfin.h.

#define EVT12   0xFFE02030 /* Event Vector 12 ESR Address */

Definition at line 329 of file def_LPBlackfin.h.

#define EVT13   0xFFE02034 /* Event Vector 13 ESR Address */

Definition at line 330 of file def_LPBlackfin.h.

#define EVT14   0xFFE02038 /* Event Vector 14 ESR Address */

Definition at line 331 of file def_LPBlackfin.h.

#define EVT15   0xFFE0203C /* Event Vector 15 ESR Address */

Definition at line 332 of file def_LPBlackfin.h.

#define EVT2   0xFFE02008 /* Event Vector 2 ESR Address */

Definition at line 319 of file def_LPBlackfin.h.

#define EVT3   0xFFE0200C /* Event Vector 3 ESR Address */

Definition at line 320 of file def_LPBlackfin.h.

#define EVT4   0xFFE02010 /* Event Vector 4 ESR Address */

Definition at line 321 of file def_LPBlackfin.h.

#define EVT5   0xFFE02014 /* Event Vector 5 ESR Address */

Definition at line 322 of file def_LPBlackfin.h.

#define EVT6   0xFFE02018 /* Event Vector 6 ESR Address */

Definition at line 323 of file def_LPBlackfin.h.

#define EVT7   0xFFE0201C /* Event Vector 7 ESR Address */

Definition at line 324 of file def_LPBlackfin.h.

#define EVT8   0xFFE02020 /* Event Vector 8 ESR Address */

Definition at line 325 of file def_LPBlackfin.h.

#define EVT9   0xFFE02024 /* Event Vector 9 ESR Address */

Definition at line 326 of file def_LPBlackfin.h.

#define EVT_EMU   MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */

Definition at line 434 of file def_LPBlackfin.h.

#define EVT_EMU_P   0x00000000 /* Emulator interrupt bit position */

Definition at line 416 of file def_LPBlackfin.h.

#define EVT_EVX   MK_BMSK_(EVT_EVX_P ) /* Exception mask */

Definition at line 437 of file def_LPBlackfin.h.

#define EVT_EVX_P   0x00000003 /* Exception bit position */

Definition at line 419 of file def_LPBlackfin.h.

#define EVT_IRPTEN   MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */

Definition at line 438 of file def_LPBlackfin.h.

#define EVT_IRPTEN_P   0x00000004 /* Global interrupt enable bit position */

Definition at line 420 of file def_LPBlackfin.h.

#define EVT_IVG10   MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */

Definition at line 444 of file def_LPBlackfin.h.

#define EVT_IVG10_P   0x0000000a /* IVG10 interrupt bit position */

Definition at line 426 of file def_LPBlackfin.h.

#define EVT_IVG11   MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */

Definition at line 445 of file def_LPBlackfin.h.

#define EVT_IVG11_P   0x0000000b /* IVG11 interrupt bit position */

Definition at line 427 of file def_LPBlackfin.h.

#define EVT_IVG12   MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */

Definition at line 446 of file def_LPBlackfin.h.

#define EVT_IVG12_P   0x0000000c /* IVG12 interrupt bit position */

Definition at line 428 of file def_LPBlackfin.h.

#define EVT_IVG13   MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */

Definition at line 447 of file def_LPBlackfin.h.

#define EVT_IVG13_P   0x0000000d /* IVG13 interrupt bit position */

Definition at line 429 of file def_LPBlackfin.h.

#define EVT_IVG14   MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */

Definition at line 448 of file def_LPBlackfin.h.

#define EVT_IVG14_P   0x0000000e /* IVG14 interrupt bit position */

Definition at line 430 of file def_LPBlackfin.h.

#define EVT_IVG15   MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */

Definition at line 449 of file def_LPBlackfin.h.

#define EVT_IVG15_P   0x0000000f /* IVG15 interrupt bit position */

Definition at line 431 of file def_LPBlackfin.h.

#define EVT_IVG7   MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */

Definition at line 441 of file def_LPBlackfin.h.

#define EVT_IVG7_P   0x00000007 /* IVG7 interrupt bit position */

Definition at line 423 of file def_LPBlackfin.h.

#define EVT_IVG8   MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */

Definition at line 442 of file def_LPBlackfin.h.

#define EVT_IVG8_P   0x00000008 /* IVG8 interrupt bit position */

Definition at line 424 of file def_LPBlackfin.h.

#define EVT_IVG9   MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */

Definition at line 443 of file def_LPBlackfin.h.

#define EVT_IVG9_P   0x00000009 /* IVG9 interrupt bit position */

Definition at line 425 of file def_LPBlackfin.h.

#define EVT_IVHW   MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */

Definition at line 439 of file def_LPBlackfin.h.

#define EVT_IVHW_P   0x00000005 /* Hardware Error interrupt bit position */

Definition at line 421 of file def_LPBlackfin.h.

#define EVT_IVTMR   MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */

Definition at line 440 of file def_LPBlackfin.h.

#define EVT_IVTMR_P   0x00000006 /* Timer interrupt bit position */

Definition at line 422 of file def_LPBlackfin.h.

#define EVT_NMI   MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */

Definition at line 436 of file def_LPBlackfin.h.

#define EVT_NMI_P   0x00000002 /* Non Maskable interrupt bit position */

Definition at line 418 of file def_LPBlackfin.h.

#define EVT_OVERRIDE   0xFFE02100 /* Event Vector Override Register */

Definition at line 333 of file def_LPBlackfin.h.

#define EVT_RST   MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */

Definition at line 435 of file def_LPBlackfin.h.

#define EVT_RST_P   0x00000001 /* Reset interrupt bit position */

Definition at line 417 of file def_LPBlackfin.h.

#define ICPLB_ADDR0
Value:
0xFFE01100 /* Instruction Cacheability
* Protection Lookaside Buffer 0
*/

Definition at line 279 of file def_LPBlackfin.h.

#define ICPLB_ADDR1
Value:
0xFFE01104 /* Instruction Cacheability
* Protection Lookaside Buffer 1
*/

Definition at line 280 of file def_LPBlackfin.h.

#define ICPLB_ADDR10
Value:
0xFFE01128 /* Instruction Cacheability
* Protection Lookaside Buffer 10
*/

Definition at line 289 of file def_LPBlackfin.h.

#define ICPLB_ADDR11
Value:
0xFFE0112C /* Instruction Cacheability
* Protection Lookaside Buffer 11
*/

Definition at line 290 of file def_LPBlackfin.h.

#define ICPLB_ADDR12
Value:
0xFFE01130 /* Instruction Cacheability
* Protection Lookaside Buffer 12
*/

Definition at line 291 of file def_LPBlackfin.h.

#define ICPLB_ADDR13
Value:
0xFFE01134 /* Instruction Cacheability
* Protection Lookaside Buffer 13
*/

Definition at line 292 of file def_LPBlackfin.h.

#define ICPLB_ADDR14
Value:
0xFFE01138 /* Instruction Cacheability
* Protection Lookaside Buffer 14
*/

Definition at line 293 of file def_LPBlackfin.h.

#define ICPLB_ADDR15
Value:
0xFFE0113C /* Instruction Cacheability
* Protection Lookaside Buffer 15
*/

Definition at line 294 of file def_LPBlackfin.h.

#define ICPLB_ADDR2
Value:
0xFFE01108 /* Instruction Cacheability
* Protection Lookaside Buffer 2
*/

Definition at line 281 of file def_LPBlackfin.h.

#define ICPLB_ADDR3
Value:
0xFFE0110C /* Instruction Cacheability
* Protection Lookaside Buffer 3
*/

Definition at line 282 of file def_LPBlackfin.h.

#define ICPLB_ADDR4
Value:
0xFFE01110 /* Instruction Cacheability
* Protection Lookaside Buffer 4
*/

Definition at line 283 of file def_LPBlackfin.h.

#define ICPLB_ADDR5
Value:
0xFFE01114 /* Instruction Cacheability
* Protection Lookaside Buffer 5
*/

Definition at line 284 of file def_LPBlackfin.h.

#define ICPLB_ADDR6
Value:
0xFFE01118 /* Instruction Cacheability
* Protection Lookaside Buffer 6
*/

Definition at line 285 of file def_LPBlackfin.h.

#define ICPLB_ADDR7
Value:
0xFFE0111C /* Instruction Cacheability
* Protection Lookaside Buffer 7
*/

Definition at line 286 of file def_LPBlackfin.h.

#define ICPLB_ADDR8
Value:
0xFFE01120 /* Instruction Cacheability
* Protection Lookaside Buffer 8
*/

Definition at line 287 of file def_LPBlackfin.h.

#define ICPLB_ADDR9
Value:
0xFFE01124 /* Instruction Cacheability
* Protection Lookaside Buffer 9
*/

Definition at line 288 of file def_LPBlackfin.h.

#define ICPLB_DATA0   0xFFE01200 /* Instruction Cache 0 Status */

Definition at line 295 of file def_LPBlackfin.h.

#define ICPLB_DATA1   0xFFE01204 /* Instruction Cache 1 Status */

Definition at line 296 of file def_LPBlackfin.h.

#define ICPLB_DATA10   0xFFE01228 /* Instruction Cache 10 Status */

Definition at line 305 of file def_LPBlackfin.h.

#define ICPLB_DATA11   0xFFE0122C /* Instruction Cache 11 Status */

Definition at line 306 of file def_LPBlackfin.h.

#define ICPLB_DATA12   0xFFE01230 /* Instruction Cache 12 Status */

Definition at line 307 of file def_LPBlackfin.h.

#define ICPLB_DATA13   0xFFE01234 /* Instruction Cache 13 Status */

Definition at line 308 of file def_LPBlackfin.h.

#define ICPLB_DATA14   0xFFE01238 /* Instruction Cache 14 Status */

Definition at line 309 of file def_LPBlackfin.h.

#define ICPLB_DATA15   0xFFE0123C /* Instruction Cache 15 Status */

Definition at line 310 of file def_LPBlackfin.h.

#define ICPLB_DATA2   0xFFE01208 /* Instruction Cache 2 Status */

Definition at line 297 of file def_LPBlackfin.h.

#define ICPLB_DATA3   0xFFE0120C /* Instruction Cache 3 Status */

Definition at line 298 of file def_LPBlackfin.h.

#define ICPLB_DATA4   0xFFE01210 /* Instruction Cache 4 Status */

Definition at line 299 of file def_LPBlackfin.h.

#define ICPLB_DATA5   0xFFE01214 /* Instruction Cache 5 Status */

Definition at line 300 of file def_LPBlackfin.h.

#define ICPLB_DATA6   0xFFE01218 /* Instruction Cache 6 Status */

Definition at line 301 of file def_LPBlackfin.h.

#define ICPLB_DATA7   0xFFE0121C /* Instruction Cache 7 Status */

Definition at line 302 of file def_LPBlackfin.h.

#define ICPLB_DATA8   0xFFE01220 /* Instruction Cache 8 Status */

Definition at line 303 of file def_LPBlackfin.h.

#define ICPLB_DATA9   0xFFE01224 /* Instruction Cache 9 Status */

Definition at line 304 of file def_LPBlackfin.h.

#define ICPLB_FAULT_ADDR   0xFFE0100C /* Instruction Cache miss address */

Definition at line 277 of file def_LPBlackfin.h.

#define ICPLB_STATUS   0xFFE01008 /* Instruction Cache miss status */

Definition at line 275 of file def_LPBlackfin.h.

#define ILAT   0xFFE0210C /* Interrupt Latch Register */

Definition at line 336 of file def_LPBlackfin.h.

#define ILOC0   0x00000008 /* Lock Way 0 */

Definition at line 495 of file def_LPBlackfin.h.

#define ILOC0_P   0x03 /* Lock Way 0 */

Definition at line 486 of file def_LPBlackfin.h.

#define ILOC1   0x00000010 /* Lock Way 1 */

Definition at line 496 of file def_LPBlackfin.h.

#define ILOC1_P   0x04 /* Lock Way 1 */

Definition at line 487 of file def_LPBlackfin.h.

#define ILOC2   0x00000020 /* Lock Way 2 */

Definition at line 497 of file def_LPBlackfin.h.

#define ILOC2_P   0x05 /* Lock Way 2 */

Definition at line 488 of file def_LPBlackfin.h.

#define ILOC3   0x00000040 /* Lock Way 3 */

Definition at line 498 of file def_LPBlackfin.h.

#define ILOC3_P   0x06 /* Lock Way 3 */

Definition at line 489 of file def_LPBlackfin.h.

#define IMASK   0xFFE02104 /* Interrupt Mask Register */

Definition at line 334 of file def_LPBlackfin.h.

#define IMC
Value:
0x00000004 /* Configure L1 code memory as
* cache (0=SRAM)
*/

Definition at line 494 of file def_LPBlackfin.h.

#define IMC_P   0x02 /* Enable */

Definition at line 484 of file def_LPBlackfin.h.

#define IMCTL_ENICPLB_P   0x01 /* "" (older define) */

Definition at line 483 of file def_LPBlackfin.h.

#define IMCTL_ENIM_P   0x00 /* "" (older define) */

Definition at line 481 of file def_LPBlackfin.h.

#define IMCTL_IMC_P
Value:
0x02 /* Configure L1 code memory as
* cache (0=SRAM)
*/

Definition at line 485 of file def_LPBlackfin.h.

#define IMEM_CONTROL   0xFFE01004 /* Instruction Memory Control */

Definition at line 274 of file def_LPBlackfin.h.

#define IPEND   0xFFE02108 /* Interrupt Pending Register */

Definition at line 335 of file def_LPBlackfin.h.

#define IPRIO   0xFFE02110 /* Core Interrupt Priority Register */

Definition at line 337 of file def_LPBlackfin.h.

#define ITEST_COMMAND   0xFFE01300 /* Instruction Test Command Register */

Definition at line 311 of file def_LPBlackfin.h.

#define ITEST_DATA0   0xFFE01400 /* Instruction Test Data Register */

Definition at line 312 of file def_LPBlackfin.h.

#define ITEST_DATA1   0xFFE01404 /* Instruction Test Data Register */

Definition at line 313 of file def_LPBlackfin.h.

#define LRUPRIORST
Value:
0x00002000 /* Least Recently Used Replacement
* Priority
*/

Definition at line 499 of file def_LPBlackfin.h.

#define LRUPRIORST_P
Value:
0x0D /* Least Recently Used Replacement
* Priority
*/

Definition at line 490 of file def_LPBlackfin.h.

#define MK_BMSK_ (   x)    (1<<x)

Definition at line 14 of file def_LPBlackfin.h.

#define NOP_PAD_ANOMALY_05000198

Definition at line 25 of file def_LPBlackfin.h.

#define PAGE_SIZE_16KB   0x00040000 /* 16 KB page size */

Definition at line 521 of file def_LPBlackfin.h.

#define PAGE_SIZE_16MB   0x00060000 /* 16 MB page size */

Definition at line 523 of file def_LPBlackfin.h.

#define PAGE_SIZE_1KB   0x00000000 /* 1 KB page size */

Definition at line 517 of file def_LPBlackfin.h.

#define PAGE_SIZE_1MB   0x00020000 /* 1 MB page size */

Definition at line 519 of file def_LPBlackfin.h.

#define PAGE_SIZE_4KB   0x00010000 /* 4 KB page size */

Definition at line 518 of file def_LPBlackfin.h.

#define PAGE_SIZE_4MB   0x00030000 /* 4 MB page size */

Definition at line 520 of file def_LPBlackfin.h.

#define PAGE_SIZE_64KB   0x00050000 /* 64 KB page size */

Definition at line 522 of file def_LPBlackfin.h.

#define PAGE_SIZE_64MB   0x00070000 /* 64 MB page size */

Definition at line 524 of file def_LPBlackfin.h.

#define PFCNTR0   0xFFE08100

Definition at line 403 of file def_LPBlackfin.h.

#define PFCNTR1   0xFFE08104

Definition at line 405 of file def_LPBlackfin.h.

#define PFCTL   0xFFE08000

Definition at line 401 of file def_LPBlackfin.h.

#define PORT_PREF0   0x00001000 /* DAG0 Port Preference */

Definition at line 475 of file def_LPBlackfin.h.

#define PORT_PREF0_P   0x12 /* DAG0 Port Preference */

Definition at line 465 of file def_LPBlackfin.h.

#define PORT_PREF1   0x00002000 /* DAG1 Port Preference */

Definition at line 476 of file def_LPBlackfin.h.

#define PORT_PREF1_P   0x13 /* DAG1 Port Preference */

Definition at line 466 of file def_LPBlackfin.h.

#define SEQSTAT_EXCAUSE
Value:
(MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
0)

Definition at line 172 of file def_LPBlackfin.h.

#define SEQSTAT_EXCAUSE0_P   0x00000000 /* Last exception cause bit 0 */

Definition at line 157 of file def_LPBlackfin.h.

#define SEQSTAT_EXCAUSE1_P   0x00000001 /* Last exception cause bit 1 */

Definition at line 158 of file def_LPBlackfin.h.

#define SEQSTAT_EXCAUSE2_P   0x00000002 /* Last exception cause bit 2 */

Definition at line 159 of file def_LPBlackfin.h.

#define SEQSTAT_EXCAUSE3_P   0x00000003 /* Last exception cause bit 3 */

Definition at line 160 of file def_LPBlackfin.h.

#define SEQSTAT_EXCAUSE4_P   0x00000004 /* Last exception cause bit 4 */

Definition at line 161 of file def_LPBlackfin.h.

#define SEQSTAT_EXCAUSE5_P   0x00000005 /* Last exception cause bit 5 */

Definition at line 162 of file def_LPBlackfin.h.

#define SEQSTAT_HWERRCAUSE
Value:
(MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
0)

Definition at line 184 of file def_LPBlackfin.h.

#define SEQSTAT_HWERRCAUSE0_P   0x0000000E /* Last hw error cause bit 0 */

Definition at line 165 of file def_LPBlackfin.h.

#define SEQSTAT_HWERRCAUSE1_P   0x0000000F /* Last hw error cause bit 1 */

Definition at line 166 of file def_LPBlackfin.h.

#define SEQSTAT_HWERRCAUSE2_P   0x00000010 /* Last hw error cause bit 2 */

Definition at line 167 of file def_LPBlackfin.h.

#define SEQSTAT_HWERRCAUSE3_P   0x00000011 /* Last hw error cause bit 3 */

Definition at line 168 of file def_LPBlackfin.h.

#define SEQSTAT_HWERRCAUSE4_P   0x00000012 /* Last hw error cause bit 4 */

Definition at line 169 of file def_LPBlackfin.h.

#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR   (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)

Definition at line 196 of file def_LPBlackfin.h.

#define SEQSTAT_HWERRCAUSE_PERF_FLOW   (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)

Definition at line 197 of file def_LPBlackfin.h.

#define SEQSTAT_HWERRCAUSE_RAISE_5   (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)

Definition at line 198 of file def_LPBlackfin.h.

#define SEQSTAT_HWERRCAUSE_SHIFT   (14)

Definition at line 194 of file def_LPBlackfin.h.

#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR   (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)

Definition at line 195 of file def_LPBlackfin.h.

#define SEQSTAT_IDLE_REQ_P
Value:
0x0000000C /* Pending idle mode request,
* set by IDLE instruction.
*/

Definition at line 163 of file def_LPBlackfin.h.

#define SEQSTAT_SFTRESET   (MK_BMSK_(SEQSTAT_SFTRESET_P))

Definition at line 181 of file def_LPBlackfin.h.

#define SEQSTAT_SFTRESET_P
Value:
0x0000000D /* Indicates whether the last
* reset was a software reset
* (=1)
*/

Definition at line 164 of file def_LPBlackfin.h.

#define SRAM_BASE_ADDRESS   0xFFE00000 /* SRAM Base Address Register */

Definition at line 229 of file def_LPBlackfin.h.

#define SYSCFG_CCCEN   SYSCFG_CCEN

Definition at line 221 of file def_LPBlackfin.h.

#define SYSCFG_CCEN   MK_BMSK_(SYSCFG_CCEN_P )

Definition at line 216 of file def_LPBlackfin.h.

#define SYSCFG_CCEN_P   0x00000001 /* Enable cycle counter (=1) */

Definition at line 206 of file def_LPBlackfin.h.

#define SYSCFG_SNEN   MK_BMSK_(SYSCFG_SNEN_P)

Definition at line 218 of file def_LPBlackfin.h.

#define SYSCFG_SNEN_P   0x00000002 /* Self nesting Interrupt Enable */

Definition at line 207 of file def_LPBlackfin.h.

#define SYSCFG_SSSSTEP   SYSCFG_SSSTEP

Definition at line 220 of file def_LPBlackfin.h.

#define SYSCFG_SSSTEP   MK_BMSK_(SYSCFG_SSSTEP_P )

Definition at line 214 of file def_LPBlackfin.h.

#define SYSCFG_SSSTEP_P
Value:
0x00000000 /* Supervisor single step, when
* set it forces an exception
* for each instruction executed
*/

Definition at line 205 of file def_LPBlackfin.h.

#define TAUTORLD   0x00000004 /* Timer auto reload */

Definition at line 504 of file def_LPBlackfin.h.

#define TBUF   0xFFE06100 /* Trace Buffer */

Definition at line 355 of file def_LPBlackfin.h.

#define TBUFCMPLP   (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)

Definition at line 545 of file def_LPBlackfin.h.

#define TBUFCMPLP_DOUBLE   0x0010

Definition at line 544 of file def_LPBlackfin.h.

#define TBUFCMPLP_SINGLE   0x0008

Definition at line 543 of file def_LPBlackfin.h.

#define TBUFCNT   0x001F

Definition at line 548 of file def_LPBlackfin.h.

#define TBUFCTL   0xFFE06000 /* Trace Buffer Control Register */

Definition at line 353 of file def_LPBlackfin.h.

#define TBUFEN   0x0002

Definition at line 541 of file def_LPBlackfin.h.

#define TBUFOVF   0x0004

Definition at line 542 of file def_LPBlackfin.h.

#define TBUFPWR   0x0001

Definition at line 540 of file def_LPBlackfin.h.

#define TBUFSTAT   0xFFE06004 /* Trace Buffer Status Register */

Definition at line 354 of file def_LPBlackfin.h.

#define TCNTL   0xFFE03000 /* Core Timer Control Register */

Definition at line 341 of file def_LPBlackfin.h.

#define TCOUNT   0xFFE0300C /* Core Timer Count Register */

Definition at line 344 of file def_LPBlackfin.h.

#define TEST_BNKSELA   0x00000000 /* Access SuperBank A */

Definition at line 571 of file def_LPBlackfin.h.

#define TEST_BNKSELB   0x00800000 /* Access SuperBank B */

Definition at line 572 of file def_LPBlackfin.h.

#define TEST_DATA   0x00000004 /* Access DATA */

Definition at line 555 of file def_LPBlackfin.h.

#define TEST_DW0   0x00000000 /* Select Double Word 0 */

Definition at line 556 of file def_LPBlackfin.h.

#define TEST_DW1   0x00000008 /* Select Double Word 1 */

Definition at line 557 of file def_LPBlackfin.h.

#define TEST_DW2   0x00000010 /* Select Double Word 2 */

Definition at line 558 of file def_LPBlackfin.h.

#define TEST_DW3   0x00000018 /* Select Double Word 3 */

Definition at line 559 of file def_LPBlackfin.h.

#define TEST_MB0   0x00000000 /* Select Mini-Bank 0 */

Definition at line 560 of file def_LPBlackfin.h.

#define TEST_MB1   0x00010000 /* Select Mini-Bank 1 */

Definition at line 561 of file def_LPBlackfin.h.

#define TEST_MB2   0x00020000 /* Select Mini-Bank 2 */

Definition at line 562 of file def_LPBlackfin.h.

#define TEST_MB3   0x00030000 /* Select Mini-Bank 3 */

Definition at line 563 of file def_LPBlackfin.h.

#define TEST_READ   0x00000000 /* Read Access */

Definition at line 552 of file def_LPBlackfin.h.

#define TEST_SET (   x)    ((x << 5) & 0x03E0) /* Set Index 0->31 */

Definition at line 564 of file def_LPBlackfin.h.

#define TEST_TAG   0x00000000 /* Access TAG */

Definition at line 554 of file def_LPBlackfin.h.

#define TEST_WAY0   0x00000000 /* Access Way0 */

Definition at line 565 of file def_LPBlackfin.h.

#define TEST_WAY1   0x04000000 /* Access Way1 */

Definition at line 566 of file def_LPBlackfin.h.

#define TEST_WAY2   0x08000000 /* Access Way2 */

Definition at line 568 of file def_LPBlackfin.h.

#define TEST_WAY3   0x0C000000 /* Access Way3 */

Definition at line 569 of file def_LPBlackfin.h.

#define TEST_WRITE   0x00000002 /* Write Access */

Definition at line 553 of file def_LPBlackfin.h.

#define TINT
Value:
0x00000008 /* Timer generated interrupt 0=no
* interrupt has been generated,
* 1=interrupt has been generated
* (sticky)
*/

Definition at line 505 of file def_LPBlackfin.h.

#define TMPWR
Value:
0x00000001 /* Timer Low Power Control,
* 0=low power mode, 1=active state
*/

Definition at line 502 of file def_LPBlackfin.h.

#define TMREN   0x00000002 /* Timer enable, 0=disable, 1=enable */

Definition at line 503 of file def_LPBlackfin.h.

#define TPERIOD   0xFFE03004 /* Core Timer Period Register */

Definition at line 342 of file def_LPBlackfin.h.

#define TSCALE   0xFFE03008 /* Core Timer Scale Register */

Definition at line 343 of file def_LPBlackfin.h.

#define WPDA0   0xFFE07140

Definition at line 388 of file def_LPBlackfin.h.

#define WPDA1   0xFFE07144

Definition at line 390 of file def_LPBlackfin.h.

#define WPDACNT0   0xFFE07180

Definition at line 392 of file def_LPBlackfin.h.

#define WPDACNT1   0xFFE07184

Definition at line 394 of file def_LPBlackfin.h.

#define WPDACTL   0xFFE07100

Definition at line 386 of file def_LPBlackfin.h.

#define WPIA0   0xFFE07040

Definition at line 362 of file def_LPBlackfin.h.

#define WPIA1   0xFFE07044

Definition at line 364 of file def_LPBlackfin.h.

#define WPIA2   0xFFE07048

Definition at line 366 of file def_LPBlackfin.h.

#define WPIA3   0xFFE0704C

Definition at line 368 of file def_LPBlackfin.h.

#define WPIA4   0xFFE07050

Definition at line 370 of file def_LPBlackfin.h.

#define WPIA5   0xFFE07054

Definition at line 372 of file def_LPBlackfin.h.

#define WPIACNT0   0xFFE07080

Definition at line 374 of file def_LPBlackfin.h.

#define WPIACNT1   0xFFE07084

Definition at line 376 of file def_LPBlackfin.h.

#define WPIACNT2   0xFFE07088

Definition at line 378 of file def_LPBlackfin.h.

#define WPIACNT3   0xFFE0708C

Definition at line 380 of file def_LPBlackfin.h.

#define WPIACNT4   0xFFE07090

Definition at line 382 of file def_LPBlackfin.h.

#define WPIACNT5   0xFFE07094

Definition at line 384 of file def_LPBlackfin.h.

#define WPIACTL   0xFFE07000

Definition at line 360 of file def_LPBlackfin.h.

#define WPSTAT   0xFFE07200

Definition at line 396 of file def_LPBlackfin.h.

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