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Data Structures | Macros
dc395x.h File Reference

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Data Structures

struct  ScsiInqData
 

Macros

#define DC395x_MAX_CMD_QUEUE   32
 
#define DC395x_MAX_QTAGS   16
 
#define DC395x_MAX_SCSI_ID   16
 
#define DC395x_MAX_CMD_PER_LUN   DC395x_MAX_QTAGS
 
#define DC395x_MAX_SG_TABLESIZE   64 /* HW limitation */
 
#define DC395x_MAX_SG_LISTENTRY   64 /* Must be equal or lower to previous */
 
#define DC395x_MAX_SRB_CNT   63
 
#define DC395x_MAX_CAN_QUEUE   DC395x_MAX_SRB_CNT
 
#define DC395x_END_SCAN   2
 
#define DC395x_SEL_TIMEOUT   153 /* 250 ms selection timeout (@ 40 MHz) */
 
#define DC395x_MAX_RETRIES   3
 
#define NORM_REC_LVL   0
 
#define BIT31   0x80000000
 
#define BIT30   0x40000000
 
#define BIT29   0x20000000
 
#define BIT28   0x10000000
 
#define BIT27   0x08000000
 
#define BIT26   0x04000000
 
#define BIT25   0x02000000
 
#define BIT24   0x01000000
 
#define BIT23   0x00800000
 
#define BIT22   0x00400000
 
#define BIT21   0x00200000
 
#define BIT20   0x00100000
 
#define BIT19   0x00080000
 
#define BIT18   0x00040000
 
#define BIT17   0x00020000
 
#define BIT16   0x00010000
 
#define BIT15   0x00008000
 
#define BIT14   0x00004000
 
#define BIT13   0x00002000
 
#define BIT12   0x00001000
 
#define BIT11   0x00000800
 
#define BIT10   0x00000400
 
#define BIT9   0x00000200
 
#define BIT8   0x00000100
 
#define BIT7   0x00000080
 
#define BIT6   0x00000040
 
#define BIT5   0x00000020
 
#define BIT4   0x00000010
 
#define BIT3   0x00000008
 
#define BIT2   0x00000004
 
#define BIT1   0x00000002
 
#define BIT0   0x00000001
 
#define UNIT_ALLOCATED   BIT0
 
#define UNIT_INFO_CHANGED   BIT1
 
#define FORMATING_MEDIA   BIT2
 
#define UNIT_RETRY   BIT3
 
#define DASD_SUPPORT   BIT0
 
#define SCSI_SUPPORT   BIT1
 
#define ASPI_SUPPORT   BIT2
 
#define SRB_FREE   0x0000
 
#define SRB_WAIT   0x0001
 
#define SRB_READY   0x0002
 
#define SRB_MSGOUT   0x0004 /* arbitration+msg_out 1st byte */
 
#define SRB_MSGIN   0x0008
 
#define SRB_EXTEND_MSGIN   0x0010
 
#define SRB_COMMAND   0x0020
 
#define SRB_START_   0x0040 /* arbitration+msg_out+command_out */
 
#define SRB_DISCONNECT   0x0080
 
#define SRB_DATA_XFER   0x0100
 
#define SRB_XFERPAD   0x0200
 
#define SRB_STATUS   0x0400
 
#define SRB_COMPLETED   0x0800
 
#define SRB_ABORT_SENT   0x1000
 
#define SRB_DO_SYNC_NEGO   0x2000
 
#define SRB_DO_WIDE_NEGO   0x4000
 
#define SRB_UNEXPECT_RESEL   0x8000
 
#define HCC_WIDE_CARD   0x20
 
#define HCC_SCSI_RESET   0x10
 
#define HCC_PARITY   0x08
 
#define HCC_AUTOTERM   0x04
 
#define HCC_LOW8TERM   0x02
 
#define HCC_UP8TERM   0x01
 
#define RESET_DEV   BIT0
 
#define RESET_DETECT   BIT1
 
#define RESET_DONE   BIT2
 
#define ABORT_DEV_   BIT0
 
#define SRB_OK   BIT0
 
#define ABORTION   BIT1
 
#define OVER_RUN   BIT2
 
#define UNDER_RUN   BIT3
 
#define PARITY_ERROR   BIT4
 
#define SRB_ERROR   BIT5
 
#define DATAOUT   BIT7
 
#define DATAIN   BIT6
 
#define RESIDUAL_VALID   BIT5
 
#define ENABLE_TIMER   BIT4
 
#define RESET_DEV0   BIT2
 
#define ABORT_DEV   BIT1
 
#define AUTO_REQSENSE   BIT0
 
#define H_STATUS_GOOD   0
 
#define H_SEL_TIMEOUT   0x11
 
#define H_OVER_UNDER_RUN   0x12
 
#define H_UNEXP_BUS_FREE   0x13
 
#define H_TARGET_PHASE_F   0x14
 
#define H_INVALID_CCB_OP   0x16
 
#define H_LINK_CCB_BAD   0x17
 
#define H_BAD_TARGET_DIR   0x18
 
#define H_DUPLICATE_CCB   0x19
 
#define H_BAD_CCB_OR_SG   0x1A
 
#define H_ABORT   0x0FF
 
#define SCSI_STAT_GOOD   0x0 /* Good status */
 
#define SCSI_STAT_CHECKCOND   0x02 /* SCSI Check Condition */
 
#define SCSI_STAT_CONDMET   0x04 /* Condition Met */
 
#define SCSI_STAT_BUSY   0x08 /* Target busy status */
 
#define SCSI_STAT_INTER   0x10 /* Intermediate status */
 
#define SCSI_STAT_INTERCONDMET   0x14 /* Intermediate condition met */
 
#define SCSI_STAT_RESCONFLICT   0x18 /* Reservation conflict */
 
#define SCSI_STAT_CMDTERM   0x22 /* Command Terminated */
 
#define SCSI_STAT_QUEUEFULL   0x28 /* Queue Full */
 
#define SCSI_STAT_UNEXP_BUS_F   0xFD /* Unexpect Bus Free */
 
#define SCSI_STAT_BUS_RST_DETECT   0xFE /* Scsi Bus Reset detected */
 
#define SCSI_STAT_SEL_TIMEOUT   0xFF /* Selection Time out */
 
#define SYNC_WIDE_TAG_ATNT_DISABLE   0
 
#define SYNC_NEGO_ENABLE   BIT0
 
#define SYNC_NEGO_DONE   BIT1
 
#define WIDE_NEGO_ENABLE   BIT2
 
#define WIDE_NEGO_DONE   BIT3
 
#define WIDE_NEGO_STATE   BIT4
 
#define EN_TAG_QUEUEING   BIT5
 
#define EN_ATN_STOP   BIT6
 
#define SYNC_NEGO_OFFSET   15
 
#define MSG_COMPLETE   0x00
 
#define MSG_EXTENDED   0x01
 
#define MSG_SAVE_PTR   0x02
 
#define MSG_RESTORE_PTR   0x03
 
#define MSG_DISCONNECT   0x04
 
#define MSG_INITIATOR_ERROR   0x05
 
#define MSG_ABORT   0x06
 
#define MSG_REJECT_   0x07
 
#define MSG_NOP   0x08
 
#define MSG_PARITY_ERROR   0x09
 
#define MSG_LINK_CMD_COMPL   0x0A
 
#define MSG_LINK_CMD_COMPL_FLG   0x0B
 
#define MSG_BUS_RESET   0x0C
 
#define MSG_ABORT_TAG   0x0D
 
#define MSG_SIMPLE_QTAG   0x20
 
#define MSG_HEAD_QTAG   0x21
 
#define MSG_ORDER_QTAG   0x22
 
#define MSG_IGNOREWIDE   0x23
 
#define MSG_IDENTIFY   0x80
 
#define MSG_HOST_ID   0xC0
 
#define STATUS_GOOD   0x00
 
#define CHECK_CONDITION_   0x02
 
#define STATUS_BUSY   0x08
 
#define STATUS_INTERMEDIATE   0x10
 
#define RESERVE_CONFLICT   0x18
 
#define STATUS_MASK_   0xFF
 
#define MSG_MASK   0xFF00
 
#define RETURN_MASK   0xFF0000
 
#define SCSI_DEVTYPE   0x1F /* Peripheral Device Type */
 
#define SCSI_PERIPHQUAL   0xE0 /* Peripheral Qualifier */
 
#define SCSI_REMOVABLE_MEDIA   0x80 /* Removable Media bit (1=removable) */
 
#define TYPE_NODEV   SCSI_DEVTYPE /* Unknown or no device type */
 
#define TYPE_PRINTER   0x02 /* Printer device */
 
#define TYPE_COMM   0x09 /* Communications device */
 
#define SCSI_INQ_RELADR   0x80 /* device supports relative addressing */
 
#define SCSI_INQ_WBUS32   0x40 /* device supports 32 bit data xfers */
 
#define SCSI_INQ_WBUS16   0x20 /* device supports 16 bit data xfers */
 
#define SCSI_INQ_SYNC   0x10 /* device supports synchronous xfer */
 
#define SCSI_INQ_LINKED   0x08 /* device supports linked commands */
 
#define SCSI_INQ_CMDQUEUE   0x02 /* device supports command queueing */
 
#define SCSI_INQ_SFTRE   0x01 /* device supports soft resets */
 
#define ENABLE_CE   1
 
#define DISABLE_CE   0
 
#define EEPROM_READ   0x80
 
#define TRM_S1040_ID   0x00 /* Vendor and Device ID */
 
#define TRM_S1040_COMMAND   0x04 /* PCI command register */
 
#define TRM_S1040_IOBASE   0x10 /* I/O Space base address */
 
#define TRM_S1040_ROMBASE   0x30 /* Expansion ROM Base Address */
 
#define TRM_S1040_INTLINE   0x3C /* Interrupt line */
 
#define TRM_S1040_SCSI_STATUS   0x80 /* SCSI Status (R) */
 
#define COMMANDPHASEDONE   0x2000 /* SCSI command phase done */
 
#define SCSIXFERDONE   0x0800 /* SCSI SCSI transfer done */
 
#define SCSIXFERCNT_2_ZERO   0x0100 /* SCSI SCSI transfer count to zero */
 
#define SCSIINTERRUPT   0x0080 /* SCSI interrupt pending */
 
#define COMMANDABORT   0x0040 /* SCSI command abort */
 
#define SEQUENCERACTIVE   0x0020 /* SCSI sequencer active */
 
#define PHASEMISMATCH   0x0010 /* SCSI phase mismatch */
 
#define PARITYERROR   0x0008 /* SCSI parity error */
 
#define PHASEMASK   0x0007 /* Phase MSG/CD/IO */
 
#define PH_DATA_OUT   0x00 /* Data out phase */
 
#define PH_DATA_IN   0x01 /* Data in phase */
 
#define PH_COMMAND   0x02 /* Command phase */
 
#define PH_STATUS   0x03 /* Status phase */
 
#define PH_BUS_FREE   0x05 /* Invalid phase used as bus free */
 
#define PH_MSG_OUT   0x06 /* Message out phase */
 
#define PH_MSG_IN   0x07 /* Message in phase */
 
#define TRM_S1040_SCSI_CONTROL   0x80 /* SCSI Control (W) */
 
#define DO_CLRATN   0x0400 /* Clear ATN */
 
#define DO_SETATN   0x0200 /* Set ATN */
 
#define DO_CMDABORT   0x0100 /* Abort SCSI command */
 
#define DO_RSTMODULE   0x0010 /* Reset SCSI chip */
 
#define DO_RSTSCSI   0x0008 /* Reset SCSI bus */
 
#define DO_CLRFIFO   0x0004 /* Clear SCSI transfer FIFO */
 
#define DO_DATALATCH   0x0002 /* Enable SCSI bus data input (latched) */
 
#define DO_HWRESELECT   0x0001 /* Enable hardware reselection */
 
#define TRM_S1040_SCSI_FIFOCNT   0x82 /* SCSI FIFO Counter 5bits(R) */
 
#define TRM_S1040_SCSI_SIGNAL   0x83 /* SCSI low level signal (R/W) */
 
#define TRM_S1040_SCSI_INTSTATUS   0x84 /* SCSI Interrupt Status (R) */
 
#define INT_SCAM   0x80 /* SCAM selection interrupt */
 
#define INT_SELECT   0x40 /* Selection interrupt */
 
#define INT_SELTIMEOUT   0x20 /* Selection timeout interrupt */
 
#define INT_DISCONNECT   0x10 /* Bus disconnected interrupt */
 
#define INT_RESELECTED   0x08 /* Reselected interrupt */
 
#define INT_SCSIRESET   0x04 /* SCSI reset detected interrupt */
 
#define INT_BUSSERVICE   0x02 /* Bus service interrupt */
 
#define INT_CMDDONE   0x01 /* SCSI command done interrupt */
 
#define TRM_S1040_SCSI_OFFSET   0x84 /* SCSI Offset Count (W) */
 
#define TRM_S1040_SCSI_SYNC   0x85 /* SCSI Synchronous Control (R/W) */
 
#define LVDS_SYNC   0x20 /* Enable LVDS synchronous */
 
#define WIDE_SYNC   0x10 /* Enable WIDE synchronous */
 
#define ALT_SYNC   0x08 /* Enable Fast-20 alternate synchronous */
 
#define TRM_S1040_SCSI_TARGETID   0x86 /* SCSI Target ID (R/W) */
 
#define TRM_S1040_SCSI_IDMSG   0x87 /* SCSI Identify Message (R) */
 
#define TRM_S1040_SCSI_HOSTID   0x87 /* SCSI Host ID (W) */
 
#define TRM_S1040_SCSI_COUNTER   0x88 /* SCSI Transfer Counter 24bits(R/W) */
 
#define TRM_S1040_SCSI_INTEN   0x8C /* SCSI Interrupt Enable (R/W) */
 
#define EN_SCAM   0x80 /* Enable SCAM selection interrupt */
 
#define EN_SELECT   0x40 /* Enable selection interrupt */
 
#define EN_SELTIMEOUT   0x20 /* Enable selection timeout interrupt */
 
#define EN_DISCONNECT   0x10 /* Enable bus disconnected interrupt */
 
#define EN_RESELECTED   0x08 /* Enable reselected interrupt */
 
#define EN_SCSIRESET   0x04 /* Enable SCSI reset detected interrupt */
 
#define EN_BUSSERVICE   0x02 /* Enable bus service interrupt */
 
#define EN_CMDDONE   0x01 /* Enable SCSI command done interrupt */
 
#define TRM_S1040_SCSI_CONFIG0   0x8D /* SCSI Configuration 0 (R/W) */
 
#define PHASELATCH   0x40 /* Enable phase latch */
 
#define INITIATOR   0x20 /* Enable initiator mode */
 
#define PARITYCHECK   0x10 /* Enable parity check */
 
#define BLOCKRST   0x01 /* Disable SCSI reset1 */
 
#define TRM_S1040_SCSI_CONFIG1   0x8E /* SCSI Configuration 1 (R/W) */
 
#define ACTIVE_NEGPLUS   0x10 /* Enhance active negation */
 
#define FILTER_DISABLE   0x08 /* Disable SCSI data filter */
 
#define FAST_FILTER   0x04 /* ? */
 
#define ACTIVE_NEG   0x02 /* Enable active negation */
 
#define TRM_S1040_SCSI_CONFIG2   0x8F /* SCSI Configuration 2 (R/W) */
 
#define CFG2_WIDEFIFO   0x02 /* */
 
#define TRM_S1040_SCSI_COMMAND   0x90 /* SCSI Command (R/W) */
 
#define SCMD_COMP   0x12 /* Command complete */
 
#define SCMD_SEL_ATN   0x60 /* Selection with ATN */
 
#define SCMD_SEL_ATN3   0x64 /* Selection with ATN3 */
 
#define SCMD_SEL_ATNSTOP   0xB8 /* Selection with ATN and Stop */
 
#define SCMD_FIFO_OUT   0xC0 /* SCSI FIFO transfer out */
 
#define SCMD_DMA_OUT   0xC1 /* SCSI DMA transfer out */
 
#define SCMD_FIFO_IN   0xC2 /* SCSI FIFO transfer in */
 
#define SCMD_DMA_IN   0xC3 /* SCSI DMA transfer in */
 
#define SCMD_MSGACCEPT   0xD8 /* Message accept */
 
#define TRM_S1040_SCSI_TIMEOUT   0x91 /* SCSI Time Out Value (R/W) */
 
#define TRM_S1040_SCSI_FIFO   0x98 /* SCSI FIFO (R/W) */
 
#define TRM_S1040_SCSI_TCR0   0x9C /* SCSI Target Control 0 (R/W) */
 
#define TCR0_WIDE_NEGO_DONE   0x8000 /* Wide nego done */
 
#define TCR0_SYNC_NEGO_DONE   0x4000 /* Synchronous nego done */
 
#define TCR0_ENABLE_LVDS   0x2000 /* Enable LVDS synchronous */
 
#define TCR0_ENABLE_WIDE   0x1000 /* Enable WIDE synchronous */
 
#define TCR0_ENABLE_ALT   0x0800 /* Enable alternate synchronous */
 
#define TCR0_PERIOD_MASK   0x0700 /* Transfer rate */
 
#define TCR0_DO_WIDE_NEGO   0x0080 /* Do wide NEGO */
 
#define TCR0_DO_SYNC_NEGO   0x0040 /* Do sync NEGO */
 
#define TCR0_DISCONNECT_EN   0x0020 /* Disconnection enable */
 
#define TCR0_OFFSET_MASK   0x001F /* Offset number */
 
#define TRM_S1040_SCSI_TCR1   0x9E /* SCSI Target Control 1 (R/W) */
 
#define MAXTAG_MASK   0x7F00 /* Maximum tags (127) */
 
#define NON_TAG_BUSY   0x0080 /* Non tag command active */
 
#define ACTTAG_MASK   0x007F /* Active tags */
 
#define TRM_S1040_DMA_COMMAND   0xA0 /* DMA Command (R/W) */
 
#define DMACMD_SG   0x02 /* Enable HW S/G support */
 
#define DMACMD_DIR   0x01 /* 1 = read from SCSI write to Host */
 
#define XFERDATAIN_SG   0x0103 /* Transfer data in w/ SG */
 
#define XFERDATAOUT_SG   0x0102 /* Transfer data out w/ SG */
 
#define XFERDATAIN   0x0101 /* Transfer data in w/o SG */
 
#define XFERDATAOUT   0x0100 /* Transfer data out w/o SG */
 
#define TRM_S1040_DMA_FIFOCNT   0xA1 /* DMA FIFO Counter (R) */
 
#define TRM_S1040_DMA_CONTROL   0xA1 /* DMA Control (W) */
 
#define DMARESETMODULE   0x10 /* Reset PCI/DMA module */
 
#define STOPDMAXFER   0x08 /* Stop DMA transfer */
 
#define ABORTXFER   0x04 /* Abort DMA transfer */
 
#define CLRXFIFO   0x02 /* Clear DMA transfer FIFO */
 
#define STARTDMAXFER   0x01 /* Start DMA transfer */
 
#define TRM_S1040_DMA_FIFOSTAT   0xA2 /* DMA FIFO Status (R) */
 
#define TRM_S1040_DMA_STATUS   0xA3 /* DMA Interrupt Status (R/W) */
 
#define XFERPENDING   0x80 /* Transfer pending */
 
#define SCSIBUSY   0x40 /* SCSI busy */
 
#define GLOBALINT   0x20 /* DMA_INTEN bit 0-4 set */
 
#define FORCEDMACOMP   0x10 /* Force DMA transfer complete */
 
#define DMAXFERERROR   0x08 /* DMA transfer error */
 
#define DMAXFERABORT   0x04 /* DMA transfer abort */
 
#define DMAXFERCOMP   0x02 /* Bus Master XFER Complete status */
 
#define SCSICOMP   0x01 /* SCSI complete interrupt */
 
#define TRM_S1040_DMA_INTEN   0xA4 /* DMA Interrupt Enable (R/W) */
 
#define EN_FORCEDMACOMP   0x10 /* Force DMA transfer complete */
 
#define EN_DMAXFERERROR   0x08 /* DMA transfer error */
 
#define EN_DMAXFERABORT   0x04 /* DMA transfer abort */
 
#define EN_DMAXFERCOMP   0x02 /* Bus Master XFER Complete status */
 
#define EN_SCSIINTR   0x01 /* Enable SCSI complete interrupt */
 
#define TRM_S1040_DMA_CONFIG   0xA6 /* DMA Configuration (R/W) */
 
#define DMA_ENHANCE   0x8000 /* Enable DMA enhance feature (SG?) */
 
#define DMA_PCI_DUAL_ADDR   0x4000 /* */
 
#define DMA_CFG_RES   0x2000 /* Always 1 */
 
#define DMA_AUTO_CLR_FIFO   0x1000 /* DISable DMA auto clear FIFO */
 
#define DMA_MEM_MULTI_READ   0x0800 /* */
 
#define DMA_MEM_WRITE_INVAL   0x0400 /* Memory write and invalidate */
 
#define DMA_FIFO_CTRL   0x0300 /* Control FIFO operation with DMA */
 
#define DMA_FIFO_HALF_HALF   0x0200 /* Keep half filled on both read/write */
 
#define TRM_S1040_DMA_XCNT   0xA8 /* DMA Transfer Counter (R/W), 24bits */
 
#define TRM_S1040_DMA_CXCNT   0xAC /* DMA Current Transfer Counter (R) */
 
#define TRM_S1040_DMA_XLOWADDR   0xB0 /* DMA Transfer Physical Low Address */
 
#define TRM_S1040_DMA_XHIGHADDR   0xB4 /* DMA Transfer Physical High Address */
 
#define TRM_S1040_GEN_CONTROL   0xD4 /* Global Control */
 
#define CTRL_LED   0x80 /* Control onboard LED */
 
#define EN_EEPROM   0x10 /* Enable EEPROM programming */
 
#define DIS_TERM   0x08 /* Disable onboard termination */
 
#define AUTOTERM   0x04 /* Enable Auto SCSI terminator */
 
#define LOW8TERM   0x02 /* Enable Lower 8 bit SCSI terminator */
 
#define UP8TERM   0x01 /* Enable Upper 8 bit SCSI terminator */
 
#define TRM_S1040_GEN_STATUS   0xD5 /* Global Status */
 
#define GTIMEOUT   0x80 /* Global timer reach 0 */
 
#define EXT68HIGH   0x40 /* Higher 8 bit connected externally */
 
#define INT68HIGH   0x20 /* Higher 8 bit connected internally */
 
#define CON5068   0x10 /* External 50/68 pin connected (low) */
 
#define CON68   0x08 /* Internal 68 pin connected (low) */
 
#define CON50   0x04 /* Internal 50 pin connected (low!) */
 
#define WIDESCSI   0x02 /* Wide SCSI card */
 
#define STATUS_LOAD_DEFAULT   0x01 /* */
 
#define TRM_S1040_GEN_NVRAM   0xD6 /* Serial NON-VOLATILE RAM port */
 
#define NVR_BITOUT   0x08 /* Serial data out */
 
#define NVR_BITIN   0x04 /* Serial data in */
 
#define NVR_CLOCK   0x02 /* Serial clock */
 
#define NVR_SELECT   0x01 /* Serial select */
 
#define TRM_S1040_GEN_EDATA   0xD7 /* Parallel EEPROM data port */
 
#define TRM_S1040_GEN_EADDRESS   0xD8 /* Parallel EEPROM address */
 
#define TRM_S1040_GEN_TIMER   0xDB /* Global timer */
 
#define NTC_DO_WIDE_NEGO   0x20 /* Wide negotiate */
 
#define NTC_DO_TAG_QUEUEING   0x10 /* Enable SCSI tag queuing */
 
#define NTC_DO_SEND_START   0x08 /* Send start command SPINUP */
 
#define NTC_DO_DISCONNECT   0x04 /* Enable SCSI disconnect */
 
#define NTC_DO_SYNC_NEGO   0x02 /* Sync negotiation */
 
#define NTC_DO_PARITY_CHK   0x01 /* (it should define at NAC) */
 
#define NAC_SCANLUN   0x20 /* Include LUN as BIOS device */
 
#define NAC_POWERON_SCSI_RESET   0x04 /* Power on reset enable */
 
#define NAC_GREATER_1G   0x02 /* > 1G support enable */
 
#define NAC_GT2DRIVES   0x01 /* Support more than 2 drives */
 

Macro Definition Documentation

#define ABORT_DEV   BIT1

Definition at line 141 of file dc395x.h.

#define ABORT_DEV_   BIT0

Definition at line 125 of file dc395x.h.

#define ABORTION   BIT1

Definition at line 129 of file dc395x.h.

#define ABORTXFER   0x04 /* Abort DMA transfer */

Definition at line 539 of file dc395x.h.

#define ACTIVE_NEG   0x02 /* Enable active negation */

Definition at line 440 of file dc395x.h.

#define ACTIVE_NEGPLUS   0x10 /* Enhance active negation */

Definition at line 437 of file dc395x.h.

#define ACTTAG_MASK   0x007F /* Active tags */

Definition at line 519 of file dc395x.h.

#define ALT_SYNC   0x08 /* Enable Fast-20 alternate synchronous */

Definition at line 343 of file dc395x.h.

#define ASPI_SUPPORT   BIT2

Definition at line 86 of file dc395x.h.

#define AUTO_REQSENSE   BIT0

Definition at line 142 of file dc395x.h.

#define AUTOTERM   0x04 /* Enable Auto SCSI terminator */

Definition at line 586 of file dc395x.h.

#define BIT0   0x00000001

Definition at line 75 of file dc395x.h.

#define BIT1   0x00000002

Definition at line 74 of file dc395x.h.

#define BIT10   0x00000400

Definition at line 65 of file dc395x.h.

#define BIT11   0x00000800

Definition at line 64 of file dc395x.h.

#define BIT12   0x00001000

Definition at line 63 of file dc395x.h.

#define BIT13   0x00002000

Definition at line 62 of file dc395x.h.

#define BIT14   0x00004000

Definition at line 61 of file dc395x.h.

#define BIT15   0x00008000

Definition at line 60 of file dc395x.h.

#define BIT16   0x00010000

Definition at line 59 of file dc395x.h.

#define BIT17   0x00020000

Definition at line 58 of file dc395x.h.

#define BIT18   0x00040000

Definition at line 57 of file dc395x.h.

#define BIT19   0x00080000

Definition at line 56 of file dc395x.h.

#define BIT2   0x00000004

Definition at line 73 of file dc395x.h.

#define BIT20   0x00100000

Definition at line 55 of file dc395x.h.

#define BIT21   0x00200000

Definition at line 54 of file dc395x.h.

#define BIT22   0x00400000

Definition at line 53 of file dc395x.h.

#define BIT23   0x00800000

Definition at line 52 of file dc395x.h.

#define BIT24   0x01000000

Definition at line 51 of file dc395x.h.

#define BIT25   0x02000000

Definition at line 50 of file dc395x.h.

#define BIT26   0x04000000

Definition at line 49 of file dc395x.h.

#define BIT27   0x08000000

Definition at line 48 of file dc395x.h.

#define BIT28   0x10000000

Definition at line 47 of file dc395x.h.

#define BIT29   0x20000000

Definition at line 46 of file dc395x.h.

#define BIT3   0x00000008

Definition at line 72 of file dc395x.h.

#define BIT30   0x40000000

Definition at line 45 of file dc395x.h.

#define BIT31   0x80000000

Definition at line 44 of file dc395x.h.

#define BIT4   0x00000010

Definition at line 71 of file dc395x.h.

#define BIT5   0x00000020

Definition at line 70 of file dc395x.h.

#define BIT6   0x00000040

Definition at line 69 of file dc395x.h.

#define BIT7   0x00000080

Definition at line 68 of file dc395x.h.

#define BIT8   0x00000100

Definition at line 67 of file dc395x.h.

#define BIT9   0x00000200

Definition at line 66 of file dc395x.h.

#define BLOCKRST   0x01 /* Disable SCSI reset1 */

Definition at line 434 of file dc395x.h.

#define CFG2_WIDEFIFO   0x02 /* */

Definition at line 443 of file dc395x.h.

#define CHECK_CONDITION_   0x02

Definition at line 207 of file dc395x.h.

#define CLRXFIFO   0x02 /* Clear DMA transfer FIFO */

Definition at line 540 of file dc395x.h.

#define COMMANDABORT   0x0040 /* SCSI command abort */

Definition at line 290 of file dc395x.h.

#define COMMANDPHASEDONE   0x2000 /* SCSI command phase done */

Definition at line 286 of file dc395x.h.

#define CON50   0x04 /* Internal 50 pin connected (low!) */

Definition at line 596 of file dc395x.h.

#define CON5068   0x10 /* External 50/68 pin connected (low) */

Definition at line 594 of file dc395x.h.

#define CON68   0x08 /* Internal 68 pin connected (low) */

Definition at line 595 of file dc395x.h.

#define CTRL_LED   0x80 /* Control onboard LED */

Definition at line 583 of file dc395x.h.

#define DASD_SUPPORT   BIT0

Definition at line 84 of file dc395x.h.

#define DATAIN   BIT6

Definition at line 137 of file dc395x.h.

#define DATAOUT   BIT7

Definition at line 136 of file dc395x.h.

#define DC395x_END_SCAN   2

Definition at line 29 of file dc395x.h.

#define DC395x_MAX_CAN_QUEUE   DC395x_MAX_SRB_CNT

Definition at line 28 of file dc395x.h.

#define DC395x_MAX_CMD_PER_LUN   DC395x_MAX_QTAGS

Definition at line 22 of file dc395x.h.

#define DC395x_MAX_CMD_QUEUE   32

Definition at line 18 of file dc395x.h.

#define DC395x_MAX_QTAGS   16

Definition at line 20 of file dc395x.h.

#define DC395x_MAX_RETRIES   3

Definition at line 31 of file dc395x.h.

#define DC395x_MAX_SCSI_ID   16

Definition at line 21 of file dc395x.h.

#define DC395x_MAX_SG_LISTENTRY   64 /* Must be equal or lower to previous */

Definition at line 24 of file dc395x.h.

#define DC395x_MAX_SG_TABLESIZE   64 /* HW limitation */

Definition at line 23 of file dc395x.h.

#define DC395x_MAX_SRB_CNT   63

Definition at line 26 of file dc395x.h.

#define DC395x_SEL_TIMEOUT   153 /* 250 ms selection timeout (@ 40 MHz) */

Definition at line 30 of file dc395x.h.

#define DIS_TERM   0x08 /* Disable onboard termination */

Definition at line 585 of file dc395x.h.

#define DISABLE_CE   0

Definition at line 266 of file dc395x.h.

#define DMA_AUTO_CLR_FIFO   0x1000 /* DISable DMA auto clear FIFO */

Definition at line 566 of file dc395x.h.

#define DMA_CFG_RES   0x2000 /* Always 1 */

Definition at line 565 of file dc395x.h.

#define DMA_ENHANCE   0x8000 /* Enable DMA enhance feature (SG?) */

Definition at line 563 of file dc395x.h.

#define DMA_FIFO_CTRL   0x0300 /* Control FIFO operation with DMA */

Definition at line 569 of file dc395x.h.

#define DMA_FIFO_HALF_HALF   0x0200 /* Keep half filled on both read/write */

Definition at line 570 of file dc395x.h.

#define DMA_MEM_MULTI_READ   0x0800 /* */

Definition at line 567 of file dc395x.h.

#define DMA_MEM_WRITE_INVAL   0x0400 /* Memory write and invalidate */

Definition at line 568 of file dc395x.h.

#define DMA_PCI_DUAL_ADDR   0x4000 /* */

Definition at line 564 of file dc395x.h.

#define DMACMD_DIR   0x01 /* 1 = read from SCSI write to Host */

Definition at line 528 of file dc395x.h.

#define DMACMD_SG   0x02 /* Enable HW S/G support */

Definition at line 527 of file dc395x.h.

#define DMARESETMODULE   0x10 /* Reset PCI/DMA module */

Definition at line 537 of file dc395x.h.

#define DMAXFERABORT   0x04 /* DMA transfer abort */

Definition at line 551 of file dc395x.h.

#define DMAXFERCOMP   0x02 /* Bus Master XFER Complete status */

Definition at line 552 of file dc395x.h.

#define DMAXFERERROR   0x08 /* DMA transfer error */

Definition at line 550 of file dc395x.h.

#define DO_CLRATN   0x0400 /* Clear ATN */

Definition at line 305 of file dc395x.h.

#define DO_CLRFIFO   0x0004 /* Clear SCSI transfer FIFO */

Definition at line 310 of file dc395x.h.

#define DO_CMDABORT   0x0100 /* Abort SCSI command */

Definition at line 307 of file dc395x.h.

#define DO_DATALATCH   0x0002 /* Enable SCSI bus data input (latched) */

Definition at line 311 of file dc395x.h.

#define DO_HWRESELECT   0x0001 /* Enable hardware reselection */

Definition at line 313 of file dc395x.h.

#define DO_RSTMODULE   0x0010 /* Reset SCSI chip */

Definition at line 308 of file dc395x.h.

#define DO_RSTSCSI   0x0008 /* Reset SCSI bus */

Definition at line 309 of file dc395x.h.

#define DO_SETATN   0x0200 /* Set ATN */

Definition at line 306 of file dc395x.h.

#define EEPROM_READ   0x80

Definition at line 267 of file dc395x.h.

#define EN_ATN_STOP   BIT6

Definition at line 179 of file dc395x.h.

#define EN_BUSSERVICE   0x02 /* Enable bus service interrupt */

Definition at line 427 of file dc395x.h.

#define EN_CMDDONE   0x01 /* Enable SCSI command done interrupt */

Definition at line 428 of file dc395x.h.

#define EN_DISCONNECT   0x10 /* Enable bus disconnected interrupt */

Definition at line 424 of file dc395x.h.

#define EN_DMAXFERABORT   0x04 /* DMA transfer abort */

Definition at line 558 of file dc395x.h.

#define EN_DMAXFERCOMP   0x02 /* Bus Master XFER Complete status */

Definition at line 559 of file dc395x.h.

#define EN_DMAXFERERROR   0x08 /* DMA transfer error */

Definition at line 557 of file dc395x.h.

#define EN_EEPROM   0x10 /* Enable EEPROM programming */

Definition at line 584 of file dc395x.h.

#define EN_FORCEDMACOMP   0x10 /* Force DMA transfer complete */

Definition at line 556 of file dc395x.h.

#define EN_RESELECTED   0x08 /* Enable reselected interrupt */

Definition at line 425 of file dc395x.h.

#define EN_SCAM   0x80 /* Enable SCAM selection interrupt */

Definition at line 421 of file dc395x.h.

#define EN_SCSIINTR   0x01 /* Enable SCSI complete interrupt */

Definition at line 560 of file dc395x.h.

#define EN_SCSIRESET   0x04 /* Enable SCSI reset detected interrupt */

Definition at line 426 of file dc395x.h.

#define EN_SELECT   0x40 /* Enable selection interrupt */

Definition at line 422 of file dc395x.h.

#define EN_SELTIMEOUT   0x20 /* Enable selection timeout interrupt */

Definition at line 423 of file dc395x.h.

#define EN_TAG_QUEUEING   BIT5

Definition at line 178 of file dc395x.h.

#define ENABLE_CE   1

Definition at line 265 of file dc395x.h.

#define ENABLE_TIMER   BIT4

Definition at line 139 of file dc395x.h.

#define EXT68HIGH   0x40 /* Higher 8 bit connected externally */

Definition at line 592 of file dc395x.h.

#define FAST_FILTER   0x04 /* ? */

Definition at line 439 of file dc395x.h.

#define FILTER_DISABLE   0x08 /* Disable SCSI data filter */

Definition at line 438 of file dc395x.h.

#define FORCEDMACOMP   0x10 /* Force DMA transfer complete */

Definition at line 549 of file dc395x.h.

#define FORMATING_MEDIA   BIT2

Definition at line 80 of file dc395x.h.

#define GLOBALINT   0x20 /* DMA_INTEN bit 0-4 set */

Definition at line 548 of file dc395x.h.

#define GTIMEOUT   0x80 /* Global timer reach 0 */

Definition at line 591 of file dc395x.h.

#define H_ABORT   0x0FF

Definition at line 155 of file dc395x.h.

#define H_BAD_CCB_OR_SG   0x1A

Definition at line 154 of file dc395x.h.

#define H_BAD_TARGET_DIR   0x18

Definition at line 152 of file dc395x.h.

#define H_DUPLICATE_CCB   0x19

Definition at line 153 of file dc395x.h.

#define H_INVALID_CCB_OP   0x16

Definition at line 150 of file dc395x.h.

#define H_LINK_CCB_BAD   0x17

Definition at line 151 of file dc395x.h.

#define H_OVER_UNDER_RUN   0x12

Definition at line 147 of file dc395x.h.

#define H_SEL_TIMEOUT   0x11

Definition at line 146 of file dc395x.h.

#define H_STATUS_GOOD   0

Definition at line 145 of file dc395x.h.

#define H_TARGET_PHASE_F   0x14

Definition at line 149 of file dc395x.h.

#define H_UNEXP_BUS_FREE   0x13

Definition at line 148 of file dc395x.h.

#define HCC_AUTOTERM   0x04

Definition at line 115 of file dc395x.h.

#define HCC_LOW8TERM   0x02

Definition at line 116 of file dc395x.h.

#define HCC_PARITY   0x08

Definition at line 114 of file dc395x.h.

#define HCC_SCSI_RESET   0x10

Definition at line 113 of file dc395x.h.

#define HCC_UP8TERM   0x01

Definition at line 117 of file dc395x.h.

#define HCC_WIDE_CARD   0x20

Definition at line 112 of file dc395x.h.

#define INITIATOR   0x20 /* Enable initiator mode */

Definition at line 432 of file dc395x.h.

#define INT68HIGH   0x20 /* Higher 8 bit connected internally */

Definition at line 593 of file dc395x.h.

#define INT_BUSSERVICE   0x02 /* Bus service interrupt */

Definition at line 325 of file dc395x.h.

#define INT_CMDDONE   0x01 /* SCSI command done interrupt */

Definition at line 326 of file dc395x.h.

#define INT_DISCONNECT   0x10 /* Bus disconnected interrupt */

Definition at line 322 of file dc395x.h.

#define INT_RESELECTED   0x08 /* Reselected interrupt */

Definition at line 323 of file dc395x.h.

#define INT_SCAM   0x80 /* SCAM selection interrupt */

Definition at line 319 of file dc395x.h.

#define INT_SCSIRESET   0x04 /* SCSI reset detected interrupt */

Definition at line 324 of file dc395x.h.

#define INT_SELECT   0x40 /* Selection interrupt */

Definition at line 320 of file dc395x.h.

#define INT_SELTIMEOUT   0x20 /* Selection timeout interrupt */

Definition at line 321 of file dc395x.h.

#define LOW8TERM   0x02 /* Enable Lower 8 bit SCSI terminator */

Definition at line 587 of file dc395x.h.

#define LVDS_SYNC   0x20 /* Enable LVDS synchronous */

Definition at line 341 of file dc395x.h.

#define MAXTAG_MASK   0x7F00 /* Maximum tags (127) */

Definition at line 517 of file dc395x.h.

#define MSG_ABORT   0x06

Definition at line 190 of file dc395x.h.

#define MSG_ABORT_TAG   0x0D

Definition at line 197 of file dc395x.h.

#define MSG_BUS_RESET   0x0C

Definition at line 196 of file dc395x.h.

#define MSG_COMPLETE   0x00

Definition at line 184 of file dc395x.h.

#define MSG_DISCONNECT   0x04

Definition at line 188 of file dc395x.h.

#define MSG_EXTENDED   0x01

Definition at line 185 of file dc395x.h.

#define MSG_HEAD_QTAG   0x21

Definition at line 199 of file dc395x.h.

#define MSG_HOST_ID   0xC0

Definition at line 203 of file dc395x.h.

#define MSG_IDENTIFY   0x80

Definition at line 202 of file dc395x.h.

#define MSG_IGNOREWIDE   0x23

Definition at line 201 of file dc395x.h.

#define MSG_INITIATOR_ERROR   0x05

Definition at line 189 of file dc395x.h.

#define MSG_LINK_CMD_COMPL   0x0A

Definition at line 194 of file dc395x.h.

#define MSG_LINK_CMD_COMPL_FLG   0x0B

Definition at line 195 of file dc395x.h.

#define MSG_MASK   0xFF00

Definition at line 214 of file dc395x.h.

#define MSG_NOP   0x08

Definition at line 192 of file dc395x.h.

#define MSG_ORDER_QTAG   0x22

Definition at line 200 of file dc395x.h.

#define MSG_PARITY_ERROR   0x09

Definition at line 193 of file dc395x.h.

#define MSG_REJECT_   0x07

Definition at line 191 of file dc395x.h.

#define MSG_RESTORE_PTR   0x03

Definition at line 187 of file dc395x.h.

#define MSG_SAVE_PTR   0x02

Definition at line 186 of file dc395x.h.

#define MSG_SIMPLE_QTAG   0x20

Definition at line 198 of file dc395x.h.

#define NAC_GREATER_1G   0x02 /* > 1G support enable */

Definition at line 644 of file dc395x.h.

#define NAC_GT2DRIVES   0x01 /* Support more than 2 drives */

Definition at line 645 of file dc395x.h.

#define NAC_POWERON_SCSI_RESET   0x04 /* Power on reset enable */

Definition at line 643 of file dc395x.h.

#define NAC_SCANLUN   0x20 /* Include LUN as BIOS device */

Definition at line 642 of file dc395x.h.

#define NON_TAG_BUSY   0x0080 /* Non tag command active */

Definition at line 518 of file dc395x.h.

#define NORM_REC_LVL   0

Definition at line 37 of file dc395x.h.

#define NTC_DO_DISCONNECT   0x04 /* Enable SCSI disconnect */

Definition at line 618 of file dc395x.h.

#define NTC_DO_PARITY_CHK   0x01 /* (it should define at NAC) */

Definition at line 620 of file dc395x.h.

#define NTC_DO_SEND_START   0x08 /* Send start command SPINUP */

Definition at line 617 of file dc395x.h.

#define NTC_DO_SYNC_NEGO   0x02 /* Sync negotiation */

Definition at line 619 of file dc395x.h.

#define NTC_DO_TAG_QUEUEING   0x10 /* Enable SCSI tag queuing */

Definition at line 616 of file dc395x.h.

#define NTC_DO_WIDE_NEGO   0x20 /* Wide negotiate */

Definition at line 615 of file dc395x.h.

#define NVR_BITIN   0x04 /* Serial data in */

Definition at line 602 of file dc395x.h.

#define NVR_BITOUT   0x08 /* Serial data out */

Definition at line 601 of file dc395x.h.

#define NVR_CLOCK   0x02 /* Serial clock */

Definition at line 603 of file dc395x.h.

#define NVR_SELECT   0x01 /* Serial select */

Definition at line 604 of file dc395x.h.

#define OVER_RUN   BIT2

Definition at line 130 of file dc395x.h.

#define PARITY_ERROR   BIT4

Definition at line 132 of file dc395x.h.

#define PARITYCHECK   0x10 /* Enable parity check */

Definition at line 433 of file dc395x.h.

#define PARITYERROR   0x0008 /* SCSI parity error */

Definition at line 293 of file dc395x.h.

#define PH_BUS_FREE   0x05 /* Invalid phase used as bus free */

Definition at line 300 of file dc395x.h.

#define PH_COMMAND   0x02 /* Command phase */

Definition at line 298 of file dc395x.h.

#define PH_DATA_IN   0x01 /* Data in phase */

Definition at line 297 of file dc395x.h.

#define PH_DATA_OUT   0x00 /* Data out phase */

Definition at line 296 of file dc395x.h.

#define PH_MSG_IN   0x07 /* Message in phase */

Definition at line 302 of file dc395x.h.

#define PH_MSG_OUT   0x06 /* Message out phase */

Definition at line 301 of file dc395x.h.

#define PH_STATUS   0x03 /* Status phase */

Definition at line 299 of file dc395x.h.

#define PHASELATCH   0x40 /* Enable phase latch */

Definition at line 431 of file dc395x.h.

#define PHASEMASK   0x0007 /* Phase MSG/CD/IO */

Definition at line 295 of file dc395x.h.

#define PHASEMISMATCH   0x0010 /* SCSI phase mismatch */

Definition at line 292 of file dc395x.h.

#define RESERVE_CONFLICT   0x18

Definition at line 210 of file dc395x.h.

#define RESET_DETECT   BIT1

Definition at line 121 of file dc395x.h.

#define RESET_DEV   BIT0

Definition at line 120 of file dc395x.h.

#define RESET_DEV0   BIT2

Definition at line 140 of file dc395x.h.

#define RESET_DONE   BIT2

Definition at line 122 of file dc395x.h.

#define RESIDUAL_VALID   BIT5

Definition at line 138 of file dc395x.h.

#define RETURN_MASK   0xFF0000

Definition at line 215 of file dc395x.h.

#define SCMD_COMP   0x12 /* Command complete */

Definition at line 446 of file dc395x.h.

#define SCMD_DMA_IN   0xC3 /* SCSI DMA transfer in */

Definition at line 453 of file dc395x.h.

#define SCMD_DMA_OUT   0xC1 /* SCSI DMA transfer out */

Definition at line 451 of file dc395x.h.

#define SCMD_FIFO_IN   0xC2 /* SCSI FIFO transfer in */

Definition at line 452 of file dc395x.h.

#define SCMD_FIFO_OUT   0xC0 /* SCSI FIFO transfer out */

Definition at line 450 of file dc395x.h.

#define SCMD_MSGACCEPT   0xD8 /* Message accept */

Definition at line 454 of file dc395x.h.

#define SCMD_SEL_ATN   0x60 /* Selection with ATN */

Definition at line 447 of file dc395x.h.

#define SCMD_SEL_ATN3   0x64 /* Selection with ATN3 */

Definition at line 448 of file dc395x.h.

#define SCMD_SEL_ATNSTOP   0xB8 /* Selection with ATN and Stop */

Definition at line 449 of file dc395x.h.

#define SCSI_DEVTYPE   0x1F /* Peripheral Device Type */

Definition at line 238 of file dc395x.h.

#define SCSI_INQ_CMDQUEUE   0x02 /* device supports command queueing */

Definition at line 262 of file dc395x.h.

#define SCSI_INQ_LINKED   0x08 /* device supports linked commands */

Definition at line 261 of file dc395x.h.

#define SCSI_INQ_RELADR   0x80 /* device supports relative addressing */

Definition at line 257 of file dc395x.h.

#define SCSI_INQ_SFTRE   0x01 /* device supports soft resets */

Definition at line 263 of file dc395x.h.

#define SCSI_INQ_SYNC   0x10 /* device supports synchronous xfer */

Definition at line 260 of file dc395x.h.

#define SCSI_INQ_WBUS16   0x20 /* device supports 16 bit data xfers */

Definition at line 259 of file dc395x.h.

#define SCSI_INQ_WBUS32   0x40 /* device supports 32 bit data xfers */

Definition at line 258 of file dc395x.h.

#define SCSI_PERIPHQUAL   0xE0 /* Peripheral Qualifier */

Definition at line 239 of file dc395x.h.

#define SCSI_REMOVABLE_MEDIA   0x80 /* Removable Media bit (1=removable) */

Definition at line 241 of file dc395x.h.

#define SCSI_STAT_BUS_RST_DETECT   0xFE /* Scsi Bus Reset detected */

Definition at line 168 of file dc395x.h.

#define SCSI_STAT_BUSY   0x08 /* Target busy status */

Definition at line 161 of file dc395x.h.

#define SCSI_STAT_CHECKCOND   0x02 /* SCSI Check Condition */

Definition at line 159 of file dc395x.h.

#define SCSI_STAT_CMDTERM   0x22 /* Command Terminated */

Definition at line 165 of file dc395x.h.

#define SCSI_STAT_CONDMET   0x04 /* Condition Met */

Definition at line 160 of file dc395x.h.

#define SCSI_STAT_GOOD   0x0 /* Good status */

Definition at line 158 of file dc395x.h.

#define SCSI_STAT_INTER   0x10 /* Intermediate status */

Definition at line 162 of file dc395x.h.

#define SCSI_STAT_INTERCONDMET   0x14 /* Intermediate condition met */

Definition at line 163 of file dc395x.h.

#define SCSI_STAT_QUEUEFULL   0x28 /* Queue Full */

Definition at line 166 of file dc395x.h.

#define SCSI_STAT_RESCONFLICT   0x18 /* Reservation conflict */

Definition at line 164 of file dc395x.h.

#define SCSI_STAT_SEL_TIMEOUT   0xFF /* Selection Time out */

Definition at line 169 of file dc395x.h.

#define SCSI_STAT_UNEXP_BUS_F   0xFD /* Unexpect Bus Free */

Definition at line 167 of file dc395x.h.

#define SCSI_SUPPORT   BIT1

Definition at line 85 of file dc395x.h.

#define SCSIBUSY   0x40 /* SCSI busy */

Definition at line 547 of file dc395x.h.

#define SCSICOMP   0x01 /* SCSI complete interrupt */

Definition at line 553 of file dc395x.h.

#define SCSIINTERRUPT   0x0080 /* SCSI interrupt pending */

Definition at line 289 of file dc395x.h.

#define SCSIXFERCNT_2_ZERO   0x0100 /* SCSI SCSI transfer count to zero */

Definition at line 288 of file dc395x.h.

#define SCSIXFERDONE   0x0800 /* SCSI SCSI transfer done */

Definition at line 287 of file dc395x.h.

#define SEQUENCERACTIVE   0x0020 /* SCSI sequencer active */

Definition at line 291 of file dc395x.h.

#define SRB_ABORT_SENT   0x1000

Definition at line 102 of file dc395x.h.

#define SRB_COMMAND   0x0020

Definition at line 95 of file dc395x.h.

#define SRB_COMPLETED   0x0800

Definition at line 101 of file dc395x.h.

#define SRB_DATA_XFER   0x0100

Definition at line 98 of file dc395x.h.

#define SRB_DISCONNECT   0x0080

Definition at line 97 of file dc395x.h.

#define SRB_DO_SYNC_NEGO   0x2000

Definition at line 103 of file dc395x.h.

#define SRB_DO_WIDE_NEGO   0x4000

Definition at line 104 of file dc395x.h.

#define SRB_ERROR   BIT5

Definition at line 133 of file dc395x.h.

#define SRB_EXTEND_MSGIN   0x0010

Definition at line 94 of file dc395x.h.

#define SRB_FREE   0x0000

Definition at line 89 of file dc395x.h.

#define SRB_MSGIN   0x0008

Definition at line 93 of file dc395x.h.

#define SRB_MSGOUT   0x0004 /* arbitration+msg_out 1st byte */

Definition at line 92 of file dc395x.h.

#define SRB_OK   BIT0

Definition at line 128 of file dc395x.h.

#define SRB_READY   0x0002

Definition at line 91 of file dc395x.h.

#define SRB_START_   0x0040 /* arbitration+msg_out+command_out */

Definition at line 96 of file dc395x.h.

#define SRB_STATUS   0x0400

Definition at line 100 of file dc395x.h.

#define SRB_UNEXPECT_RESEL   0x8000

Definition at line 105 of file dc395x.h.

#define SRB_WAIT   0x0001

Definition at line 90 of file dc395x.h.

#define SRB_XFERPAD   0x0200

Definition at line 99 of file dc395x.h.

#define STARTDMAXFER   0x01 /* Start DMA transfer */

Definition at line 541 of file dc395x.h.

#define STATUS_BUSY   0x08

Definition at line 208 of file dc395x.h.

#define STATUS_GOOD   0x00

Definition at line 206 of file dc395x.h.

#define STATUS_INTERMEDIATE   0x10

Definition at line 209 of file dc395x.h.

#define STATUS_LOAD_DEFAULT   0x01 /* */

Definition at line 598 of file dc395x.h.

#define STATUS_MASK_   0xFF

Definition at line 213 of file dc395x.h.

#define STOPDMAXFER   0x08 /* Stop DMA transfer */

Definition at line 538 of file dc395x.h.

#define SYNC_NEGO_DONE   BIT1

Definition at line 174 of file dc395x.h.

#define SYNC_NEGO_ENABLE   BIT0

Definition at line 173 of file dc395x.h.

#define SYNC_NEGO_OFFSET   15

Definition at line 181 of file dc395x.h.

#define SYNC_WIDE_TAG_ATNT_DISABLE   0

Definition at line 172 of file dc395x.h.

#define TCR0_DISCONNECT_EN   0x0020 /* Disconnection enable */

Definition at line 513 of file dc395x.h.

#define TCR0_DO_SYNC_NEGO   0x0040 /* Do sync NEGO */

Definition at line 512 of file dc395x.h.

#define TCR0_DO_WIDE_NEGO   0x0080 /* Do wide NEGO */

Definition at line 511 of file dc395x.h.

#define TCR0_ENABLE_ALT   0x0800 /* Enable alternate synchronous */

Definition at line 508 of file dc395x.h.

#define TCR0_ENABLE_LVDS   0x2000 /* Enable LVDS synchronous */

Definition at line 506 of file dc395x.h.

#define TCR0_ENABLE_WIDE   0x1000 /* Enable WIDE synchronous */

Definition at line 507 of file dc395x.h.

#define TCR0_OFFSET_MASK   0x001F /* Offset number */

Definition at line 514 of file dc395x.h.

#define TCR0_PERIOD_MASK   0x0700 /* Transfer rate */

Definition at line 509 of file dc395x.h.

#define TCR0_SYNC_NEGO_DONE   0x4000 /* Synchronous nego done */

Definition at line 505 of file dc395x.h.

#define TCR0_WIDE_NEGO_DONE   0x8000 /* Wide nego done */

Definition at line 504 of file dc395x.h.

#define TRM_S1040_COMMAND   0x04 /* PCI command register */

Definition at line 275 of file dc395x.h.

#define TRM_S1040_DMA_COMMAND   0xA0 /* DMA Command (R/W) */

Definition at line 526 of file dc395x.h.

#define TRM_S1040_DMA_CONFIG   0xA6 /* DMA Configuration (R/W) */

Definition at line 562 of file dc395x.h.

#define TRM_S1040_DMA_CONTROL   0xA1 /* DMA Control (W) */

Definition at line 536 of file dc395x.h.

#define TRM_S1040_DMA_CXCNT   0xAC /* DMA Current Transfer Counter (R) */

Definition at line 573 of file dc395x.h.

#define TRM_S1040_DMA_FIFOCNT   0xA1 /* DMA FIFO Counter (R) */

Definition at line 534 of file dc395x.h.

#define TRM_S1040_DMA_FIFOSTAT   0xA2 /* DMA FIFO Status (R) */

Definition at line 543 of file dc395x.h.

#define TRM_S1040_DMA_INTEN   0xA4 /* DMA Interrupt Enable (R/W) */

Definition at line 555 of file dc395x.h.

#define TRM_S1040_DMA_STATUS   0xA3 /* DMA Interrupt Status (R/W) */

Definition at line 545 of file dc395x.h.

#define TRM_S1040_DMA_XCNT   0xA8 /* DMA Transfer Counter (R/W), 24bits */

Definition at line 572 of file dc395x.h.

#define TRM_S1040_DMA_XHIGHADDR   0xB4 /* DMA Transfer Physical High Address */

Definition at line 575 of file dc395x.h.

#define TRM_S1040_DMA_XLOWADDR   0xB0 /* DMA Transfer Physical Low Address */

Definition at line 574 of file dc395x.h.

#define TRM_S1040_GEN_CONTROL   0xD4 /* Global Control */

Definition at line 582 of file dc395x.h.

#define TRM_S1040_GEN_EADDRESS   0xD8 /* Parallel EEPROM address */

Definition at line 607 of file dc395x.h.

#define TRM_S1040_GEN_EDATA   0xD7 /* Parallel EEPROM data port */

Definition at line 606 of file dc395x.h.

#define TRM_S1040_GEN_NVRAM   0xD6 /* Serial NON-VOLATILE RAM port */

Definition at line 600 of file dc395x.h.

#define TRM_S1040_GEN_STATUS   0xD5 /* Global Status */

Definition at line 590 of file dc395x.h.

#define TRM_S1040_GEN_TIMER   0xDB /* Global timer */

Definition at line 608 of file dc395x.h.

#define TRM_S1040_ID   0x00 /* Vendor and Device ID */

Definition at line 274 of file dc395x.h.

#define TRM_S1040_INTLINE   0x3C /* Interrupt line */

Definition at line 278 of file dc395x.h.

#define TRM_S1040_IOBASE   0x10 /* I/O Space base address */

Definition at line 276 of file dc395x.h.

#define TRM_S1040_ROMBASE   0x30 /* Expansion ROM Base Address */

Definition at line 277 of file dc395x.h.

#define TRM_S1040_SCSI_COMMAND   0x90 /* SCSI Command (R/W) */

Definition at line 445 of file dc395x.h.

#define TRM_S1040_SCSI_CONFIG0   0x8D /* SCSI Configuration 0 (R/W) */

Definition at line 430 of file dc395x.h.

#define TRM_S1040_SCSI_CONFIG1   0x8E /* SCSI Configuration 1 (R/W) */

Definition at line 436 of file dc395x.h.

#define TRM_S1040_SCSI_CONFIG2   0x8F /* SCSI Configuration 2 (R/W) */

Definition at line 442 of file dc395x.h.

#define TRM_S1040_SCSI_CONTROL   0x80 /* SCSI Control (W) */

Definition at line 304 of file dc395x.h.

#define TRM_S1040_SCSI_COUNTER   0x88 /* SCSI Transfer Counter 24bits(R/W) */

Definition at line 418 of file dc395x.h.

#define TRM_S1040_SCSI_FIFO   0x98 /* SCSI FIFO (R/W) */

Definition at line 501 of file dc395x.h.

#define TRM_S1040_SCSI_FIFOCNT   0x82 /* SCSI FIFO Counter 5bits(R) */

Definition at line 315 of file dc395x.h.

#define TRM_S1040_SCSI_HOSTID   0x87 /* SCSI Host ID (W) */

Definition at line 417 of file dc395x.h.

#define TRM_S1040_SCSI_IDMSG   0x87 /* SCSI Identify Message (R) */

Definition at line 416 of file dc395x.h.

#define TRM_S1040_SCSI_INTEN   0x8C /* SCSI Interrupt Enable (R/W) */

Definition at line 420 of file dc395x.h.

#define TRM_S1040_SCSI_INTSTATUS   0x84 /* SCSI Interrupt Status (R) */

Definition at line 318 of file dc395x.h.

#define TRM_S1040_SCSI_OFFSET   0x84 /* SCSI Offset Count (W) */

Definition at line 328 of file dc395x.h.

#define TRM_S1040_SCSI_SIGNAL   0x83 /* SCSI low level signal (R/W) */

Definition at line 316 of file dc395x.h.

#define TRM_S1040_SCSI_STATUS   0x80 /* SCSI Status (R) */

Definition at line 285 of file dc395x.h.

#define TRM_S1040_SCSI_SYNC   0x85 /* SCSI Synchronous Control (R/W) */

Definition at line 340 of file dc395x.h.

#define TRM_S1040_SCSI_TARGETID   0x86 /* SCSI Target ID (R/W) */

Definition at line 415 of file dc395x.h.

#define TRM_S1040_SCSI_TCR0   0x9C /* SCSI Target Control 0 (R/W) */

Definition at line 503 of file dc395x.h.

#define TRM_S1040_SCSI_TCR1   0x9E /* SCSI Target Control 1 (R/W) */

Definition at line 516 of file dc395x.h.

#define TRM_S1040_SCSI_TIMEOUT   0x91 /* SCSI Time Out Value (R/W) */

Definition at line 500 of file dc395x.h.

#define TYPE_COMM   0x09 /* Communications device */

Definition at line 249 of file dc395x.h.

#define TYPE_NODEV   SCSI_DEVTYPE /* Unknown or no device type */

Definition at line 244 of file dc395x.h.

#define TYPE_PRINTER   0x02 /* Printer device */

Definition at line 246 of file dc395x.h.

#define UNDER_RUN   BIT3

Definition at line 131 of file dc395x.h.

#define UNIT_ALLOCATED   BIT0

Definition at line 78 of file dc395x.h.

#define UNIT_INFO_CHANGED   BIT1

Definition at line 79 of file dc395x.h.

#define UNIT_RETRY   BIT3

Definition at line 81 of file dc395x.h.

#define UP8TERM   0x01 /* Enable Upper 8 bit SCSI terminator */

Definition at line 588 of file dc395x.h.

#define WIDE_NEGO_DONE   BIT3

Definition at line 176 of file dc395x.h.

#define WIDE_NEGO_ENABLE   BIT2

Definition at line 175 of file dc395x.h.

#define WIDE_NEGO_STATE   BIT4

Definition at line 177 of file dc395x.h.

#define WIDE_SYNC   0x10 /* Enable WIDE synchronous */

Definition at line 342 of file dc395x.h.

#define WIDESCSI   0x02 /* Wide SCSI card */

Definition at line 597 of file dc395x.h.

#define XFERDATAIN   0x0101 /* Transfer data in w/o SG */

Definition at line 531 of file dc395x.h.

#define XFERDATAIN_SG   0x0103 /* Transfer data in w/ SG */

Definition at line 529 of file dc395x.h.

#define XFERDATAOUT   0x0100 /* Transfer data out w/o SG */

Definition at line 532 of file dc395x.h.

#define XFERDATAOUT_SG   0x0102 /* Transfer data out w/ SG */

Definition at line 530 of file dc395x.h.

#define XFERPENDING   0x80 /* Transfer pending */

Definition at line 546 of file dc395x.h.