Data Structures
struct	reg_ddr2_rw_cfg

struct	reg_ddr2_rw_timing

struct	reg_ddr2_rw_latency

struct	reg_ddr2_rw_phy_cfg

struct	reg_ddr2_rw_phy_ctrl

struct	reg_ddr2_rw_ctrl

struct	reg_ddr2_rw_pwr_down

struct	reg_ddr2_r_stat

struct	reg_ddr2_rw_imp_ctrl

struct	reg_ddr2_rw_dll_ctrl

struct	reg_ddr2_rw_dqs_dll_ctrl

Macros
#define	REG_RD(scope, inst, reg)

#define	REG_WR(scope, inst, reg, val)

#define	REG_RD_VECT(scope, inst, reg, index)

#define	REG_WR_VECT(scope, inst, reg, index, val)

#define	REG_RD_INT(scope, inst, reg) REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )

#define	REG_WR_INT(scope, inst, reg, val) REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

#define	REG_RD_INT_VECT(scope, inst, reg, index)

#define	REG_WR_INT_VECT(scope, inst, reg, index, val)

#define	REG_TYPE_CONV(type, orgtype, val) ( { union { orgtype o; type n; } r; r.o = val; r.n; } )

#define	reg_page_size 8192

#define	REG_ADDR(scope, inst, reg) ( (inst) + REG_RD_ADDR_##scope##_##reg )

#define	REG_ADDR_VECT(scope, inst, reg, index)

#define	REG_RD_ADDR_ddr2_rw_cfg 0

#define	REG_WR_ADDR_ddr2_rw_cfg 0

#define	REG_RD_ADDR_ddr2_rw_timing 4

#define	REG_WR_ADDR_ddr2_rw_timing 4

#define	REG_RD_ADDR_ddr2_rw_latency 8

#define	REG_WR_ADDR_ddr2_rw_latency 8

#define	REG_RD_ADDR_ddr2_rw_phy_cfg 12

#define	REG_WR_ADDR_ddr2_rw_phy_cfg 12

#define	REG_RD_ADDR_ddr2_rw_phy_ctrl 16

#define	REG_WR_ADDR_ddr2_rw_phy_ctrl 16

#define	REG_RD_ADDR_ddr2_rw_ctrl 20

#define	REG_WR_ADDR_ddr2_rw_ctrl 20

#define	REG_RD_ADDR_ddr2_rw_pwr_down 24

#define	REG_WR_ADDR_ddr2_rw_pwr_down 24

#define	REG_RD_ADDR_ddr2_r_stat 28

#define	REG_RD_ADDR_ddr2_rw_imp_ctrl 32

#define	REG_WR_ADDR_ddr2_rw_imp_ctrl 32

#define	STRIDE_ddr2_rw_dll_ctrl 4

#define	REG_RD_ADDR_ddr2_rw_dll_ctrl 36

#define	REG_WR_ADDR_ddr2_rw_dll_ctrl 36

#define	STRIDE_ddr2_rw_dqs_dll_ctrl 4

#define	REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52

#define	REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52

Enumerations
enum	{ regk_ddr2_al0 = 0x00000000, regk_ddr2_al1 = 0x00000008, regk_ddr2_al2 = 0x00000010, regk_ddr2_al3 = 0x00000018, regk_ddr2_al4 = 0x00000020, regk_ddr2_auto = 0x00000003, regk_ddr2_bank4 = 0x00000000, regk_ddr2_bank8 = 0x00000001, regk_ddr2_bl4 = 0x00000002, regk_ddr2_bl8 = 0x00000003, regk_ddr2_bt_il = 0x00000008, regk_ddr2_bt_seq = 0x00000000, regk_ddr2_bw16 = 0x00000001, regk_ddr2_bw32 = 0x00000000, regk_ddr2_cas2 = 0x00000020, regk_ddr2_cas3 = 0x00000030, regk_ddr2_cas4 = 0x00000040, regk_ddr2_cas5 = 0x00000050, regk_ddr2_deselect = 0x000000c0, regk_ddr2_dic_weak = 0x00000002, regk_ddr2_direct = 0x00000001, regk_ddr2_dis = 0x00000000, regk_ddr2_dll_dis = 0x00000001, regk_ddr2_dll_en = 0x00000000, regk_ddr2_dll_rst = 0x00000100, regk_ddr2_emrs = 0x00000081, regk_ddr2_emrs2 = 0x00000082, regk_ddr2_emrs3 = 0x00000083, regk_ddr2_full = 0x00000001, regk_ddr2_hi_ref_rate = 0x00000080, regk_ddr2_mrs = 0x00000080, regk_ddr2_no = 0x00000000, regk_ddr2_nop = 0x000000b8, regk_ddr2_ocd_adj = 0x00000200, regk_ddr2_ocd_default = 0x00000380, regk_ddr2_ocd_drive0 = 0x00000100, regk_ddr2_ocd_drive1 = 0x00000080, regk_ddr2_ocd_exit = 0x00000000, regk_ddr2_odt_dis = 0x00000000, regk_ddr2_offs = 0x00000000, regk_ddr2_pre = 0x00000090, regk_ddr2_pre_all = 0x00000400, regk_ddr2_pwr_down_fast = 0x00000000, regk_ddr2_pwr_down_slow = 0x00001000, regk_ddr2_ref = 0x00000088, regk_ddr2_rtt150 = 0x00000040, regk_ddr2_rtt50 = 0x00000044, regk_ddr2_rtt75 = 0x00000004, regk_ddr2_rw_cfg_default = 0x00186000, regk_ddr2_rw_dll_ctrl_default = 0x00000000, regk_ddr2_rw_dll_ctrl_size = 0x00000004, regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000, regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004, regk_ddr2_rw_latency_default = 0x00000000, regk_ddr2_rw_phy_cfg_default = 0x00000000, regk_ddr2_rw_pwr_down_default = 0x00000000, regk_ddr2_rw_timing_default = 0x00000000, regk_ddr2_s1Gb = 0x0000001a, regk_ddr2_s256Mb = 0x0000000f, regk_ddr2_s2Gb = 0x00000027, regk_ddr2_s4Gb = 0x00000042, regk_ddr2_s512Mb = 0x00000015, regk_ddr2_temp0_85 = 0x00000618, regk_ddr2_temp85_95 = 0x0000030c, regk_ddr2_term150 = 0x00000002, regk_ddr2_term50 = 0x00000003, regk_ddr2_term75 = 0x00000001, regk_ddr2_test = 0x00000080, regk_ddr2_weak = 0x00000000, regk_ddr2_wr2 = 0x00000200, regk_ddr2_wr3 = 0x00000400, regk_ddr2_yes = 0x00000001 }

Macro Definition Documentation

#define REG_ADDR	(	scope,
		inst,
		reg
	)	( (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 72 of file ddr2_defs.h.

#define REG_ADDR_VECT	(	scope,
		inst,
		reg,
		index
	)

Value:

( (inst) + REG_RD_ADDR_##scope##_##reg + \

(index) * STRIDE_##scope##_##reg )

Definition at line 77 of file ddr2_defs.h.

#define reg_page_size 8192

Definition at line 68 of file ddr2_defs.h.

#define REG_RD	(	scope,
		inst,
		reg
	)

Value:

REG_READ( reg_##scope##_##reg, \

(inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 15 of file ddr2_defs.h.

#define REG_RD_ADDR_ddr2_r_stat 28

Definition at line 172 of file ddr2_defs.h.

#define REG_RD_ADDR_ddr2_rw_cfg 0

Definition at line 99 of file ddr2_defs.h.

#define REG_RD_ADDR_ddr2_rw_ctrl 20

Definition at line 150 of file ddr2_defs.h.

#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36

Definition at line 190 of file ddr2_defs.h.

#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52

Definition at line 202 of file ddr2_defs.h.

#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32

Definition at line 180 of file ddr2_defs.h.

#define REG_RD_ADDR_ddr2_rw_latency 8

Definition at line 123 of file ddr2_defs.h.

#define REG_RD_ADDR_ddr2_rw_phy_cfg 12

Definition at line 131 of file ddr2_defs.h.

#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16

Definition at line 141 of file ddr2_defs.h.

#define REG_RD_ADDR_ddr2_rw_pwr_down 24

Definition at line 159 of file ddr2_defs.h.

#define REG_RD_ADDR_ddr2_rw_timing 4

Definition at line 114 of file ddr2_defs.h.

#define REG_RD_INT	(	scope,
		inst,
		reg
	)	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 41 of file ddr2_defs.h.

#define REG_RD_INT_VECT	(	scope,
		inst,
		reg,
		index
	)

Value:

REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \

(index) * STRIDE_##scope##_##reg )

Definition at line 51 of file ddr2_defs.h.

#define REG_RD_VECT	(	scope,
		inst,
		reg,
		index
	)

Value:

REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
        (index) * STRIDE_##scope##_##reg )

Definition at line 27 of file ddr2_defs.h.

#define REG_TYPE_CONV	(	type,
		orgtype,
		val
	)	( { union { orgtype o; type n; } r; r.o = val; r.n; } )

Definition at line 63 of file ddr2_defs.h.

#define REG_WR	(	scope,
		inst,
		reg,
		val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \

(inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 21 of file ddr2_defs.h.

#define REG_WR_ADDR_ddr2_rw_cfg 0

Definition at line 100 of file ddr2_defs.h.

#define REG_WR_ADDR_ddr2_rw_ctrl 20

Definition at line 151 of file ddr2_defs.h.

#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36

Definition at line 191 of file ddr2_defs.h.

#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52

Definition at line 203 of file ddr2_defs.h.

#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32

Definition at line 181 of file ddr2_defs.h.

#define REG_WR_ADDR_ddr2_rw_latency 8

Definition at line 124 of file ddr2_defs.h.

#define REG_WR_ADDR_ddr2_rw_phy_cfg 12

Definition at line 132 of file ddr2_defs.h.

#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16

Definition at line 142 of file ddr2_defs.h.

#define REG_WR_ADDR_ddr2_rw_pwr_down 24

Definition at line 160 of file ddr2_defs.h.

#define REG_WR_ADDR_ddr2_rw_timing 4

Definition at line 115 of file ddr2_defs.h.

#define REG_WR_INT	(	scope,
		inst,
		reg,
		val
	)	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 46 of file ddr2_defs.h.

#define REG_WR_INT_VECT	(	scope,
		inst,
		reg,
		index,
		val
	)

Value:

REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \

(index) * STRIDE_##scope##_##reg, (val) )

Definition at line 57 of file ddr2_defs.h.

#define REG_WR_VECT	(	scope,
		inst,
		reg,
		index,
		val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
         (index) * STRIDE_##scope##_##reg, (val) )

Definition at line 34 of file ddr2_defs.h.

#define STRIDE_ddr2_rw_dll_ctrl 4

Definition at line 183 of file ddr2_defs.h.

#define STRIDE_ddr2_rw_dqs_dll_ctrl 4

Definition at line 193 of file ddr2_defs.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

regk_ddr2_al0
regk_ddr2_al1
regk_ddr2_al2
regk_ddr2_al3
regk_ddr2_al4
regk_ddr2_auto
regk_ddr2_bank4
regk_ddr2_bank8
regk_ddr2_bl4
regk_ddr2_bl8
regk_ddr2_bt_il
regk_ddr2_bt_seq
regk_ddr2_bw16
regk_ddr2_bw32
regk_ddr2_cas2
regk_ddr2_cas3
regk_ddr2_cas4
regk_ddr2_cas5
regk_ddr2_deselect
regk_ddr2_dic_weak
regk_ddr2_direct
regk_ddr2_dis
regk_ddr2_dll_dis
regk_ddr2_dll_en
regk_ddr2_dll_rst
regk_ddr2_emrs
regk_ddr2_emrs2
regk_ddr2_emrs3
regk_ddr2_full
regk_ddr2_hi_ref_rate
regk_ddr2_mrs
regk_ddr2_no
regk_ddr2_nop
regk_ddr2_ocd_adj
regk_ddr2_ocd_default
regk_ddr2_ocd_drive0
regk_ddr2_ocd_drive1
regk_ddr2_ocd_exit
regk_ddr2_odt_dis
regk_ddr2_offs
regk_ddr2_pre
regk_ddr2_pre_all
regk_ddr2_pwr_down_fast
regk_ddr2_pwr_down_slow
regk_ddr2_ref
regk_ddr2_rtt150
regk_ddr2_rtt50
regk_ddr2_rtt75
regk_ddr2_rw_cfg_default
regk_ddr2_rw_dll_ctrl_default
regk_ddr2_rw_dll_ctrl_size
regk_ddr2_rw_dqs_dll_ctrl_default
regk_ddr2_rw_dqs_dll_ctrl_size
regk_ddr2_rw_latency_default
regk_ddr2_rw_phy_cfg_default
regk_ddr2_rw_pwr_down_default
regk_ddr2_rw_timing_default
regk_ddr2_s1Gb
regk_ddr2_s256Mb
regk_ddr2_s2Gb
regk_ddr2_s4Gb
regk_ddr2_s512Mb
regk_ddr2_temp0_85
regk_ddr2_temp85_95
regk_ddr2_term150
regk_ddr2_term50
regk_ddr2_term75
regk_ddr2_test
regk_ddr2_weak
regk_ddr2_wr2
regk_ddr2_wr3
regk_ddr2_yes

Definition at line 207 of file ddr2_defs.h.

Data Structures

Macros

Enumerations

Macro Definition Documentation

Enumeration Type Documentation