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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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#include "defBF522.h"Go to the source code of this file.
Macros | |
| #define | USB_FADDR 0xffc03800 /* Function address register */ |
| #define | USB_POWER 0xffc03804 /* Power management register */ |
| #define | USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ |
| #define | USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */ |
| #define | USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */ |
| #define | USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */ |
| #define | USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */ |
| #define | USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */ |
| #define | USB_FRAME 0xffc03820 /* USB frame number */ |
| #define | USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */ |
| #define | USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */ |
| #define | USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ |
| #define | USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */ |
| #define | USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */ |
| #define | USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ |
| #define | USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ |
| #define | USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */ |
| #define | USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */ |
| #define | USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ |
| #define | USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ |
| #define | USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ |
| #define | USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ |
| #define | USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ |
| #define | USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ |
| #define | USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ |
| #define | USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ |
| #define | USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */ |
| #define | USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */ |
| #define | USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */ |
| #define | USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */ |
| #define | USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */ |
| #define | USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */ |
| #define | USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */ |
| #define | USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */ |
| #define | USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */ |
| #define | USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */ |
| #define | USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */ |
| #define | USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */ |
| #define | USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */ |
| #define | USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */ |
| #define | USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */ |
| #define | USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */ |
| #define | USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */ |
| #define | USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */ |
| #define | USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ |
| #define | USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */ |
| #define | USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */ |
| #define | USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ |
| #define | USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */ |
| #define | USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */ |
| #define | USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */ |
| #define | USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */ |
| #define | USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */ |
| #define | USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ |
| #define | USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */ |
| #define | USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ |
| #define | USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ |
| #define | USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ |
| #define | USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */ |
| #define | USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */ |
| #define | USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */ |
| #define | USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */ |
| #define | USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */ |
| #define | USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ |
| #define | USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */ |
| #define | USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ |
| #define | USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ |
| #define | USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ |
| #define | USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */ |
| #define | USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */ |
| #define | USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */ |
| #define | USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */ |
| #define | USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */ |
| #define | USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ |
| #define | USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */ |
| #define | USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ |
| #define | USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ |
| #define | USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ |
| #define | USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */ |
| #define | USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */ |
| #define | USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */ |
| #define | USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */ |
| #define | USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */ |
| #define | USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ |
| #define | USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */ |
| #define | USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ |
| #define | USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ |
| #define | USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ |
| #define | USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */ |
| #define | USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */ |
| #define | USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */ |
| #define | USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */ |
| #define | USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */ |
| #define | USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ |
| #define | USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */ |
| #define | USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ |
| #define | USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ |
| #define | USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ |
| #define | USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */ |
| #define | USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */ |
| #define | USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */ |
| #define | USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */ |
| #define | USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */ |
| #define | USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ |
| #define | USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */ |
| #define | USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ |
| #define | USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ |
| #define | USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ |
| #define | USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */ |
| #define | USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */ |
| #define | USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */ |
| #define | USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */ |
| #define | USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */ |
| #define | USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ |
| #define | USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */ |
| #define | USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ |
| #define | USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ |
| #define | USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ |
| #define | USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */ |
| #define | USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */ |
| #define | USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */ |
| #define | USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */ |
| #define | USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */ |
| #define | USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ |
| #define | USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */ |
| #define | USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ |
| #define | USB_EP_NI7_RXINTERVAL 0xffc03be0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ |
| #define | USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ |
| #define | USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */ |
| #define | USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */ |
| #define | USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ |
| #define | USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ |
| #define | USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ |
| #define | USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ |
| #define | USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */ |
| #define | USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ |
| #define | USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ |
| #define | USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ |
| #define | USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ |
| #define | USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */ |
| #define | USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ |
| #define | USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ |
| #define | USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ |
| #define | USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ |
| #define | USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */ |
| #define | USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ |
| #define | USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ |
| #define | USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ |
| #define | USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ |
| #define | USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */ |
| #define | USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ |
| #define | USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ |
| #define | USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ |
| #define | USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ |
| #define | USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */ |
| #define | USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ |
| #define | USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ |
| #define | USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ |
| #define | USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ |
| #define | USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */ |
| #define | USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ |
| #define | USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ |
| #define | USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ |
| #define | USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ |
| #define | USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */ |
| #define | USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ |
| #define | USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ |
| #define | USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ |
| #define | USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ |
| #define | FUNCTION_ADDRESS 0x7f /* Function address */ |
| #define | ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ |
| #define | nENABLE_SUSPENDM 0x0 |
| #define | SUSPEND_MODE 0x2 /* Suspend Mode indicator */ |
| #define | nSUSPEND_MODE 0x0 |
| #define | RESUME_MODE 0x4 /* DMA Mode */ |
| #define | nRESUME_MODE 0x0 |
| #define | RESET 0x8 /* Reset indicator */ |
| #define | nRESET 0x0 |
| #define | HS_MODE 0x10 /* High Speed mode indicator */ |
| #define | nHS_MODE 0x0 |
| #define | HS_ENABLE 0x20 /* high Speed Enable */ |
| #define | nHS_ENABLE 0x0 |
| #define | SOFT_CONN 0x40 /* Soft connect */ |
| #define | nSOFT_CONN 0x0 |
| #define | ISO_UPDATE 0x80 /* Isochronous update */ |
| #define | nISO_UPDATE 0x0 |
| #define | EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ |
| #define | nEP0_TX 0x0 |
| #define | EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ |
| #define | nEP1_TX 0x0 |
| #define | EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ |
| #define | nEP2_TX 0x0 |
| #define | EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ |
| #define | nEP3_TX 0x0 |
| #define | EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ |
| #define | nEP4_TX 0x0 |
| #define | EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ |
| #define | nEP5_TX 0x0 |
| #define | EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ |
| #define | nEP6_TX 0x0 |
| #define | EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ |
| #define | nEP7_TX 0x0 |
| #define | EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ |
| #define | nEP1_RX 0x0 |
| #define | EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ |
| #define | nEP2_RX 0x0 |
| #define | EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ |
| #define | nEP3_RX 0x0 |
| #define | EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ |
| #define | nEP4_RX 0x0 |
| #define | EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ |
| #define | nEP5_RX 0x0 |
| #define | EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ |
| #define | nEP6_RX 0x0 |
| #define | EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ |
| #define | nEP7_RX 0x0 |
| #define | EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ |
| #define | nEP0_TX_E 0x0 |
| #define | EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ |
| #define | nEP1_TX_E 0x0 |
| #define | EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ |
| #define | nEP2_TX_E 0x0 |
| #define | EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ |
| #define | nEP3_TX_E 0x0 |
| #define | EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ |
| #define | nEP4_TX_E 0x0 |
| #define | EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ |
| #define | nEP5_TX_E 0x0 |
| #define | EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ |
| #define | nEP6_TX_E 0x0 |
| #define | EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ |
| #define | nEP7_TX_E 0x0 |
| #define | EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ |
| #define | nEP1_RX_E 0x0 |
| #define | EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ |
| #define | nEP2_RX_E 0x0 |
| #define | EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ |
| #define | nEP3_RX_E 0x0 |
| #define | EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ |
| #define | nEP4_RX_E 0x0 |
| #define | EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ |
| #define | nEP5_RX_E 0x0 |
| #define | EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ |
| #define | nEP6_RX_E 0x0 |
| #define | EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ |
| #define | nEP7_RX_E 0x0 |
| #define | SUSPEND_B 0x1 /* Suspend indicator */ |
| #define | nSUSPEND_B 0x0 |
| #define | RESUME_B 0x2 /* Resume indicator */ |
| #define | nRESUME_B 0x0 |
| #define | RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ |
| #define | nRESET_OR_BABLE_B 0x0 |
| #define | SOF_B 0x8 /* Start of frame */ |
| #define | nSOF_B 0x0 |
| #define | CONN_B 0x10 /* Connection indicator */ |
| #define | nCONN_B 0x0 |
| #define | DISCON_B 0x20 /* Disconnect indicator */ |
| #define | nDISCON_B 0x0 |
| #define | SESSION_REQ_B 0x40 /* Session Request */ |
| #define | nSESSION_REQ_B 0x0 |
| #define | VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ |
| #define | nVBUS_ERROR_B 0x0 |
| #define | SUSPEND_BE 0x1 /* Suspend indicator int enable */ |
| #define | nSUSPEND_BE 0x0 |
| #define | RESUME_BE 0x2 /* Resume indicator int enable */ |
| #define | nRESUME_BE 0x0 |
| #define | RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ |
| #define | nRESET_OR_BABLE_BE 0x0 |
| #define | SOF_BE 0x8 /* Start of frame int enable */ |
| #define | nSOF_BE 0x0 |
| #define | CONN_BE 0x10 /* Connection indicator int enable */ |
| #define | nCONN_BE 0x0 |
| #define | DISCON_BE 0x20 /* Disconnect indicator int enable */ |
| #define | nDISCON_BE 0x0 |
| #define | SESSION_REQ_BE 0x40 /* Session Request int enable */ |
| #define | nSESSION_REQ_BE 0x0 |
| #define | VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ |
| #define | nVBUS_ERROR_BE 0x0 |
| #define | FRAME_NUMBER 0x7ff /* Frame number */ |
| #define | SELECTED_ENDPOINT 0xf /* selected endpoint */ |
| #define | GLOBAL_ENA 0x1 /* enables USB module */ |
| #define | nGLOBAL_ENA 0x0 |
| #define | EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ |
| #define | nEP1_TX_ENA 0x0 |
| #define | EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ |
| #define | nEP2_TX_ENA 0x0 |
| #define | EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ |
| #define | nEP3_TX_ENA 0x0 |
| #define | EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ |
| #define | nEP4_TX_ENA 0x0 |
| #define | EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ |
| #define | nEP5_TX_ENA 0x0 |
| #define | EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ |
| #define | nEP6_TX_ENA 0x0 |
| #define | EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ |
| #define | nEP7_TX_ENA 0x0 |
| #define | EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ |
| #define | nEP1_RX_ENA 0x0 |
| #define | EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ |
| #define | nEP2_RX_ENA 0x0 |
| #define | EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ |
| #define | nEP3_RX_ENA 0x0 |
| #define | EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ |
| #define | nEP4_RX_ENA 0x0 |
| #define | EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ |
| #define | nEP5_RX_ENA 0x0 |
| #define | EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ |
| #define | nEP6_RX_ENA 0x0 |
| #define | EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ |
| #define | nEP7_RX_ENA 0x0 |
| #define | SESSION 0x1 /* session indicator */ |
| #define | nSESSION 0x0 |
| #define | HOST_REQ 0x2 /* Host negotiation request */ |
| #define | nHOST_REQ 0x0 |
| #define | HOST_MODE 0x4 /* indicates USBDRC is a host */ |
| #define | nHOST_MODE 0x0 |
| #define | VBUS0 0x8 /* Vbus level indicator[0] */ |
| #define | nVBUS0 0x0 |
| #define | VBUS1 0x10 /* Vbus level indicator[1] */ |
| #define | nVBUS1 0x0 |
| #define | LSDEV 0x20 /* Low-speed indicator */ |
| #define | nLSDEV 0x0 |
| #define | FSDEV 0x40 /* Full or High-speed indicator */ |
| #define | nFSDEV 0x0 |
| #define | B_DEVICE 0x80 /* A' or 'B' device indicator */ |
| #define | nB_DEVICE 0x0 |
| #define | DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ |
| #define | nDRIVE_VBUS_ON 0x0 |
| #define | DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ |
| #define | nDRIVE_VBUS_OFF 0x0 |
| #define | CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ |
| #define | nCHRG_VBUS_START 0x0 |
| #define | CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ |
| #define | nCHRG_VBUS_END 0x0 |
| #define | DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ |
| #define | nDISCHRG_VBUS_START 0x0 |
| #define | DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ |
| #define | nDISCHRG_VBUS_END 0x0 |
| #define | DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ |
| #define | nDRIVE_VBUS_ON_ENA 0x0 |
| #define | DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ |
| #define | nDRIVE_VBUS_OFF_ENA 0x0 |
| #define | CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ |
| #define | nCHRG_VBUS_START_ENA 0x0 |
| #define | CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ |
| #define | nCHRG_VBUS_END_ENA 0x0 |
| #define | DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ |
| #define | nDISCHRG_VBUS_START_ENA 0x0 |
| #define | DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ |
| #define | nDISCHRG_VBUS_END_ENA 0x0 |
| #define | RXPKTRDY 0x1 /* data packet receive indicator */ |
| #define | nRXPKTRDY 0x0 |
| #define | TXPKTRDY 0x2 /* data packet in FIFO indicator */ |
| #define | nTXPKTRDY 0x0 |
| #define | STALL_SENT 0x4 /* STALL handshake sent */ |
| #define | nSTALL_SENT 0x0 |
| #define | DATAEND 0x8 /* Data end indicator */ |
| #define | nDATAEND 0x0 |
| #define | SETUPEND 0x10 /* Setup end */ |
| #define | nSETUPEND 0x0 |
| #define | SENDSTALL 0x20 /* Send STALL handshake */ |
| #define | nSENDSTALL 0x0 |
| #define | SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ |
| #define | nSERVICED_RXPKTRDY 0x0 |
| #define | SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ |
| #define | nSERVICED_SETUPEND 0x0 |
| #define | FLUSHFIFO 0x100 /* flush endpoint FIFO */ |
| #define | nFLUSHFIFO 0x0 |
| #define | STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ |
| #define | nSTALL_RECEIVED_H 0x0 |
| #define | SETUPPKT_H 0x8 /* send Setup token host mode */ |
| #define | nSETUPPKT_H 0x0 |
| #define | ERROR_H 0x10 /* timeout error indicator host mode */ |
| #define | nERROR_H 0x0 |
| #define | REQPKT_H 0x20 /* Request an IN transaction host mode */ |
| #define | nREQPKT_H 0x0 |
| #define | STATUSPKT_H 0x40 /* Status stage transaction host mode */ |
| #define | nSTATUSPKT_H 0x0 |
| #define | NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ |
| #define | nNAK_TIMEOUT_H 0x0 |
| #define | EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ |
| #define | EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ |
| #define | MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ |
| #define | MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ |
| #define | TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ |
| #define | nTXPKTRDY_T 0x0 |
| #define | FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ |
| #define | nFIFO_NOT_EMPTY_T 0x0 |
| #define | UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ |
| #define | nUNDERRUN_T 0x0 |
| #define | FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ |
| #define | nFLUSHFIFO_T 0x0 |
| #define | STALL_SEND_T 0x10 /* issue a Stall handshake */ |
| #define | nSTALL_SEND_T 0x0 |
| #define | STALL_SENT_T 0x20 /* Stall handshake transmitted */ |
| #define | nSTALL_SENT_T 0x0 |
| #define | CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ |
| #define | nCLEAR_DATATOGGLE_T 0x0 |
| #define | INCOMPTX_T 0x80 /* indicates that a large packet is split */ |
| #define | nINCOMPTX_T 0x0 |
| #define | DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ |
| #define | nDMAREQMODE_T 0x0 |
| #define | FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ |
| #define | nFORCE_DATATOGGLE_T 0x0 |
| #define | DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ |
| #define | nDMAREQ_ENA_T 0x0 |
| #define | ISO_T 0x4000 /* enable Isochronous transfers */ |
| #define | nISO_T 0x0 |
| #define | AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ |
| #define | nAUTOSET_T 0x0 |
| #define | ERROR_TH 0x4 /* error condition host mode */ |
| #define | nERROR_TH 0x0 |
| #define | STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ |
| #define | nSTALL_RECEIVED_TH 0x0 |
| #define | NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ |
| #define | nNAK_TIMEOUT_TH 0x0 |
| #define | TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ |
| #define | RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ |
| #define | nRXPKTRDY_R 0x0 |
| #define | FIFO_FULL_R 0x2 /* FIFO not empty */ |
| #define | nFIFO_FULL_R 0x0 |
| #define | OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ |
| #define | nOVERRUN_R 0x0 |
| #define | DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ |
| #define | nDATAERROR_R 0x0 |
| #define | FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ |
| #define | nFLUSHFIFO_R 0x0 |
| #define | STALL_SEND_R 0x20 /* issue a Stall handshake */ |
| #define | nSTALL_SEND_R 0x0 |
| #define | STALL_SENT_R 0x40 /* Stall handshake transmitted */ |
| #define | nSTALL_SENT_R 0x0 |
| #define | CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ |
| #define | nCLEAR_DATATOGGLE_R 0x0 |
| #define | INCOMPRX_R 0x100 /* indicates that a large packet is split */ |
| #define | nINCOMPRX_R 0x0 |
| #define | DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ |
| #define | nDMAREQMODE_R 0x0 |
| #define | DISNYET_R 0x1000 /* disable Nyet handshakes */ |
| #define | nDISNYET_R 0x0 |
| #define | DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ |
| #define | nDMAREQ_ENA_R 0x0 |
| #define | ISO_R 0x4000 /* enable Isochronous transfers */ |
| #define | nISO_R 0x0 |
| #define | AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ |
| #define | nAUTOCLEAR_R 0x0 |
| #define | ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ |
| #define | nERROR_RH 0x0 |
| #define | REQPKT_RH 0x20 /* request an IN transaction host mode */ |
| #define | nREQPKT_RH 0x0 |
| #define | STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ |
| #define | nSTALL_RECEIVED_RH 0x0 |
| #define | INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ |
| #define | nINCOMPRX_RH 0x0 |
| #define | DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ |
| #define | nDMAREQMODE_RH 0x0 |
| #define | AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ |
| #define | nAUTOREQ_RH 0x0 |
| #define | RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ |
| #define | TARGET_EP_NO_T 0xf /* EP number */ |
| #define | PROTOCOL_T 0xc /* transfer type */ |
| #define | TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ |
| #define | TARGET_EP_NO_R 0xf /* EP number */ |
| #define | PROTOCOL_R 0xc /* transfer type */ |
| #define | RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ |
| #define | DMA0_INT 0x1 /* DMA0 pending interrupt */ |
| #define | nDMA0_INT 0x0 |
| #define | DMA1_INT 0x2 /* DMA1 pending interrupt */ |
| #define | nDMA1_INT 0x0 |
| #define | DMA2_INT 0x4 /* DMA2 pending interrupt */ |
| #define | nDMA2_INT 0x0 |
| #define | DMA3_INT 0x8 /* DMA3 pending interrupt */ |
| #define | nDMA3_INT 0x0 |
| #define | DMA4_INT 0x10 /* DMA4 pending interrupt */ |
| #define | nDMA4_INT 0x0 |
| #define | DMA5_INT 0x20 /* DMA5 pending interrupt */ |
| #define | nDMA5_INT 0x0 |
| #define | DMA6_INT 0x40 /* DMA6 pending interrupt */ |
| #define | nDMA6_INT 0x0 |
| #define | DMA7_INT 0x80 /* DMA7 pending interrupt */ |
| #define | nDMA7_INT 0x0 |
| #define | DMA_ENA 0x1 /* DMA enable */ |
| #define | nDMA_ENA 0x0 |
| #define | DIRECTION 0x2 /* direction of DMA transfer */ |
| #define | nDIRECTION 0x0 |
| #define | MODE 0x4 /* DMA Bus error */ |
| #define | nMODE 0x0 |
| #define | INT_ENA 0x8 /* Interrupt enable */ |
| #define | nINT_ENA 0x0 |
| #define | EPNUM 0xf0 /* EP number */ |
| #define | BUSERROR 0x100 /* DMA Bus error */ |
| #define | nBUSERROR 0x0 |
| #define | DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ |
| #define | DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ |
| #define | DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ |
| #define | DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ |
| #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ |
Definition at line 596 of file defBF525.h.
| #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ |
Definition at line 608 of file defBF525.h.
| #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ |
Definition at line 555 of file defBF525.h.
| #define B_DEVICE 0x80 /* A' or 'B' device indicator */ |
Definition at line 447 of file defBF525.h.
| #define BUSERROR 0x100 /* DMA Bus error */ |
Definition at line 663 of file defBF525.h.
| #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ |
Definition at line 458 of file defBF525.h.
| #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ |
Definition at line 473 of file defBF525.h.
| #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ |
Definition at line 456 of file defBF525.h.
| #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ |
Definition at line 471 of file defBF525.h.
| #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ |
Definition at line 584 of file defBF525.h.
| #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ |
Definition at line 543 of file defBF525.h.
| #define CONN_B 0x10 /* Connection indicator */ |
Definition at line 362 of file defBF525.h.
| #define CONN_BE 0x10 /* Connection indicator int enable */ |
Definition at line 381 of file defBF525.h.
| #define DATAEND 0x8 /* Data end indicator */ |
Definition at line 488 of file defBF525.h.
| #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ |
Definition at line 576 of file defBF525.h.
| #define DIRECTION 0x2 /* direction of DMA transfer */ |
Definition at line 656 of file defBF525.h.
| #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ |
Definition at line 462 of file defBF525.h.
| #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ |
Definition at line 477 of file defBF525.h.
| #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ |
Definition at line 460 of file defBF525.h.
| #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ |
Definition at line 475 of file defBF525.h.
| #define DISCON_B 0x20 /* Disconnect indicator */ |
Definition at line 364 of file defBF525.h.
| #define DISCON_BE 0x20 /* Disconnect indicator int enable */ |
Definition at line 383 of file defBF525.h.
| #define DISNYET_R 0x1000 /* disable Nyet handshakes */ |
Definition at line 590 of file defBF525.h.
| #define DMA0_INT 0x1 /* DMA0 pending interrupt */ |
Definition at line 635 of file defBF525.h.
| #define DMA1_INT 0x2 /* DMA1 pending interrupt */ |
Definition at line 637 of file defBF525.h.
| #define DMA2_INT 0x4 /* DMA2 pending interrupt */ |
Definition at line 639 of file defBF525.h.
| #define DMA3_INT 0x8 /* DMA3 pending interrupt */ |
Definition at line 641 of file defBF525.h.
| #define DMA4_INT 0x10 /* DMA4 pending interrupt */ |
Definition at line 643 of file defBF525.h.
| #define DMA5_INT 0x20 /* DMA5 pending interrupt */ |
Definition at line 645 of file defBF525.h.
| #define DMA6_INT 0x40 /* DMA6 pending interrupt */ |
Definition at line 647 of file defBF525.h.
| #define DMA7_INT 0x80 /* DMA7 pending interrupt */ |
Definition at line 649 of file defBF525.h.
| #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ |
Definition at line 668 of file defBF525.h.
| #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ |
Definition at line 672 of file defBF525.h.
| #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ |
Definition at line 676 of file defBF525.h.
| #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ |
Definition at line 680 of file defBF525.h.
| #define DMA_ENA 0x1 /* DMA enable */ |
Definition at line 654 of file defBF525.h.
| #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ |
Definition at line 592 of file defBF525.h.
| #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ |
Definition at line 551 of file defBF525.h.
| #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ |
Definition at line 588 of file defBF525.h.
| #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ |
Definition at line 606 of file defBF525.h.
| #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ |
Definition at line 547 of file defBF525.h.
| #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ |
Definition at line 454 of file defBF525.h.
| #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ |
Definition at line 469 of file defBF525.h.
| #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ |
Definition at line 452 of file defBF525.h.
| #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ |
Definition at line 467 of file defBF525.h.
| #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ |
Definition at line 263 of file defBF525.h.
| #define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ |
Definition at line 519 of file defBF525.h.
| #define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ |
Definition at line 515 of file defBF525.h.
| #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ |
Definition at line 282 of file defBF525.h.
| #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ |
Definition at line 318 of file defBF525.h.
| #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ |
Definition at line 301 of file defBF525.h.
| #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ |
Definition at line 337 of file defBF525.h.
| #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ |
Definition at line 416 of file defBF525.h.
| #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ |
Definition at line 284 of file defBF525.h.
| #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ |
Definition at line 320 of file defBF525.h.
| #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ |
Definition at line 402 of file defBF525.h.
| #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ |
Definition at line 303 of file defBF525.h.
| #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ |
Definition at line 339 of file defBF525.h.
| #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ |
Definition at line 418 of file defBF525.h.
| #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ |
Definition at line 286 of file defBF525.h.
| #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ |
Definition at line 322 of file defBF525.h.
| #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ |
Definition at line 404 of file defBF525.h.
| #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ |
Definition at line 305 of file defBF525.h.
| #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ |
Definition at line 341 of file defBF525.h.
| #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ |
Definition at line 420 of file defBF525.h.
| #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ |
Definition at line 288 of file defBF525.h.
| #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ |
Definition at line 324 of file defBF525.h.
| #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ |
Definition at line 406 of file defBF525.h.
| #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ |
Definition at line 307 of file defBF525.h.
| #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ |
Definition at line 343 of file defBF525.h.
| #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ |
Definition at line 422 of file defBF525.h.
| #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ |
Definition at line 290 of file defBF525.h.
| #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ |
Definition at line 326 of file defBF525.h.
| #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ |
Definition at line 408 of file defBF525.h.
| #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ |
Definition at line 309 of file defBF525.h.
| #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ |
Definition at line 345 of file defBF525.h.
| #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ |
Definition at line 424 of file defBF525.h.
| #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ |
Definition at line 292 of file defBF525.h.
| #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ |
Definition at line 328 of file defBF525.h.
| #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ |
Definition at line 410 of file defBF525.h.
| #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ |
Definition at line 311 of file defBF525.h.
| #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ |
Definition at line 347 of file defBF525.h.
| #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ |
Definition at line 426 of file defBF525.h.
| #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ |
Definition at line 294 of file defBF525.h.
| #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ |
Definition at line 330 of file defBF525.h.
| #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ |
Definition at line 412 of file defBF525.h.
| #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ |
Definition at line 313 of file defBF525.h.
| #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ |
Definition at line 349 of file defBF525.h.
| #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ |
Definition at line 428 of file defBF525.h.
| #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ |
Definition at line 296 of file defBF525.h.
| #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ |
Definition at line 332 of file defBF525.h.
| #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ |
Definition at line 414 of file defBF525.h.
| #define EPNUM 0xf0 /* EP number */ |
Definition at line 662 of file defBF525.h.
| #define ERROR_H 0x10 /* timeout error indicator host mode */ |
Definition at line 504 of file defBF525.h.
| #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ |
Definition at line 598 of file defBF525.h.
| #define ERROR_TH 0x4 /* error condition host mode */ |
Definition at line 557 of file defBF525.h.
| #define FIFO_FULL_R 0x2 /* FIFO not empty */ |
Definition at line 572 of file defBF525.h.
| #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ |
Definition at line 533 of file defBF525.h.
| #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ |
Definition at line 498 of file defBF525.h.
| #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ |
Definition at line 578 of file defBF525.h.
| #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ |
Definition at line 537 of file defBF525.h.
| #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ |
Definition at line 549 of file defBF525.h.
| #define FRAME_NUMBER 0x7ff /* Frame number */ |
Definition at line 392 of file defBF525.h.
| #define FSDEV 0x40 /* Full or High-speed indicator */ |
Definition at line 445 of file defBF525.h.
| #define FUNCTION_ADDRESS 0x7f /* Function address */ |
Definition at line 259 of file defBF525.h.
| #define GLOBAL_ENA 0x1 /* enables USB module */ |
Definition at line 400 of file defBF525.h.
| #define HOST_MODE 0x4 /* indicates USBDRC is a host */ |
Definition at line 437 of file defBF525.h.
| #define HOST_REQ 0x2 /* Host negotiation request */ |
Definition at line 435 of file defBF525.h.
| #define HS_ENABLE 0x20 /* high Speed Enable */ |
Definition at line 273 of file defBF525.h.
| #define HS_MODE 0x10 /* High Speed mode indicator */ |
Definition at line 271 of file defBF525.h.
| #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ |
Definition at line 586 of file defBF525.h.
| #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ |
Definition at line 604 of file defBF525.h.
| #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ |
Definition at line 545 of file defBF525.h.
| #define INT_ENA 0x8 /* Interrupt enable */ |
Definition at line 660 of file defBF525.h.
| #define ISO_R 0x4000 /* enable Isochronous transfers */ |
Definition at line 594 of file defBF525.h.
| #define ISO_T 0x4000 /* enable Isochronous transfers */ |
Definition at line 553 of file defBF525.h.
| #define ISO_UPDATE 0x80 /* Isochronous update */ |
Definition at line 277 of file defBF525.h.
| #define LSDEV 0x20 /* Low-speed indicator */ |
Definition at line 443 of file defBF525.h.
| #define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ |
Definition at line 527 of file defBF525.h.
| #define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ |
Definition at line 523 of file defBF525.h.
| #define MODE 0x4 /* DMA Bus error */ |
Definition at line 658 of file defBF525.h.
| #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ |
Definition at line 510 of file defBF525.h.
| #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ |
Definition at line 561 of file defBF525.h.
| #define nAUTOCLEAR_R 0x0 |
Definition at line 597 of file defBF525.h.
| #define nAUTOREQ_RH 0x0 |
Definition at line 609 of file defBF525.h.
| #define nAUTOSET_T 0x0 |
Definition at line 556 of file defBF525.h.
| #define nB_DEVICE 0x0 |
Definition at line 448 of file defBF525.h.
| #define nBUSERROR 0x0 |
Definition at line 664 of file defBF525.h.
| #define nCHRG_VBUS_END 0x0 |
Definition at line 459 of file defBF525.h.
| #define nCHRG_VBUS_END_ENA 0x0 |
Definition at line 474 of file defBF525.h.
| #define nCHRG_VBUS_START 0x0 |
Definition at line 457 of file defBF525.h.
| #define nCHRG_VBUS_START_ENA 0x0 |
Definition at line 472 of file defBF525.h.
| #define nCLEAR_DATATOGGLE_R 0x0 |
Definition at line 585 of file defBF525.h.
| #define nCLEAR_DATATOGGLE_T 0x0 |
Definition at line 544 of file defBF525.h.
| #define nCONN_B 0x0 |
Definition at line 363 of file defBF525.h.
| #define nCONN_BE 0x0 |
Definition at line 382 of file defBF525.h.
| #define nDATAEND 0x0 |
Definition at line 489 of file defBF525.h.
| #define nDATAERROR_R 0x0 |
Definition at line 577 of file defBF525.h.
| #define nDIRECTION 0x0 |
Definition at line 657 of file defBF525.h.
| #define nDISCHRG_VBUS_END 0x0 |
Definition at line 463 of file defBF525.h.
| #define nDISCHRG_VBUS_END_ENA 0x0 |
Definition at line 478 of file defBF525.h.
| #define nDISCHRG_VBUS_START 0x0 |
Definition at line 461 of file defBF525.h.
| #define nDISCHRG_VBUS_START_ENA 0x0 |
Definition at line 476 of file defBF525.h.
| #define nDISCON_B 0x0 |
Definition at line 365 of file defBF525.h.
| #define nDISCON_BE 0x0 |
Definition at line 384 of file defBF525.h.
| #define nDISNYET_R 0x0 |
Definition at line 591 of file defBF525.h.
| #define nDMA0_INT 0x0 |
Definition at line 636 of file defBF525.h.
| #define nDMA1_INT 0x0 |
Definition at line 638 of file defBF525.h.
| #define nDMA2_INT 0x0 |
Definition at line 640 of file defBF525.h.
| #define nDMA3_INT 0x0 |
Definition at line 642 of file defBF525.h.
| #define nDMA4_INT 0x0 |
Definition at line 644 of file defBF525.h.
| #define nDMA5_INT 0x0 |
Definition at line 646 of file defBF525.h.
| #define nDMA6_INT 0x0 |
Definition at line 648 of file defBF525.h.
| #define nDMA7_INT 0x0 |
Definition at line 650 of file defBF525.h.
| #define nDMA_ENA 0x0 |
Definition at line 655 of file defBF525.h.
| #define nDMAREQ_ENA_R 0x0 |
Definition at line 593 of file defBF525.h.
| #define nDMAREQ_ENA_T 0x0 |
Definition at line 552 of file defBF525.h.
| #define nDMAREQMODE_R 0x0 |
Definition at line 589 of file defBF525.h.
| #define nDMAREQMODE_RH 0x0 |
Definition at line 607 of file defBF525.h.
| #define nDMAREQMODE_T 0x0 |
Definition at line 548 of file defBF525.h.
| #define nDRIVE_VBUS_OFF 0x0 |
Definition at line 455 of file defBF525.h.
| #define nDRIVE_VBUS_OFF_ENA 0x0 |
Definition at line 470 of file defBF525.h.
| #define nDRIVE_VBUS_ON 0x0 |
Definition at line 453 of file defBF525.h.
| #define nDRIVE_VBUS_ON_ENA 0x0 |
Definition at line 468 of file defBF525.h.
| #define nENABLE_SUSPENDM 0x0 |
Definition at line 264 of file defBF525.h.
| #define nEP0_TX 0x0 |
Definition at line 283 of file defBF525.h.
| #define nEP0_TX_E 0x0 |
Definition at line 319 of file defBF525.h.
| #define nEP1_RX 0x0 |
Definition at line 302 of file defBF525.h.
| #define nEP1_RX_E 0x0 |
Definition at line 338 of file defBF525.h.
| #define nEP1_RX_ENA 0x0 |
Definition at line 417 of file defBF525.h.
| #define nEP1_TX 0x0 |
Definition at line 285 of file defBF525.h.
| #define nEP1_TX_E 0x0 |
Definition at line 321 of file defBF525.h.
| #define nEP1_TX_ENA 0x0 |
Definition at line 403 of file defBF525.h.
| #define nEP2_RX 0x0 |
Definition at line 304 of file defBF525.h.
| #define nEP2_RX_E 0x0 |
Definition at line 340 of file defBF525.h.
| #define nEP2_RX_ENA 0x0 |
Definition at line 419 of file defBF525.h.
| #define nEP2_TX 0x0 |
Definition at line 287 of file defBF525.h.
| #define nEP2_TX_E 0x0 |
Definition at line 323 of file defBF525.h.
| #define nEP2_TX_ENA 0x0 |
Definition at line 405 of file defBF525.h.
| #define nEP3_RX 0x0 |
Definition at line 306 of file defBF525.h.
| #define nEP3_RX_E 0x0 |
Definition at line 342 of file defBF525.h.
| #define nEP3_RX_ENA 0x0 |
Definition at line 421 of file defBF525.h.
| #define nEP3_TX 0x0 |
Definition at line 289 of file defBF525.h.
| #define nEP3_TX_E 0x0 |
Definition at line 325 of file defBF525.h.
| #define nEP3_TX_ENA 0x0 |
Definition at line 407 of file defBF525.h.
| #define nEP4_RX 0x0 |
Definition at line 308 of file defBF525.h.
| #define nEP4_RX_E 0x0 |
Definition at line 344 of file defBF525.h.
| #define nEP4_RX_ENA 0x0 |
Definition at line 423 of file defBF525.h.
| #define nEP4_TX 0x0 |
Definition at line 291 of file defBF525.h.
| #define nEP4_TX_E 0x0 |
Definition at line 327 of file defBF525.h.
| #define nEP4_TX_ENA 0x0 |
Definition at line 409 of file defBF525.h.
| #define nEP5_RX 0x0 |
Definition at line 310 of file defBF525.h.
| #define nEP5_RX_E 0x0 |
Definition at line 346 of file defBF525.h.
| #define nEP5_RX_ENA 0x0 |
Definition at line 425 of file defBF525.h.
| #define nEP5_TX 0x0 |
Definition at line 293 of file defBF525.h.
| #define nEP5_TX_E 0x0 |
Definition at line 329 of file defBF525.h.
| #define nEP5_TX_ENA 0x0 |
Definition at line 411 of file defBF525.h.
| #define nEP6_RX 0x0 |
Definition at line 312 of file defBF525.h.
| #define nEP6_RX_E 0x0 |
Definition at line 348 of file defBF525.h.
| #define nEP6_RX_ENA 0x0 |
Definition at line 427 of file defBF525.h.
| #define nEP6_TX 0x0 |
Definition at line 295 of file defBF525.h.
| #define nEP6_TX_E 0x0 |
Definition at line 331 of file defBF525.h.
| #define nEP6_TX_ENA 0x0 |
Definition at line 413 of file defBF525.h.
| #define nEP7_RX 0x0 |
Definition at line 314 of file defBF525.h.
| #define nEP7_RX_E 0x0 |
Definition at line 350 of file defBF525.h.
| #define nEP7_RX_ENA 0x0 |
Definition at line 429 of file defBF525.h.
| #define nEP7_TX 0x0 |
Definition at line 297 of file defBF525.h.
| #define nEP7_TX_E 0x0 |
Definition at line 333 of file defBF525.h.
| #define nEP7_TX_ENA 0x0 |
Definition at line 415 of file defBF525.h.
| #define nERROR_H 0x0 |
Definition at line 505 of file defBF525.h.
| #define nERROR_RH 0x0 |
Definition at line 599 of file defBF525.h.
| #define nERROR_TH 0x0 |
Definition at line 558 of file defBF525.h.
| #define nFIFO_FULL_R 0x0 |
Definition at line 573 of file defBF525.h.
| #define nFIFO_NOT_EMPTY_T 0x0 |
Definition at line 534 of file defBF525.h.
| #define nFLUSHFIFO 0x0 |
Definition at line 499 of file defBF525.h.
| #define nFLUSHFIFO_R 0x0 |
Definition at line 579 of file defBF525.h.
| #define nFLUSHFIFO_T 0x0 |
Definition at line 538 of file defBF525.h.
| #define nFORCE_DATATOGGLE_T 0x0 |
Definition at line 550 of file defBF525.h.
| #define nFSDEV 0x0 |
Definition at line 446 of file defBF525.h.
| #define nGLOBAL_ENA 0x0 |
Definition at line 401 of file defBF525.h.
| #define nHOST_MODE 0x0 |
Definition at line 438 of file defBF525.h.
| #define nHOST_REQ 0x0 |
Definition at line 436 of file defBF525.h.
| #define nHS_ENABLE 0x0 |
Definition at line 274 of file defBF525.h.
| #define nHS_MODE 0x0 |
Definition at line 272 of file defBF525.h.
| #define nINCOMPRX_R 0x0 |
Definition at line 587 of file defBF525.h.
| #define nINCOMPRX_RH 0x0 |
Definition at line 605 of file defBF525.h.
| #define nINCOMPTX_T 0x0 |
Definition at line 546 of file defBF525.h.
| #define nINT_ENA 0x0 |
Definition at line 661 of file defBF525.h.
| #define nISO_R 0x0 |
Definition at line 595 of file defBF525.h.
| #define nISO_T 0x0 |
Definition at line 554 of file defBF525.h.
| #define nISO_UPDATE 0x0 |
Definition at line 278 of file defBF525.h.
| #define nLSDEV 0x0 |
Definition at line 444 of file defBF525.h.
| #define nMODE 0x0 |
Definition at line 659 of file defBF525.h.
| #define nNAK_TIMEOUT_H 0x0 |
Definition at line 511 of file defBF525.h.
| #define nNAK_TIMEOUT_TH 0x0 |
Definition at line 562 of file defBF525.h.
| #define nOVERRUN_R 0x0 |
Definition at line 575 of file defBF525.h.
| #define nREQPKT_H 0x0 |
Definition at line 507 of file defBF525.h.
| #define nREQPKT_RH 0x0 |
Definition at line 601 of file defBF525.h.
| #define nRESET 0x0 |
Definition at line 270 of file defBF525.h.
| #define nRESET_OR_BABLE_B 0x0 |
Definition at line 359 of file defBF525.h.
| #define nRESET_OR_BABLE_BE 0x0 |
Definition at line 378 of file defBF525.h.
| #define nRESUME_B 0x0 |
Definition at line 357 of file defBF525.h.
| #define nRESUME_BE 0x0 |
Definition at line 376 of file defBF525.h.
| #define nRESUME_MODE 0x0 |
Definition at line 268 of file defBF525.h.
| #define nRXPKTRDY 0x0 |
Definition at line 483 of file defBF525.h.
| #define nRXPKTRDY_R 0x0 |
Definition at line 571 of file defBF525.h.
| #define nSENDSTALL 0x0 |
Definition at line 493 of file defBF525.h.
| #define nSERVICED_RXPKTRDY 0x0 |
Definition at line 495 of file defBF525.h.
| #define nSERVICED_SETUPEND 0x0 |
Definition at line 497 of file defBF525.h.
| #define nSESSION 0x0 |
Definition at line 434 of file defBF525.h.
| #define nSESSION_REQ_B 0x0 |
Definition at line 367 of file defBF525.h.
| #define nSESSION_REQ_BE 0x0 |
Definition at line 386 of file defBF525.h.
| #define nSETUPEND 0x0 |
Definition at line 491 of file defBF525.h.
| #define nSETUPPKT_H 0x0 |
Definition at line 503 of file defBF525.h.
| #define nSOF_B 0x0 |
Definition at line 361 of file defBF525.h.
| #define nSOF_BE 0x0 |
Definition at line 380 of file defBF525.h.
| #define nSOFT_CONN 0x0 |
Definition at line 276 of file defBF525.h.
| #define nSTALL_RECEIVED_H 0x0 |
Definition at line 501 of file defBF525.h.
| #define nSTALL_RECEIVED_RH 0x0 |
Definition at line 603 of file defBF525.h.
| #define nSTALL_RECEIVED_TH 0x0 |
Definition at line 560 of file defBF525.h.
| #define nSTALL_SEND_R 0x0 |
Definition at line 581 of file defBF525.h.
| #define nSTALL_SEND_T 0x0 |
Definition at line 540 of file defBF525.h.
| #define nSTALL_SENT 0x0 |
Definition at line 487 of file defBF525.h.
| #define nSTALL_SENT_R 0x0 |
Definition at line 583 of file defBF525.h.
| #define nSTALL_SENT_T 0x0 |
Definition at line 542 of file defBF525.h.
| #define nSTATUSPKT_H 0x0 |
Definition at line 509 of file defBF525.h.
| #define nSUSPEND_B 0x0 |
Definition at line 355 of file defBF525.h.
| #define nSUSPEND_BE 0x0 |
Definition at line 374 of file defBF525.h.
| #define nSUSPEND_MODE 0x0 |
Definition at line 266 of file defBF525.h.
| #define nTXPKTRDY 0x0 |
Definition at line 485 of file defBF525.h.
| #define nTXPKTRDY_T 0x0 |
Definition at line 532 of file defBF525.h.
| #define nUNDERRUN_T 0x0 |
Definition at line 536 of file defBF525.h.
| #define nVBUS0 0x0 |
Definition at line 440 of file defBF525.h.
| #define nVBUS1 0x0 |
Definition at line 442 of file defBF525.h.
| #define nVBUS_ERROR_B 0x0 |
Definition at line 369 of file defBF525.h.
| #define nVBUS_ERROR_BE 0x0 |
Definition at line 388 of file defBF525.h.
| #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ |
Definition at line 574 of file defBF525.h.
| #define PROTOCOL_R 0xc /* transfer type */ |
Definition at line 627 of file defBF525.h.
| #define PROTOCOL_T 0xc /* transfer type */ |
Definition at line 618 of file defBF525.h.
| #define REQPKT_H 0x20 /* Request an IN transaction host mode */ |
Definition at line 506 of file defBF525.h.
| #define REQPKT_RH 0x20 /* request an IN transaction host mode */ |
Definition at line 600 of file defBF525.h.
| #define RESET 0x8 /* Reset indicator */ |
Definition at line 269 of file defBF525.h.
| #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ |
Definition at line 358 of file defBF525.h.
| #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ |
Definition at line 377 of file defBF525.h.
| #define RESUME_B 0x2 /* Resume indicator */ |
Definition at line 356 of file defBF525.h.
| #define RESUME_BE 0x2 /* Resume indicator int enable */ |
Definition at line 375 of file defBF525.h.
| #define RESUME_MODE 0x4 /* DMA Mode */ |
Definition at line 267 of file defBF525.h.
| #define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ |
Definition at line 613 of file defBF525.h.
| #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ |
Definition at line 631 of file defBF525.h.
| #define RXPKTRDY 0x1 /* data packet receive indicator */ |
Definition at line 482 of file defBF525.h.
| #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ |
Definition at line 570 of file defBF525.h.
| #define SELECTED_ENDPOINT 0xf /* selected endpoint */ |
Definition at line 396 of file defBF525.h.
| #define SENDSTALL 0x20 /* Send STALL handshake */ |
Definition at line 492 of file defBF525.h.
| #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ |
Definition at line 494 of file defBF525.h.
| #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ |
Definition at line 496 of file defBF525.h.
| #define SESSION 0x1 /* session indicator */ |
Definition at line 433 of file defBF525.h.
| #define SESSION_REQ_B 0x40 /* Session Request */ |
Definition at line 366 of file defBF525.h.
| #define SESSION_REQ_BE 0x40 /* Session Request int enable */ |
Definition at line 385 of file defBF525.h.
| #define SETUPEND 0x10 /* Setup end */ |
Definition at line 490 of file defBF525.h.
| #define SETUPPKT_H 0x8 /* send Setup token host mode */ |
Definition at line 502 of file defBF525.h.
| #define SOF_B 0x8 /* Start of frame */ |
Definition at line 360 of file defBF525.h.
| #define SOF_BE 0x8 /* Start of frame int enable */ |
Definition at line 379 of file defBF525.h.
| #define SOFT_CONN 0x40 /* Soft connect */ |
Definition at line 275 of file defBF525.h.
| #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ |
Definition at line 500 of file defBF525.h.
| #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ |
Definition at line 602 of file defBF525.h.
| #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ |
Definition at line 559 of file defBF525.h.
| #define STALL_SEND_R 0x20 /* issue a Stall handshake */ |
Definition at line 580 of file defBF525.h.
| #define STALL_SEND_T 0x10 /* issue a Stall handshake */ |
Definition at line 539 of file defBF525.h.
| #define STALL_SENT 0x4 /* STALL handshake sent */ |
Definition at line 486 of file defBF525.h.
| #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ |
Definition at line 582 of file defBF525.h.
| #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ |
Definition at line 541 of file defBF525.h.
| #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ |
Definition at line 508 of file defBF525.h.
| #define SUSPEND_B 0x1 /* Suspend indicator */ |
Definition at line 354 of file defBF525.h.
| #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ |
Definition at line 373 of file defBF525.h.
| #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ |
Definition at line 265 of file defBF525.h.
| #define TARGET_EP_NO_R 0xf /* EP number */ |
Definition at line 626 of file defBF525.h.
| #define TARGET_EP_NO_T 0xf /* EP number */ |
Definition at line 617 of file defBF525.h.
| #define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ |
Definition at line 566 of file defBF525.h.
| #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ |
Definition at line 622 of file defBF525.h.
| #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ |
Definition at line 484 of file defBF525.h.
| #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ |
Definition at line 531 of file defBF525.h.
| #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ |
Definition at line 535 of file defBF525.h.
| #define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */ |
Definition at line 76 of file defBF525.h.
| #define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */ |
Definition at line 72 of file defBF525.h.
| #define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ |
Definition at line 78 of file defBF525.h.
| #define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ |
Definition at line 36 of file defBF525.h.
| #define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ |
Definition at line 32 of file defBF525.h.
| #define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ |
Definition at line 197 of file defBF525.h.
| #define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ |
Definition at line 196 of file defBF525.h.
| #define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */ |
Definition at line 195 of file defBF525.h.
| #define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ |
Definition at line 199 of file defBF525.h.
| #define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ |
Definition at line 198 of file defBF525.h.
| #define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ |
Definition at line 205 of file defBF525.h.
| #define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ |
Definition at line 204 of file defBF525.h.
| #define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */ |
Definition at line 203 of file defBF525.h.
| #define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ |
Definition at line 207 of file defBF525.h.
| #define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ |
Definition at line 206 of file defBF525.h.
| #define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ |
Definition at line 213 of file defBF525.h.
| #define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ |
Definition at line 212 of file defBF525.h.
| #define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */ |
Definition at line 211 of file defBF525.h.
| #define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ |
Definition at line 215 of file defBF525.h.
| #define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ |
Definition at line 214 of file defBF525.h.
| #define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ |
Definition at line 221 of file defBF525.h.
| #define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ |
Definition at line 220 of file defBF525.h.
| #define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */ |
Definition at line 219 of file defBF525.h.
| #define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ |
Definition at line 223 of file defBF525.h.
| #define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ |
Definition at line 222 of file defBF525.h.
| #define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ |
Definition at line 229 of file defBF525.h.
| #define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ |
Definition at line 228 of file defBF525.h.
| #define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */ |
Definition at line 227 of file defBF525.h.
| #define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ |
Definition at line 231 of file defBF525.h.
| #define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ |
Definition at line 230 of file defBF525.h.
| #define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ |
Definition at line 237 of file defBF525.h.
| #define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ |
Definition at line 236 of file defBF525.h.
| #define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */ |
Definition at line 235 of file defBF525.h.
| #define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ |
Definition at line 239 of file defBF525.h.
| #define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ |
Definition at line 238 of file defBF525.h.
| #define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ |
Definition at line 245 of file defBF525.h.
| #define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ |
Definition at line 244 of file defBF525.h.
| #define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */ |
Definition at line 243 of file defBF525.h.
| #define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ |
Definition at line 247 of file defBF525.h.
| #define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ |
Definition at line 246 of file defBF525.h.
| #define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ |
Definition at line 253 of file defBF525.h.
| #define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ |
Definition at line 252 of file defBF525.h.
| #define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */ |
Definition at line 251 of file defBF525.h.
| #define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ |
Definition at line 255 of file defBF525.h.
| #define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ |
Definition at line 254 of file defBF525.h.
| #define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */ |
Definition at line 191 of file defBF525.h.
| #define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */ |
Definition at line 47 of file defBF525.h.
| #define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */ |
Definition at line 48 of file defBF525.h.
| #define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */ |
Definition at line 49 of file defBF525.h.
| #define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */ |
Definition at line 50 of file defBF525.h.
| #define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */ |
Definition at line 51 of file defBF525.h.
| #define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */ |
Definition at line 52 of file defBF525.h.
| #define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */ |
Definition at line 53 of file defBF525.h.
| #define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */ |
Definition at line 54 of file defBF525.h.
| #define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */ |
Definition at line 93 of file defBF525.h.
| #define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */ |
Definition at line 92 of file defBF525.h.
| #define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ |
Definition at line 97 of file defBF525.h.
| #define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */ |
Definition at line 91 of file defBF525.h.
| #define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ |
Definition at line 96 of file defBF525.h.
| #define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ |
Definition at line 98 of file defBF525.h.
| #define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */ |
Definition at line 90 of file defBF525.h.
| #define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */ |
Definition at line 95 of file defBF525.h.
| #define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */ |
Definition at line 89 of file defBF525.h.
| #define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ |
Definition at line 94 of file defBF525.h.
| #define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */ |
Definition at line 106 of file defBF525.h.
| #define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */ |
Definition at line 105 of file defBF525.h.
| #define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ |
Definition at line 110 of file defBF525.h.
| #define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */ |
Definition at line 104 of file defBF525.h.
| #define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ |
Definition at line 109 of file defBF525.h.
| #define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ |
Definition at line 111 of file defBF525.h.
| #define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */ |
Definition at line 103 of file defBF525.h.
| #define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */ |
Definition at line 108 of file defBF525.h.
| #define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */ |
Definition at line 102 of file defBF525.h.
| #define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ |
Definition at line 107 of file defBF525.h.
| #define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */ |
Definition at line 119 of file defBF525.h.
| #define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */ |
Definition at line 118 of file defBF525.h.
| #define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ |
Definition at line 123 of file defBF525.h.
| #define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */ |
Definition at line 117 of file defBF525.h.
| #define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ |
Definition at line 122 of file defBF525.h.
| #define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ |
Definition at line 124 of file defBF525.h.
| #define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */ |
Definition at line 116 of file defBF525.h.
| #define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */ |
Definition at line 121 of file defBF525.h.
| #define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */ |
Definition at line 115 of file defBF525.h.
| #define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ |
Definition at line 120 of file defBF525.h.
| #define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */ |
Definition at line 132 of file defBF525.h.
| #define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */ |
Definition at line 131 of file defBF525.h.
| #define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ |
Definition at line 136 of file defBF525.h.
| #define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */ |
Definition at line 130 of file defBF525.h.
| #define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ |
Definition at line 135 of file defBF525.h.
| #define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ |
Definition at line 137 of file defBF525.h.
| #define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */ |
Definition at line 129 of file defBF525.h.
| #define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */ |
Definition at line 134 of file defBF525.h.
| #define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */ |
Definition at line 128 of file defBF525.h.
| #define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ |
Definition at line 133 of file defBF525.h.
| #define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */ |
Definition at line 145 of file defBF525.h.
| #define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */ |
Definition at line 144 of file defBF525.h.
| #define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ |
Definition at line 149 of file defBF525.h.
| #define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */ |
Definition at line 143 of file defBF525.h.
| #define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ |
Definition at line 148 of file defBF525.h.
| #define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ |
Definition at line 150 of file defBF525.h.
| #define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */ |
Definition at line 142 of file defBF525.h.
| #define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */ |
Definition at line 147 of file defBF525.h.
| #define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */ |
Definition at line 141 of file defBF525.h.
| #define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ |
Definition at line 146 of file defBF525.h.
| #define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */ |
Definition at line 158 of file defBF525.h.
| #define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */ |
Definition at line 157 of file defBF525.h.
| #define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ |
Definition at line 162 of file defBF525.h.
| #define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */ |
Definition at line 156 of file defBF525.h.
| #define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ |
Definition at line 161 of file defBF525.h.
| #define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ |
Definition at line 163 of file defBF525.h.
| #define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */ |
Definition at line 155 of file defBF525.h.
| #define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */ |
Definition at line 160 of file defBF525.h.
| #define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */ |
Definition at line 154 of file defBF525.h.
| #define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ |
Definition at line 159 of file defBF525.h.
| #define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */ |
Definition at line 171 of file defBF525.h.
| #define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */ |
Definition at line 170 of file defBF525.h.
| #define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ |
Definition at line 175 of file defBF525.h.
| #define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */ |
Definition at line 169 of file defBF525.h.
| #define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ |
Definition at line 174 of file defBF525.h.
| #define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ |
Definition at line 176 of file defBF525.h.
| #define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */ |
Definition at line 168 of file defBF525.h.
| #define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */ |
Definition at line 173 of file defBF525.h.
| #define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */ |
Definition at line 167 of file defBF525.h.
| #define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ |
Definition at line 172 of file defBF525.h.
| #define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */ |
Definition at line 184 of file defBF525.h.
| #define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */ |
Definition at line 183 of file defBF525.h.
| #define USB_EP_NI7_RXINTERVAL 0xffc03be0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ |
Definition at line 188 of file defBF525.h.
| #define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */ |
Definition at line 182 of file defBF525.h.
| #define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ |
Definition at line 187 of file defBF525.h.
| #define USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ |
Definition at line 189 of file defBF525.h.
| #define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */ |
Definition at line 181 of file defBF525.h.
| #define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */ |
Definition at line 186 of file defBF525.h.
| #define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */ |
Definition at line 180 of file defBF525.h.
| #define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ |
Definition at line 185 of file defBF525.h.
| #define USB_FADDR 0xffc03800 /* Function address register */ |
Definition at line 15 of file defBF525.h.
| #define USB_FRAME 0xffc03820 /* USB frame number */ |
Definition at line 23 of file defBF525.h.
| #define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */ |
Definition at line 67 of file defBF525.h.
| #define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */ |
Definition at line 27 of file defBF525.h.
| #define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ |
Definition at line 26 of file defBF525.h.
| #define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */ |
Definition at line 66 of file defBF525.h.
| #define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */ |
Definition at line 24 of file defBF525.h.
| #define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */ |
Definition at line 18 of file defBF525.h.
| #define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */ |
Definition at line 20 of file defBF525.h.
| #define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ |
Definition at line 17 of file defBF525.h.
| #define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */ |
Definition at line 19 of file defBF525.h.
| #define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */ |
Definition at line 21 of file defBF525.h.
| #define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */ |
Definition at line 22 of file defBF525.h.
| #define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */ |
Definition at line 64 of file defBF525.h.
| #define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */ |
Definition at line 68 of file defBF525.h.
| #define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ |
Definition at line 39 of file defBF525.h.
| #define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */ |
Definition at line 58 of file defBF525.h.
| #define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */ |
Definition at line 59 of file defBF525.h.
| #define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */ |
Definition at line 60 of file defBF525.h.
| #define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */ |
Definition at line 82 of file defBF525.h.
| #define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */ |
Definition at line 84 of file defBF525.h.
| #define USB_POWER 0xffc03804 /* Power management register */ |
Definition at line 16 of file defBF525.h.
| #define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */ |
Definition at line 34 of file defBF525.h.
| #define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ |
Definition at line 37 of file defBF525.h.
| #define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */ |
Definition at line 35 of file defBF525.h.
| #define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ |
Definition at line 42 of file defBF525.h.
| #define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ |
Definition at line 41 of file defBF525.h.
| #define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ |
Definition at line 85 of file defBF525.h.
| #define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */ |
Definition at line 25 of file defBF525.h.
| #define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */ |
Definition at line 31 of file defBF525.h.
| #define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ |
Definition at line 43 of file defBF525.h.
| #define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ |
Definition at line 33 of file defBF525.h.
| #define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ |
Definition at line 40 of file defBF525.h.
| #define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ |
Definition at line 38 of file defBF525.h.
| #define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */ |
Definition at line 65 of file defBF525.h.
| #define VBUS0 0x8 /* Vbus level indicator[0] */ |
Definition at line 439 of file defBF525.h.
| #define VBUS1 0x10 /* Vbus level indicator[1] */ |
Definition at line 441 of file defBF525.h.
| #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ |
Definition at line 368 of file defBF525.h.
| #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ |
Definition at line 387 of file defBF525.h.
1.8.2