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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | PLL_CTL 0xFFC00000 /* PLL Control Register */ |
| #define | PLL_DIV 0xFFC00004 /* PLL Divide Register */ |
| #define | VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ |
| #define | PLL_STAT 0xFFC0000C /* PLL Status Register */ |
| #define | PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ |
| #define | CHIPID 0xFFC00014 /* Chip ID Register */ |
| #define | SWRST 0xFFC00100 /* Software Reset Register */ |
| #define | SYSCR 0xFFC00104 /* System Configuration Register */ |
| #define | SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ |
| #define | SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ |
| #define | SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ |
| #define | SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ |
| #define | SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ |
| #define | SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ |
| #define | SIC_ISR 0xFFC00120 /* Interrupt Status Register */ |
| #define | SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ |
| #define | WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ |
| #define | WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ |
| #define | WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ |
| #define | RTC_STAT 0xFFC00300 /* RTC Status Register */ |
| #define | RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ |
| #define | RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ |
| #define | RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ |
| #define | RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ |
| #define | RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ |
| #define | RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ |
| #define | UART0_THR 0xFFC00400 /* Transmit Holding register */ |
| #define | UART0_RBR 0xFFC00400 /* Receive Buffer register */ |
| #define | UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ |
| #define | UART0_IER 0xFFC00404 /* Interrupt Enable Register */ |
| #define | UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ |
| #define | UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ |
| #define | UART0_LCR 0xFFC0040C /* Line Control Register */ |
| #define | UART0_MCR 0xFFC00410 /* Modem Control Register */ |
| #define | UART0_LSR 0xFFC00414 /* Line Status Register */ |
| #define | UART0_MSR 0xFFC00418 /* Modem Status Register */ |
| #define | UART0_SCR 0xFFC0041C /* SCR Scratch Register */ |
| #define | UART0_GCTL 0xFFC00424 /* Global Control Register */ |
| #define | SPI0_REGBASE 0xFFC00500 |
| #define | SPI_CTL 0xFFC00500 /* SPI Control Register */ |
| #define | SPI_FLG 0xFFC00504 /* SPI Flag register */ |
| #define | SPI_STAT 0xFFC00508 /* SPI Status register */ |
| #define | SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ |
| #define | SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ |
| #define | SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ |
| #define | SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ |
| #define | TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ |
| #define | TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ |
| #define | TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ |
| #define | TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ |
| #define | TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ |
| #define | TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ |
| #define | TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ |
| #define | TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ |
| #define | TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ |
| #define | TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ |
| #define | TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ |
| #define | TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ |
| #define | TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ |
| #define | TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ |
| #define | TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ |
| #define | TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ |
| #define | TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ |
| #define | TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ |
| #define | TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ |
| #define | TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ |
| #define | TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ |
| #define | TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ |
| #define | TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ |
| #define | TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ |
| #define | TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ |
| #define | TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ |
| #define | TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ |
| #define | TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ |
| #define | TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ |
| #define | TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ |
| #define | TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ |
| #define | TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ |
| #define | TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ |
| #define | TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ |
| #define | TIMER_STATUS 0xFFC00688 /* Timer Status Register */ |
| #define | PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ |
| #define | PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ |
| #define | PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ |
| #define | PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ |
| #define | PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ |
| #define | PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ |
| #define | PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ |
| #define | PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ |
| #define | PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ |
| #define | PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ |
| #define | PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ |
| #define | PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ |
| #define | PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ |
| #define | PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ |
| #define | PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ |
| #define | PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ |
| #define | PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ |
| #define | SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ |
| #define | SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ |
| #define | SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ |
| #define | SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ |
| #define | SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ |
| #define | SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ |
| #define | SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ |
| #define | SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ |
| #define | SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ |
| #define | SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ |
| #define | SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ |
| #define | SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ |
| #define | SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ |
| #define | SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ |
| #define | SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ |
| #define | SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ |
| #define | SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ |
| #define | SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ |
| #define | SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ |
| #define | SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ |
| #define | SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ |
| #define | SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ |
| #define | SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ |
| #define | SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ |
| #define | SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ |
| #define | SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ |
| #define | SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ |
| #define | SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ |
| #define | SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ |
| #define | SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ |
| #define | SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ |
| #define | SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ |
| #define | SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ |
| #define | SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ |
| #define | SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ |
| #define | SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ |
| #define | SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ |
| #define | SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ |
| #define | SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ |
| #define | SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ |
| #define | SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ |
| #define | SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ |
| #define | SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ |
| #define | SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ |
| #define | EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ |
| #define | EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ |
| #define | EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ |
| #define | EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ |
| #define | EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ |
| #define | EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ |
| #define | EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ |
| #define | DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ |
| #define | DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ |
| #define | DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ |
| #define | DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ |
| #define | DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ |
| #define | DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ |
| #define | DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ |
| #define | DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ |
| #define | DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ |
| #define | DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ |
| #define | DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ |
| #define | DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ |
| #define | DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ |
| #define | DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ |
| #define | DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ |
| #define | DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ |
| #define | DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ |
| #define | DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ |
| #define | DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ |
| #define | DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ |
| #define | DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ |
| #define | DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ |
| #define | DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ |
| #define | DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ |
| #define | DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ |
| #define | DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ |
| #define | DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ |
| #define | DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ |
| #define | DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ |
| #define | DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ |
| #define | DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ |
| #define | DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ |
| #define | DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ |
| #define | DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ |
| #define | DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ |
| #define | DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ |
| #define | DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ |
| #define | DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ |
| #define | DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ |
| #define | DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ |
| #define | DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ |
| #define | DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ |
| #define | DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ |
| #define | DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ |
| #define | DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ |
| #define | DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ |
| #define | DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ |
| #define | DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ |
| #define | DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ |
| #define | DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ |
| #define | DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ |
| #define | DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ |
| #define | DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ |
| #define | DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ |
| #define | DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ |
| #define | DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ |
| #define | DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ |
| #define | DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ |
| #define | DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ |
| #define | DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ |
| #define | DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ |
| #define | DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ |
| #define | DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ |
| #define | DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ |
| #define | DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ |
| #define | DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ |
| #define | DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ |
| #define | DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ |
| #define | DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ |
| #define | DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ |
| #define | DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ |
| #define | DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ |
| #define | DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ |
| #define | DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ |
| #define | DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ |
| #define | DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ |
| #define | DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ |
| #define | DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ |
| #define | DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ |
| #define | DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ |
| #define | DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ |
| #define | DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ |
| #define | DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ |
| #define | DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ |
| #define | DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ |
| #define | DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ |
| #define | DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ |
| #define | DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ |
| #define | DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ |
| #define | DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ |
| #define | DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ |
| #define | DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ |
| #define | DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ |
| #define | DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ |
| #define | DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ |
| #define | DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ |
| #define | DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ |
| #define | DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ |
| #define | DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ |
| #define | DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ |
| #define | DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ |
| #define | DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ |
| #define | DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ |
| #define | DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ |
| #define | DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ |
| #define | DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ |
| #define | DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ |
| #define | DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ |
| #define | DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ |
| #define | DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ |
| #define | DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ |
| #define | DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ |
| #define | DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ |
| #define | DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ |
| #define | DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ |
| #define | DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ |
| #define | DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ |
| #define | DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ |
| #define | DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ |
| #define | DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ |
| #define | DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ |
| #define | DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ |
| #define | DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ |
| #define | DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ |
| #define | DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ |
| #define | DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ |
| #define | DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ |
| #define | DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ |
| #define | DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ |
| #define | DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ |
| #define | DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ |
| #define | DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ |
| #define | DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ |
| #define | DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ |
| #define | DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ |
| #define | DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ |
| #define | DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ |
| #define | DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ |
| #define | DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ |
| #define | DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ |
| #define | DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ |
| #define | DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ |
| #define | DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ |
| #define | DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ |
| #define | DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ |
| #define | DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ |
| #define | DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ |
| #define | DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ |
| #define | DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ |
| #define | DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ |
| #define | DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ |
| #define | DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ |
| #define | DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ |
| #define | DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ |
| #define | DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ |
| #define | DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ |
| #define | DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ |
| #define | DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ |
| #define | MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ |
| #define | MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ |
| #define | MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ |
| #define | MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ |
| #define | MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ |
| #define | MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ |
| #define | MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ |
| #define | MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ |
| #define | MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ |
| #define | MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ |
| #define | MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ |
| #define | MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ |
| #define | MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ |
| #define | MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ |
| #define | MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ |
| #define | MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ |
| #define | MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ |
| #define | MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ |
| #define | MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ |
| #define | MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ |
| #define | MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ |
| #define | MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ |
| #define | MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ |
| #define | MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ |
| #define | MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ |
| #define | MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ |
| #define | MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ |
| #define | MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ |
| #define | MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ |
| #define | MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ |
| #define | MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ |
| #define | MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ |
| #define | MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ |
| #define | MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ |
| #define | MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ |
| #define | MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ |
| #define | MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ |
| #define | MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ |
| #define | MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ |
| #define | MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ |
| #define | MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ |
| #define | MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ |
| #define | MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ |
| #define | MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ |
| #define | MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ |
| #define | MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ |
| #define | MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ |
| #define | MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ |
| #define | MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ |
| #define | MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ |
| #define | MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ |
| #define | MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ |
| #define | PPI_CONTROL 0xFFC01000 /* PPI Control Register */ |
| #define | PPI_STATUS 0xFFC01004 /* PPI Status Register */ |
| #define | PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ |
| #define | PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ |
| #define | PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ |
| #define | TWI0_REGBASE 0xFFC01400 |
| #define | TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
| #define | TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ |
| #define | TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ |
| #define | TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ |
| #define | TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ |
| #define | TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ |
| #define | TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ |
| #define | TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ |
| #define | TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ |
| #define | TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ |
| #define | TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ |
| #define | TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ |
| #define | TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ |
| #define | TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ |
| #define | TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ |
| #define | TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ |
| #define | PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ |
| #define | PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ |
| #define | PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ |
| #define | PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ |
| #define | PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ |
| #define | PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ |
| #define | PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ |
| #define | PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ |
| #define | PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ |
| #define | PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ |
| #define | PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ |
| #define | PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ |
| #define | PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ |
| #define | PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ |
| #define | PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ |
| #define | PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ |
| #define | PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ |
| #define | PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ |
| #define | PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ |
| #define | PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ |
| #define | PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ |
| #define | PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ |
| #define | PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ |
| #define | PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ |
| #define | PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ |
| #define | PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ |
| #define | PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ |
| #define | PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ |
| #define | PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ |
| #define | PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ |
| #define | PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ |
| #define | PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ |
| #define | PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ |
| #define | PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ |
| #define | UART1_THR 0xFFC02000 /* Transmit Holding register */ |
| #define | UART1_RBR 0xFFC02000 /* Receive Buffer register */ |
| #define | UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ |
| #define | UART1_IER 0xFFC02004 /* Interrupt Enable Register */ |
| #define | UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ |
| #define | UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ |
| #define | UART1_LCR 0xFFC0200C /* Line Control Register */ |
| #define | UART1_MCR 0xFFC02010 /* Modem Control Register */ |
| #define | UART1_LSR 0xFFC02014 /* Line Status Register */ |
| #define | UART1_MSR 0xFFC02018 /* Modem Status Register */ |
| #define | UART1_SCR 0xFFC0201C /* SCR Scratch Register */ |
| #define | UART1_GCTL 0xFFC02024 /* Global Control Register */ |
| #define | CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ |
| #define | CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ |
| #define | CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ |
| #define | CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ |
| #define | CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ |
| #define | CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ |
| #define | CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ |
| #define | CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ |
| #define | CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ |
| #define | CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ |
| #define | CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ |
| #define | CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ |
| #define | CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */ |
| #define | CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ |
| #define | CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ |
| #define | CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ |
| #define | CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ |
| #define | CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ |
| #define | CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ |
| #define | CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ |
| #define | CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ |
| #define | CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ |
| #define | CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ |
| #define | CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ |
| #define | CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ |
| #define | CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */ |
| #define | CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ |
| #define | CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ |
| #define | CAN_DEBUG 0xFFC02A88 /* Debug Register */ |
| #define | CAN_STATUS 0xFFC02A8C /* Global Status Register */ |
| #define | CAN_CEC 0xFFC02A90 /* Error Counter Register */ |
| #define | CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ |
| #define | CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ |
| #define | CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ |
| #define | CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ |
| #define | CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ |
| #define | CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ |
| #define | CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ |
| #define | CAN_ESR 0xFFC02AB4 /* Error Status Register */ |
| #define | CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */ |
| #define | CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ |
| #define | CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */ |
| #define | CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ |
| #define | CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ |
| #define | CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ |
| #define | CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ |
| #define | CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ |
| #define | CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ |
| #define | CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ |
| #define | CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ |
| #define | CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ |
| #define | CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ |
| #define | CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ |
| #define | CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ |
| #define | CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ |
| #define | CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ |
| #define | CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ |
| #define | CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ |
| #define | CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ |
| #define | CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ |
| #define | CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ |
| #define | CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ |
| #define | CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ |
| #define | CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ |
| #define | CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ |
| #define | CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ |
| #define | CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ |
| #define | CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ |
| #define | CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ |
| #define | CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ |
| #define | CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ |
| #define | CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ |
| #define | CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ |
| #define | CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ |
| #define | CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ |
| #define | CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ |
| #define | CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ |
| #define | CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ |
| #define | CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ |
| #define | CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ |
| #define | CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ |
| #define | CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ |
| #define | CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ |
| #define | CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ |
| #define | CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ |
| #define | CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ |
| #define | CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ |
| #define | CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ |
| #define | CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ |
| #define | CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ |
| #define | CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ |
| #define | CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ |
| #define | CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ |
| #define | CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ |
| #define | CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ |
| #define | CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ |
| #define | CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ |
| #define | CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ |
| #define | CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ |
| #define | CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ |
| #define | CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ |
| #define | CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ |
| #define | CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ |
| #define | CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ |
| #define | CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ |
| #define | CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ |
| #define | CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ |
| #define | CAN_AM_L(x) (CAN_AM00L+((x)*0x8)) |
| #define | CAN_AM_H(x) (CAN_AM00H+((x)*0x8)) |
| #define | CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ |
| #define | CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ |
| #define | CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ |
| #define | CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ |
| #define | CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ |
| #define | CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ |
| #define | CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ |
| #define | CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ |
| #define | CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ |
| #define | CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ |
| #define | CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ |
| #define | CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ |
| #define | CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ |
| #define | CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ |
| #define | CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ |
| #define | CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ |
| #define | CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ |
| #define | CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ |
| #define | CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ |
| #define | CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ |
| #define | CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ |
| #define | CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ |
| #define | CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ |
| #define | CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ |
| #define | CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ |
| #define | CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ |
| #define | CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ |
| #define | CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ |
| #define | CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ |
| #define | CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ |
| #define | CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ |
| #define | CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ |
| #define | CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ |
| #define | CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ |
| #define | CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ |
| #define | CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ |
| #define | CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ |
| #define | CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ |
| #define | CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ |
| #define | CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ |
| #define | CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ |
| #define | CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ |
| #define | CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ |
| #define | CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ |
| #define | CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ |
| #define | CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ |
| #define | CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ |
| #define | CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ |
| #define | CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ |
| #define | CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ |
| #define | CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ |
| #define | CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ |
| #define | CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ |
| #define | CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ |
| #define | CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ |
| #define | CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ |
| #define | CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ |
| #define | CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ |
| #define | CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ |
| #define | CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ |
| #define | CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ |
| #define | CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ |
| #define | CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ |
| #define | CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ |
| #define | CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ |
| #define | CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ |
| #define | CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ |
| #define | CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ |
| #define | CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ |
| #define | CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ |
| #define | CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ |
| #define | CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ |
| #define | CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ |
| #define | CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ |
| #define | CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ |
| #define | CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ |
| #define | CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ |
| #define | CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ |
| #define | CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ |
| #define | CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ |
| #define | CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ |
| #define | CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ |
| #define | CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ |
| #define | CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ |
| #define | CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ |
| #define | CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ |
| #define | CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ |
| #define | CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ |
| #define | CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ |
| #define | CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ |
| #define | CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ |
| #define | CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ |
| #define | CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ |
| #define | CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ |
| #define | CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ |
| #define | CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ |
| #define | CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ |
| #define | CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ |
| #define | CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ |
| #define | CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ |
| #define | CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ |
| #define | CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ |
| #define | CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ |
| #define | CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ |
| #define | CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ |
| #define | CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ |
| #define | CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ |
| #define | CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ |
| #define | CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ |
| #define | CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ |
| #define | CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ |
| #define | CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ |
| #define | CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ |
| #define | CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ |
| #define | CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ |
| #define | CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ |
| #define | CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ |
| #define | CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ |
| #define | CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ |
| #define | CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ |
| #define | CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ |
| #define | CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ |
| #define | CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ |
| #define | CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ |
| #define | CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ |
| #define | CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ |
| #define | CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ |
| #define | CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ |
| #define | CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ |
| #define | CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ |
| #define | CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ |
| #define | CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ |
| #define | CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ |
| #define | CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ |
| #define | CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ |
| #define | CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ |
| #define | CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ |
| #define | CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ |
| #define | CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ |
| #define | CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ |
| #define | CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ |
| #define | CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ |
| #define | CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ |
| #define | CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ |
| #define | CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ |
| #define | CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ |
| #define | CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ |
| #define | CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ |
| #define | CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ |
| #define | CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ |
| #define | CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ |
| #define | CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ |
| #define | CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ |
| #define | CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ |
| #define | CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ |
| #define | CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ |
| #define | CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ |
| #define | CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ |
| #define | CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ |
| #define | CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ |
| #define | CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ |
| #define | CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ |
| #define | CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ |
| #define | CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ |
| #define | CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ |
| #define | CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ |
| #define | CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ |
| #define | CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ |
| #define | CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ |
| #define | CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ |
| #define | CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ |
| #define | CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ |
| #define | CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ |
| #define | CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ |
| #define | CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ |
| #define | CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ |
| #define | CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ |
| #define | CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ |
| #define | CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ |
| #define | CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ |
| #define | CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ |
| #define | CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ |
| #define | CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ |
| #define | CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ |
| #define | CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ |
| #define | CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ |
| #define | CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ |
| #define | CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ |
| #define | CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ |
| #define | CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ |
| #define | CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ |
| #define | CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ |
| #define | CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ |
| #define | CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ |
| #define | CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ |
| #define | CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ |
| #define | CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ |
| #define | CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ |
| #define | CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ |
| #define | CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ |
| #define | CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ |
| #define | CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ |
| #define | CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ |
| #define | CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ |
| #define | CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ |
| #define | CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ |
| #define | CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ |
| #define | CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ |
| #define | CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ |
| #define | CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ |
| #define | CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ |
| #define | CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ |
| #define | CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ |
| #define | CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ |
| #define | CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ |
| #define | CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ |
| #define | CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ |
| #define | CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ |
| #define | CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ |
| #define | CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ |
| #define | CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ |
| #define | CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ |
| #define | CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ |
| #define | CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ |
| #define | CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ |
| #define | CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ |
| #define | CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ |
| #define | CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ |
| #define | CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ |
| #define | CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ |
| #define | CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ |
| #define | CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ |
| #define | CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ |
| #define | CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ |
| #define | CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ |
| #define | CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ |
| #define | CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ |
| #define | CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ |
| #define | CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ |
| #define | CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ |
| #define | CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ |
| #define | CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ |
| #define | CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ |
| #define | CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ |
| #define | CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ |
| #define | CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ |
| #define | CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ |
| #define | CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ |
| #define | CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ |
| #define | CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ |
| #define | CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ |
| #define | CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ |
| #define | CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ |
| #define | CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ |
| #define | CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ |
| #define | CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ |
| #define | CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20)) |
| #define | CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20)) |
| #define | CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20)) |
| #define | CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20)) |
| #define | CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20)) |
| #define | CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20)) |
| #define | CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20)) |
| #define | CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20)) |
| #define | PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ |
| #define | PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ |
| #define | PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ |
| #define | BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ |
| #define | HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ |
| #define | HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ |
| #define | HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ |
| #define | HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */ |
| #define | HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ |
| #define | HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ |
| #define | HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ |
| #define | HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ |
| #define | HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ |
| #define | HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ |
| #define | HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */ |
| #define | HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ |
| #define | HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ |
| #define | HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ |
| #define | CHIPID_VERSION 0xF0000000 |
| #define | CHIPID_FAMILY 0x0FFFF000 |
| #define | CHIPID_MANUFACTURE 0x00000FFE |
| #define | SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ |
| #define | DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ |
| #define | RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ |
| #define | RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ |
| #define | RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ |
| #define | BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ |
| #define | NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ |
| #define | P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ |
| #define | P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ |
| #define | P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ |
| #define | P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ |
| #define | P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ |
| #define | P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ |
| #define | P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ |
| #define | P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ |
| #define | P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ |
| #define | P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ |
| #define | P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ |
| #define | P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ |
| #define | P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ |
| #define | P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ |
| #define | P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ |
| #define | P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ |
| #define | P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ |
| #define | P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ |
| #define | P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ |
| #define | P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ |
| #define | P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ |
| #define | P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ |
| #define | P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ |
| #define | P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ |
| #define | P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ |
| #define | P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ |
| #define | P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ |
| #define | P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ |
| #define | P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ |
| #define | P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ |
| #define | P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ |
| #define | P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ |
| #define | SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ |
| #define | SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ |
| #define | SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ |
| #define | SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ |
| #define | IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ |
| #define | IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ |
| #define | IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ |
| #define | IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ |
| #define | TIMEN0 0x0001 /* Enable Timer 0 */ |
| #define | TIMEN1 0x0002 /* Enable Timer 1 */ |
| #define | TIMEN2 0x0004 /* Enable Timer 2 */ |
| #define | TIMEN3 0x0008 /* Enable Timer 3 */ |
| #define | TIMEN4 0x0010 /* Enable Timer 4 */ |
| #define | TIMEN5 0x0020 /* Enable Timer 5 */ |
| #define | TIMEN6 0x0040 /* Enable Timer 6 */ |
| #define | TIMEN7 0x0080 /* Enable Timer 7 */ |
| #define | TIMDIS0 TIMEN0 /* Disable Timer 0 */ |
| #define | TIMDIS1 TIMEN1 /* Disable Timer 1 */ |
| #define | TIMDIS2 TIMEN2 /* Disable Timer 2 */ |
| #define | TIMDIS3 TIMEN3 /* Disable Timer 3 */ |
| #define | TIMDIS4 TIMEN4 /* Disable Timer 4 */ |
| #define | TIMDIS5 TIMEN5 /* Disable Timer 5 */ |
| #define | TIMDIS6 TIMEN6 /* Disable Timer 6 */ |
| #define | TIMDIS7 TIMEN7 /* Disable Timer 7 */ |
| #define | TIMIL0 0x00000001 /* Timer 0 Interrupt */ |
| #define | TIMIL1 0x00000002 /* Timer 1 Interrupt */ |
| #define | TIMIL2 0x00000004 /* Timer 2 Interrupt */ |
| #define | TIMIL3 0x00000008 /* Timer 3 Interrupt */ |
| #define | TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ |
| #define | TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ |
| #define | TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ |
| #define | TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ |
| #define | TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ |
| #define | TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ |
| #define | TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ |
| #define | TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ |
| #define | TIMIL4 0x00010000 /* Timer 4 Interrupt */ |
| #define | TIMIL5 0x00020000 /* Timer 5 Interrupt */ |
| #define | TIMIL6 0x00040000 /* Timer 6 Interrupt */ |
| #define | TIMIL7 0x00080000 /* Timer 7 Interrupt */ |
| #define | TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ |
| #define | TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ |
| #define | TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ |
| #define | TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ |
| #define | TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ |
| #define | TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ |
| #define | TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ |
| #define | TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ |
| #define | TOVL_ERR0 TOVF_ERR0 |
| #define | TOVL_ERR1 TOVF_ERR1 |
| #define | TOVL_ERR2 TOVF_ERR2 |
| #define | TOVL_ERR3 TOVF_ERR3 |
| #define | TOVL_ERR4 TOVF_ERR4 |
| #define | TOVL_ERR5 TOVF_ERR5 |
| #define | TOVL_ERR6 TOVF_ERR6 |
| #define | TOVL_ERR7 TOVF_ERR7 |
| #define | PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ |
| #define | WDTH_CAP 0x0002 /* Width Capture Input Mode */ |
| #define | EXT_CLK 0x0003 /* External Clock Mode */ |
| #define | PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ |
| #define | PERIOD_CNT 0x0008 /* Period Count */ |
| #define | IRQ_ENA 0x0010 /* Interrupt Request Enable */ |
| #define | TIN_SEL 0x0020 /* Timer Input Select */ |
| #define | OUT_DIS 0x0040 /* Output Pad Disable */ |
| #define | CLK_SEL 0x0080 /* Timer Clock Select */ |
| #define | TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ |
| #define | EMU_RUN 0x0200 /* Emulation Behavior Select */ |
| #define | ERR_TYP 0xC000 /* Error Type */ |
| #define | AMCKEN 0x0001 /* Enable CLKOUT */ |
| #define | AMBEN_NONE 0x0000 /* All Banks Disabled */ |
| #define | AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ |
| #define | AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ |
| #define | AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ |
| #define | AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ |
| #define | B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ |
| #define | B0RDYPOL 0x00000002 /* B0 RDY Active High */ |
| #define | B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ |
| #define | B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ |
| #define | B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ |
| #define | B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ |
| #define | B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ |
| #define | B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ |
| #define | B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ |
| #define | B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ |
| #define | B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ |
| #define | B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ |
| #define | B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ |
| #define | B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ |
| #define | B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ |
| #define | B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ |
| #define | B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ |
| #define | B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ |
| #define | B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ |
| #define | B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ |
| #define | B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ |
| #define | B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ |
| #define | B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ |
| #define | B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ |
| #define | B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ |
| #define | B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ |
| #define | B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ |
| #define | B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ |
| #define | B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ |
| #define | B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ |
| #define | B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ |
| #define | B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ |
| #define | B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ |
| #define | B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ |
| #define | B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ |
| #define | B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ |
| #define | B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ |
| #define | B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ |
| #define | B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ |
| #define | B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ |
| #define | B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ |
| #define | B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ |
| #define | B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ |
| #define | B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ |
| #define | B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ |
| #define | B1RDYPOL 0x00020000 /* B1 RDY Active High */ |
| #define | B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ |
| #define | B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ |
| #define | B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ |
| #define | B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ |
| #define | B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ |
| #define | B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ |
| #define | B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ |
| #define | B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ |
| #define | B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ |
| #define | B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ |
| #define | B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ |
| #define | B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ |
| #define | B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ |
| #define | B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ |
| #define | B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ |
| #define | B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ |
| #define | B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ |
| #define | B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ |
| #define | B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ |
| #define | B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ |
| #define | B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ |
| #define | B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ |
| #define | B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ |
| #define | B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ |
| #define | B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ |
| #define | B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ |
| #define | B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ |
| #define | B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ |
| #define | B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ |
| #define | B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ |
| #define | B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ |
| #define | B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ |
| #define | B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ |
| #define | B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ |
| #define | B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ |
| #define | B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ |
| #define | B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ |
| #define | B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ |
| #define | B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ |
| #define | B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ |
| #define | B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ |
| #define | B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ |
| #define | B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ |
| #define | B2RDYPOL 0x00000002 /* B2 RDY Active High */ |
| #define | B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ |
| #define | B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ |
| #define | B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ |
| #define | B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ |
| #define | B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ |
| #define | B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ |
| #define | B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ |
| #define | B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ |
| #define | B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ |
| #define | B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ |
| #define | B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ |
| #define | B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ |
| #define | B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ |
| #define | B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ |
| #define | B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ |
| #define | B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ |
| #define | B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ |
| #define | B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ |
| #define | B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ |
| #define | B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ |
| #define | B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ |
| #define | B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ |
| #define | B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ |
| #define | B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ |
| #define | B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ |
| #define | B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ |
| #define | B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ |
| #define | B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ |
| #define | B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ |
| #define | B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ |
| #define | B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ |
| #define | B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ |
| #define | B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ |
| #define | B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ |
| #define | B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ |
| #define | B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ |
| #define | B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ |
| #define | B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ |
| #define | B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ |
| #define | B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ |
| #define | B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ |
| #define | B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ |
| #define | B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ |
| #define | B3RDYPOL 0x00020000 /* B3 RDY Active High */ |
| #define | B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ |
| #define | B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ |
| #define | B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ |
| #define | B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ |
| #define | B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ |
| #define | B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ |
| #define | B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ |
| #define | B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ |
| #define | B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ |
| #define | B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ |
| #define | B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ |
| #define | B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ |
| #define | B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ |
| #define | B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ |
| #define | B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ |
| #define | B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ |
| #define | B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ |
| #define | B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ |
| #define | B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ |
| #define | B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ |
| #define | B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ |
| #define | B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ |
| #define | B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ |
| #define | B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ |
| #define | B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ |
| #define | B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ |
| #define | B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ |
| #define | B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ |
| #define | B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ |
| #define | B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ |
| #define | B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ |
| #define | B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ |
| #define | B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ |
| #define | B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ |
| #define | B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ |
| #define | B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ |
| #define | B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ |
| #define | B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ |
| #define | B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ |
| #define | B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ |
| #define | B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ |
| #define | B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ |
| #define | SCTLE 0x00000001 /* Enable SDRAM Signals */ |
| #define | CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ |
| #define | CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ |
| #define | PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ |
| #define | PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ |
| #define | PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ |
| #define | TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ |
| #define | TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ |
| #define | TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ |
| #define | TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ |
| #define | TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ |
| #define | TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ |
| #define | TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ |
| #define | TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ |
| #define | TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ |
| #define | TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ |
| #define | TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ |
| #define | TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ |
| #define | TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ |
| #define | TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ |
| #define | TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ |
| #define | TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ |
| #define | TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ |
| #define | TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ |
| #define | TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ |
| #define | TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ |
| #define | TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ |
| #define | TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ |
| #define | TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ |
| #define | TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ |
| #define | TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ |
| #define | TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ |
| #define | TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ |
| #define | TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ |
| #define | TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ |
| #define | TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ |
| #define | TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ |
| #define | TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ |
| #define | PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ |
| #define | PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ |
| #define | PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ |
| #define | SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ |
| #define | EBUFE 0x02000000 /* Enable External Buffering Timing */ |
| #define | FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ |
| #define | EMREN 0x10000000 /* Extended Mode Register Enable */ |
| #define | TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ |
| #define | CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ |
| #define | EBE 0x0001 /* Enable SDRAM External Bank */ |
| #define | EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ |
| #define | EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ |
| #define | EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ |
| #define | EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ |
| #define | EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ |
| #define | EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ |
| #define | EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ |
| #define | EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ |
| #define | EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ |
| #define | EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ |
| #define | SDCI 0x0001 /* SDRAM Controller Idle */ |
| #define | SDSRA 0x0002 /* SDRAM Self-Refresh Active */ |
| #define | SDPUA 0x0004 /* SDRAM Power-Up Active */ |
| #define | SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ |
| #define | SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ |
| #define | BGSTAT 0x0020 /* Bus Grant Status */ |
| #define | CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ |
| #define | PMAP 0xF000 /* Peripheral Mapped To This Channel */ |
| #define | PMAP_PPI 0x0000 /* PPI Port DMA */ |
| #define | PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ |
| #define | PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ |
| #define | PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ |
| #define | PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ |
| #define | PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ |
| #define | PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ |
| #define | PMAP_SPI 0x7000 /* SPI Port DMA */ |
| #define | PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ |
| #define | PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ |
| #define | PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ |
| #define | PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ |
| #define | PORT_EN 0x0001 /* PPI Port Enable */ |
| #define | PORT_DIR 0x0002 /* PPI Port Direction */ |
| #define | XFR_TYPE 0x000C /* PPI Transfer Type */ |
| #define | PORT_CFG 0x0030 /* PPI Port Configuration */ |
| #define | FLD_SEL 0x0040 /* PPI Active Field Select */ |
| #define | PACK_EN 0x0080 /* PPI Packing Mode */ |
| #define | DMA32 0x0100 /* PPI 32-bit DMA Enable */ |
| #define | SKIP_EN 0x0200 /* PPI Skip Element Enable */ |
| #define | SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ |
| #define | DLENGTH 0x3800 /* PPI Data Length */ |
| #define | DLEN_8 0x0000 /* Data Length = 8 Bits */ |
| #define | DLEN_10 0x0800 /* Data Length = 10 Bits */ |
| #define | DLEN_11 0x1000 /* Data Length = 11 Bits */ |
| #define | DLEN_12 0x1800 /* Data Length = 12 Bits */ |
| #define | DLEN_13 0x2000 /* Data Length = 13 Bits */ |
| #define | DLEN_14 0x2800 /* Data Length = 14 Bits */ |
| #define | DLEN_15 0x3000 /* Data Length = 15 Bits */ |
| #define | DLEN_16 0x3800 /* Data Length = 16 Bits */ |
| #define | POLC 0x4000 /* PPI Clock Polarity */ |
| #define | POLS 0x8000 /* PPI Frame Sync Polarity */ |
| #define | FLD 0x0400 /* Field Indicator */ |
| #define | FT_ERR 0x0800 /* Frame Track Error */ |
| #define | OVR 0x1000 /* FIFO Overflow Error */ |
| #define | UNDR 0x2000 /* FIFO Underrun Error */ |
| #define | ERR_DET 0x4000 /* Error Detected Indicator */ |
| #define | ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ |
| #define | PJSE 0x0001 /* Port J SPI/SPORT Enable */ |
| #define | PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ |
| #define | PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ |
| #define | PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ |
| #define | PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ |
| #define | PJCE_CAN 0x0002 /* Enable CAN RX/TX */ |
| #define | PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ |
| #define | PFDE 0x0008 /* Port F DMA Request Enable */ |
| #define | PFDE_UART 0x0000 /* Enable UART0 RX/TX */ |
| #define | PFDE_DMA 0x0008 /* Enable DMAR1:0 */ |
| #define | PFTE 0x0010 /* Port F Timer Enable */ |
| #define | PFTE_UART 0x0000 /* Enable UART1 RX/TX */ |
| #define | PFTE_TIMER 0x0010 /* Enable TMR7:6 */ |
| #define | PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ |
| #define | PFS6E_TIMER 0x0000 /* Enable TMR5 */ |
| #define | PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ |
| #define | PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ |
| #define | PFS5E_TIMER 0x0000 /* Enable TMR4 */ |
| #define | PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ |
| #define | PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ |
| #define | PFS4E_TIMER 0x0000 /* Enable TMR3 */ |
| #define | PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ |
| #define | PFFE 0x0100 /* Port F PPI Frame Sync Enable */ |
| #define | PFFE_TIMER 0x0000 /* Enable TMR2 */ |
| #define | PFFE_PPI 0x0100 /* Enable PPI FS3 */ |
| #define | PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ |
| #define | PGSE_PPI 0x0000 /* Enable PPI D9:8 */ |
| #define | PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ |
| #define | PGRE 0x0400 /* Port G SPORT1 Receive Enable */ |
| #define | PGRE_PPI 0x0000 /* Enable PPI D12:10 */ |
| #define | PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ |
| #define | PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ |
| #define | PGTE_PPI 0x0000 /* Enable PPI D15:13 */ |
| #define | PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ |
| #define | _BOOTROM_RESET 0xEF000000 |
| #define | _BOOTROM_FINAL_INIT 0xEF000002 |
| #define | _BOOTROM_DO_MEMORY_DMA 0xEF000006 |
| #define | _BOOTROM_BOOT_DXE_FLASH 0xEF000008 |
| #define | _BOOTROM_BOOT_DXE_SPI 0xEF00000A |
| #define | _BOOTROM_BOOT_DXE_TWI 0xEF00000C |
| #define | _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 |
| #define | _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 |
| #define | _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 |
| #define | PGDE_UART PFDE_UART |
| #define | PGDE_DMA PFDE_DMA |
| #define | CKELOW SCKELOW |
| #define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 |
Definition at line 1459 of file defBF534.h.
| #define _BOOTROM_BOOT_DXE_SPI 0xEF00000A |
Definition at line 1460 of file defBF534.h.
| #define _BOOTROM_BOOT_DXE_TWI 0xEF00000C |
Definition at line 1461 of file defBF534.h.
| #define _BOOTROM_DO_MEMORY_DMA 0xEF000006 |
Definition at line 1458 of file defBF534.h.
| #define _BOOTROM_FINAL_INIT 0xEF000002 |
Definition at line 1457 of file defBF534.h.
| #define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 |
Definition at line 1462 of file defBF534.h.
| #define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 |
Definition at line 1463 of file defBF534.h.
| #define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 |
Definition at line 1464 of file defBF534.h.
| #define _BOOTROM_RESET 0xEF000000 |
Definition at line 1456 of file defBF534.h.
| #define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ |
Definition at line 1102 of file defBF534.h.
| #define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ |
Definition at line 1099 of file defBF534.h.
| #define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ |
Definition at line 1100 of file defBF534.h.
| #define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ |
Definition at line 1101 of file defBF534.h.
| #define AMBEN_NONE 0x0000 /* All Banks Disabled */ |
Definition at line 1098 of file defBF534.h.
| #define AMCKEN 0x0001 /* Enable CLKOUT */ |
Definition at line 1097 of file defBF534.h.
| #define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ |
Definition at line 1118 of file defBF534.h.
| #define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ |
Definition at line 1115 of file defBF534.h.
| #define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ |
Definition at line 1116 of file defBF534.h.
| #define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ |
Definition at line 1117 of file defBF534.h.
| #define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ |
Definition at line 1119 of file defBF534.h.
| #define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ |
Definition at line 1128 of file defBF534.h.
| #define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ |
Definition at line 1129 of file defBF534.h.
| #define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ |
Definition at line 1130 of file defBF534.h.
| #define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ |
Definition at line 1131 of file defBF534.h.
| #define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ |
Definition at line 1132 of file defBF534.h.
| #define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ |
Definition at line 1133 of file defBF534.h.
| #define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ |
Definition at line 1120 of file defBF534.h.
| #define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ |
Definition at line 1121 of file defBF534.h.
| #define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ |
Definition at line 1122 of file defBF534.h.
| #define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ |
Definition at line 1123 of file defBF534.h.
| #define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ |
Definition at line 1124 of file defBF534.h.
| #define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ |
Definition at line 1125 of file defBF534.h.
| #define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ |
Definition at line 1126 of file defBF534.h.
| #define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ |
Definition at line 1127 of file defBF534.h.
| #define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ |
Definition at line 1105 of file defBF534.h.
| #define B0RDYPOL 0x00000002 /* B0 RDY Active High */ |
Definition at line 1106 of file defBF534.h.
| #define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ |
Definition at line 1111 of file defBF534.h.
| #define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ |
Definition at line 1112 of file defBF534.h.
| #define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ |
Definition at line 1113 of file defBF534.h.
| #define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ |
Definition at line 1114 of file defBF534.h.
| #define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ |
Definition at line 1107 of file defBF534.h.
| #define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ |
Definition at line 1108 of file defBF534.h.
| #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ |
Definition at line 1109 of file defBF534.h.
| #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ |
Definition at line 1110 of file defBF534.h.
| #define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ |
Definition at line 1134 of file defBF534.h.
| #define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ |
Definition at line 1143 of file defBF534.h.
| #define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ |
Definition at line 1144 of file defBF534.h.
| #define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ |
Definition at line 1145 of file defBF534.h.
| #define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ |
Definition at line 1146 of file defBF534.h.
| #define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ |
Definition at line 1147 of file defBF534.h.
| #define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ |
Definition at line 1148 of file defBF534.h.
| #define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ |
Definition at line 1135 of file defBF534.h.
| #define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ |
Definition at line 1136 of file defBF534.h.
| #define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ |
Definition at line 1137 of file defBF534.h.
| #define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ |
Definition at line 1138 of file defBF534.h.
| #define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ |
Definition at line 1139 of file defBF534.h.
| #define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ |
Definition at line 1140 of file defBF534.h.
| #define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ |
Definition at line 1141 of file defBF534.h.
| #define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ |
Definition at line 1142 of file defBF534.h.
| #define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ |
Definition at line 1163 of file defBF534.h.
| #define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ |
Definition at line 1160 of file defBF534.h.
| #define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ |
Definition at line 1161 of file defBF534.h.
| #define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ |
Definition at line 1162 of file defBF534.h.
| #define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ |
Definition at line 1164 of file defBF534.h.
| #define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ |
Definition at line 1173 of file defBF534.h.
| #define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ |
Definition at line 1174 of file defBF534.h.
| #define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ |
Definition at line 1175 of file defBF534.h.
| #define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ |
Definition at line 1176 of file defBF534.h.
| #define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ |
Definition at line 1177 of file defBF534.h.
| #define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ |
Definition at line 1178 of file defBF534.h.
| #define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ |
Definition at line 1165 of file defBF534.h.
| #define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ |
Definition at line 1166 of file defBF534.h.
| #define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ |
Definition at line 1167 of file defBF534.h.
| #define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ |
Definition at line 1168 of file defBF534.h.
| #define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ |
Definition at line 1169 of file defBF534.h.
| #define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ |
Definition at line 1170 of file defBF534.h.
| #define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ |
Definition at line 1171 of file defBF534.h.
| #define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ |
Definition at line 1172 of file defBF534.h.
| #define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ |
Definition at line 1150 of file defBF534.h.
| #define B1RDYPOL 0x00020000 /* B1 RDY Active High */ |
Definition at line 1151 of file defBF534.h.
| #define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ |
Definition at line 1156 of file defBF534.h.
| #define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ |
Definition at line 1157 of file defBF534.h.
| #define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ |
Definition at line 1158 of file defBF534.h.
| #define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ |
Definition at line 1159 of file defBF534.h.
| #define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ |
Definition at line 1152 of file defBF534.h.
| #define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ |
Definition at line 1153 of file defBF534.h.
| #define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ |
Definition at line 1154 of file defBF534.h.
| #define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ |
Definition at line 1155 of file defBF534.h.
| #define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ |
Definition at line 1179 of file defBF534.h.
| #define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ |
Definition at line 1188 of file defBF534.h.
| #define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ |
Definition at line 1189 of file defBF534.h.
| #define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ |
Definition at line 1190 of file defBF534.h.
| #define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ |
Definition at line 1191 of file defBF534.h.
| #define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ |
Definition at line 1192 of file defBF534.h.
| #define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ |
Definition at line 1193 of file defBF534.h.
| #define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ |
Definition at line 1180 of file defBF534.h.
| #define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ |
Definition at line 1181 of file defBF534.h.
| #define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ |
Definition at line 1182 of file defBF534.h.
| #define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ |
Definition at line 1183 of file defBF534.h.
| #define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ |
Definition at line 1184 of file defBF534.h.
| #define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ |
Definition at line 1185 of file defBF534.h.
| #define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ |
Definition at line 1186 of file defBF534.h.
| #define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ |
Definition at line 1187 of file defBF534.h.
| #define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ |
Definition at line 1209 of file defBF534.h.
| #define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ |
Definition at line 1206 of file defBF534.h.
| #define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ |
Definition at line 1207 of file defBF534.h.
| #define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ |
Definition at line 1208 of file defBF534.h.
| #define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ |
Definition at line 1210 of file defBF534.h.
| #define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ |
Definition at line 1219 of file defBF534.h.
| #define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ |
Definition at line 1220 of file defBF534.h.
| #define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ |
Definition at line 1221 of file defBF534.h.
| #define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ |
Definition at line 1222 of file defBF534.h.
| #define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ |
Definition at line 1223 of file defBF534.h.
| #define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ |
Definition at line 1224 of file defBF534.h.
| #define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ |
Definition at line 1211 of file defBF534.h.
| #define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ |
Definition at line 1212 of file defBF534.h.
| #define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ |
Definition at line 1213 of file defBF534.h.
| #define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ |
Definition at line 1214 of file defBF534.h.
| #define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ |
Definition at line 1215 of file defBF534.h.
| #define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ |
Definition at line 1216 of file defBF534.h.
| #define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ |
Definition at line 1217 of file defBF534.h.
| #define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ |
Definition at line 1218 of file defBF534.h.
| #define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ |
Definition at line 1196 of file defBF534.h.
| #define B2RDYPOL 0x00000002 /* B2 RDY Active High */ |
Definition at line 1197 of file defBF534.h.
| #define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ |
Definition at line 1202 of file defBF534.h.
| #define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ |
Definition at line 1203 of file defBF534.h.
| #define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ |
Definition at line 1204 of file defBF534.h.
| #define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ |
Definition at line 1205 of file defBF534.h.
| #define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ |
Definition at line 1198 of file defBF534.h.
| #define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ |
Definition at line 1199 of file defBF534.h.
| #define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ |
Definition at line 1200 of file defBF534.h.
| #define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ |
Definition at line 1201 of file defBF534.h.
| #define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ |
Definition at line 1225 of file defBF534.h.
| #define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ |
Definition at line 1234 of file defBF534.h.
| #define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ |
Definition at line 1235 of file defBF534.h.
| #define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ |
Definition at line 1236 of file defBF534.h.
| #define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ |
Definition at line 1237 of file defBF534.h.
| #define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ |
Definition at line 1238 of file defBF534.h.
| #define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ |
Definition at line 1239 of file defBF534.h.
| #define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ |
Definition at line 1226 of file defBF534.h.
| #define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ |
Definition at line 1227 of file defBF534.h.
| #define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ |
Definition at line 1228 of file defBF534.h.
| #define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ |
Definition at line 1229 of file defBF534.h.
| #define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ |
Definition at line 1230 of file defBF534.h.
| #define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ |
Definition at line 1231 of file defBF534.h.
| #define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ |
Definition at line 1232 of file defBF534.h.
| #define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ |
Definition at line 1233 of file defBF534.h.
| #define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ |
Definition at line 1254 of file defBF534.h.
| #define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ |
Definition at line 1251 of file defBF534.h.
| #define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ |
Definition at line 1252 of file defBF534.h.
| #define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ |
Definition at line 1253 of file defBF534.h.
| #define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ |
Definition at line 1255 of file defBF534.h.
| #define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ |
Definition at line 1264 of file defBF534.h.
| #define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ |
Definition at line 1265 of file defBF534.h.
| #define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ |
Definition at line 1266 of file defBF534.h.
| #define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ |
Definition at line 1267 of file defBF534.h.
| #define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ |
Definition at line 1268 of file defBF534.h.
| #define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ |
Definition at line 1269 of file defBF534.h.
| #define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ |
Definition at line 1256 of file defBF534.h.
| #define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ |
Definition at line 1257 of file defBF534.h.
| #define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ |
Definition at line 1258 of file defBF534.h.
| #define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ |
Definition at line 1259 of file defBF534.h.
| #define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ |
Definition at line 1260 of file defBF534.h.
| #define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ |
Definition at line 1261 of file defBF534.h.
| #define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ |
Definition at line 1262 of file defBF534.h.
| #define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ |
Definition at line 1263 of file defBF534.h.
| #define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ |
Definition at line 1241 of file defBF534.h.
| #define B3RDYPOL 0x00020000 /* B3 RDY Active High */ |
Definition at line 1242 of file defBF534.h.
| #define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ |
Definition at line 1247 of file defBF534.h.
| #define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ |
Definition at line 1248 of file defBF534.h.
| #define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ |
Definition at line 1249 of file defBF534.h.
| #define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ |
Definition at line 1250 of file defBF534.h.
| #define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ |
Definition at line 1243 of file defBF534.h.
| #define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ |
Definition at line 1244 of file defBF534.h.
| #define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ |
Definition at line 1245 of file defBF534.h.
| #define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ |
Definition at line 1246 of file defBF534.h.
| #define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ |
Definition at line 1270 of file defBF534.h.
| #define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ |
Definition at line 1279 of file defBF534.h.
| #define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ |
Definition at line 1280 of file defBF534.h.
| #define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ |
Definition at line 1281 of file defBF534.h.
| #define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ |
Definition at line 1282 of file defBF534.h.
| #define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ |
Definition at line 1283 of file defBF534.h.
| #define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ |
Definition at line 1284 of file defBF534.h.
| #define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ |
Definition at line 1271 of file defBF534.h.
| #define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ |
Definition at line 1272 of file defBF534.h.
| #define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ |
Definition at line 1273 of file defBF534.h.
| #define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ |
Definition at line 1274 of file defBF534.h.
| #define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ |
Definition at line 1275 of file defBF534.h.
| #define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ |
Definition at line 1276 of file defBF534.h.
| #define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ |
Definition at line 1277 of file defBF534.h.
| #define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ |
Definition at line 1278 of file defBF534.h.
| #define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ |
Definition at line 924 of file defBF534.h.
| #define BGSTAT 0x0020 /* Bus Grant Status */ |
Definition at line 1355 of file defBF534.h.
| #define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ |
Definition at line 968 of file defBF534.h.
| #define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ |
Definition at line 506 of file defBF534.h.
| #define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ |
Definition at line 521 of file defBF534.h.
| #define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ |
Definition at line 552 of file defBF534.h.
| #define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ |
Definition at line 551 of file defBF534.h.
| #define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ |
Definition at line 554 of file defBF534.h.
| #define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ |
Definition at line 553 of file defBF534.h.
| #define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ |
Definition at line 556 of file defBF534.h.
| #define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ |
Definition at line 555 of file defBF534.h.
| #define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ |
Definition at line 558 of file defBF534.h.
| #define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ |
Definition at line 557 of file defBF534.h.
| #define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ |
Definition at line 560 of file defBF534.h.
| #define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ |
Definition at line 559 of file defBF534.h.
| #define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ |
Definition at line 562 of file defBF534.h.
| #define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ |
Definition at line 561 of file defBF534.h.
| #define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ |
Definition at line 564 of file defBF534.h.
| #define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ |
Definition at line 563 of file defBF534.h.
| #define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ |
Definition at line 566 of file defBF534.h.
| #define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ |
Definition at line 565 of file defBF534.h.
| #define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ |
Definition at line 568 of file defBF534.h.
| #define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ |
Definition at line 567 of file defBF534.h.
| #define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ |
Definition at line 570 of file defBF534.h.
| #define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ |
Definition at line 569 of file defBF534.h.
| #define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ |
Definition at line 572 of file defBF534.h.
| #define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ |
Definition at line 571 of file defBF534.h.
| #define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ |
Definition at line 574 of file defBF534.h.
| #define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ |
Definition at line 573 of file defBF534.h.
| #define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ |
Definition at line 576 of file defBF534.h.
| #define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ |
Definition at line 575 of file defBF534.h.
| #define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ |
Definition at line 578 of file defBF534.h.
| #define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ |
Definition at line 577 of file defBF534.h.
| #define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ |
Definition at line 580 of file defBF534.h.
| #define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ |
Definition at line 579 of file defBF534.h.
| #define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ |
Definition at line 582 of file defBF534.h.
| #define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ |
Definition at line 581 of file defBF534.h.
| #define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ |
Definition at line 585 of file defBF534.h.
| #define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ |
Definition at line 584 of file defBF534.h.
| #define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ |
Definition at line 587 of file defBF534.h.
| #define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ |
Definition at line 586 of file defBF534.h.
| #define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ |
Definition at line 589 of file defBF534.h.
| #define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ |
Definition at line 588 of file defBF534.h.
| #define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ |
Definition at line 591 of file defBF534.h.
| #define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ |
Definition at line 590 of file defBF534.h.
| #define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ |
Definition at line 593 of file defBF534.h.
| #define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ |
Definition at line 592 of file defBF534.h.
| #define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ |
Definition at line 595 of file defBF534.h.
| #define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ |
Definition at line 594 of file defBF534.h.
| #define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ |
Definition at line 597 of file defBF534.h.
| #define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ |
Definition at line 596 of file defBF534.h.
| #define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ |
Definition at line 599 of file defBF534.h.
| #define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ |
Definition at line 598 of file defBF534.h.
| #define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ |
Definition at line 601 of file defBF534.h.
| #define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ |
Definition at line 600 of file defBF534.h.
| #define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ |
Definition at line 603 of file defBF534.h.
| #define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ |
Definition at line 602 of file defBF534.h.
| #define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ |
Definition at line 605 of file defBF534.h.
| #define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ |
Definition at line 604 of file defBF534.h.
| #define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ |
Definition at line 607 of file defBF534.h.
| #define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ |
Definition at line 606 of file defBF534.h.
| #define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ |
Definition at line 609 of file defBF534.h.
| #define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ |
Definition at line 608 of file defBF534.h.
| #define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ |
Definition at line 611 of file defBF534.h.
| #define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ |
Definition at line 610 of file defBF534.h.
| #define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ |
Definition at line 613 of file defBF534.h.
| #define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ |
Definition at line 612 of file defBF534.h.
| #define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ |
Definition at line 615 of file defBF534.h.
| #define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ |
Definition at line 614 of file defBF534.h.
Definition at line 619 of file defBF534.h.
Definition at line 618 of file defBF534.h.
| #define CAN_CEC 0xFFC02A90 /* Error Counter Register */ |
Definition at line 535 of file defBF534.h.
| #define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ |
Definition at line 531 of file defBF534.h.
| #define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ |
Definition at line 539 of file defBF534.h.
| #define CAN_DEBUG 0xFFC02A88 /* Debug Register */ |
Definition at line 533 of file defBF534.h.
| #define CAN_ESR 0xFFC02AB4 /* Error Status Register */ |
Definition at line 544 of file defBF534.h.
| #define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ |
Definition at line 543 of file defBF534.h.
| #define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ |
Definition at line 538 of file defBF534.h.
| #define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ |
Definition at line 537 of file defBF534.h.
| #define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ |
Definition at line 536 of file defBF534.h.
| #define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ |
Definition at line 540 of file defBF534.h.
| #define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ |
Definition at line 622 of file defBF534.h.
| #define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ |
Definition at line 623 of file defBF534.h.
| #define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ |
Definition at line 624 of file defBF534.h.
| #define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ |
Definition at line 625 of file defBF534.h.
| #define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ |
Definition at line 628 of file defBF534.h.
| #define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ |
Definition at line 629 of file defBF534.h.
| #define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ |
Definition at line 626 of file defBF534.h.
| #define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ |
Definition at line 627 of file defBF534.h.
| #define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ |
Definition at line 631 of file defBF534.h.
| #define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ |
Definition at line 632 of file defBF534.h.
| #define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ |
Definition at line 633 of file defBF534.h.
| #define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ |
Definition at line 634 of file defBF534.h.
| #define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ |
Definition at line 637 of file defBF534.h.
| #define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ |
Definition at line 638 of file defBF534.h.
| #define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ |
Definition at line 635 of file defBF534.h.
| #define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ |
Definition at line 636 of file defBF534.h.
| #define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ |
Definition at line 640 of file defBF534.h.
| #define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ |
Definition at line 641 of file defBF534.h.
| #define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ |
Definition at line 642 of file defBF534.h.
| #define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ |
Definition at line 643 of file defBF534.h.
| #define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ |
Definition at line 646 of file defBF534.h.
| #define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ |
Definition at line 647 of file defBF534.h.
| #define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ |
Definition at line 644 of file defBF534.h.
| #define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ |
Definition at line 645 of file defBF534.h.
| #define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ |
Definition at line 649 of file defBF534.h.
| #define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ |
Definition at line 650 of file defBF534.h.
| #define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ |
Definition at line 651 of file defBF534.h.
| #define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ |
Definition at line 652 of file defBF534.h.
| #define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ |
Definition at line 655 of file defBF534.h.
| #define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ |
Definition at line 656 of file defBF534.h.
| #define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ |
Definition at line 653 of file defBF534.h.
| #define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ |
Definition at line 654 of file defBF534.h.
| #define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ |
Definition at line 658 of file defBF534.h.
| #define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ |
Definition at line 659 of file defBF534.h.
| #define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ |
Definition at line 660 of file defBF534.h.
| #define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ |
Definition at line 661 of file defBF534.h.
| #define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ |
Definition at line 664 of file defBF534.h.
| #define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ |
Definition at line 665 of file defBF534.h.
| #define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ |
Definition at line 662 of file defBF534.h.
| #define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ |
Definition at line 663 of file defBF534.h.
| #define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ |
Definition at line 667 of file defBF534.h.
| #define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ |
Definition at line 668 of file defBF534.h.
| #define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ |
Definition at line 669 of file defBF534.h.
| #define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ |
Definition at line 670 of file defBF534.h.
| #define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ |
Definition at line 673 of file defBF534.h.
| #define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ |
Definition at line 674 of file defBF534.h.
| #define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ |
Definition at line 671 of file defBF534.h.
| #define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ |
Definition at line 672 of file defBF534.h.
| #define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ |
Definition at line 676 of file defBF534.h.
| #define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ |
Definition at line 677 of file defBF534.h.
| #define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ |
Definition at line 678 of file defBF534.h.
| #define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ |
Definition at line 679 of file defBF534.h.
| #define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ |
Definition at line 682 of file defBF534.h.
| #define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ |
Definition at line 683 of file defBF534.h.
| #define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ |
Definition at line 680 of file defBF534.h.
| #define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ |
Definition at line 681 of file defBF534.h.
| #define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ |
Definition at line 685 of file defBF534.h.
| #define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ |
Definition at line 686 of file defBF534.h.
| #define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ |
Definition at line 687 of file defBF534.h.
| #define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ |
Definition at line 688 of file defBF534.h.
| #define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ |
Definition at line 691 of file defBF534.h.
| #define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ |
Definition at line 692 of file defBF534.h.
| #define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ |
Definition at line 689 of file defBF534.h.
| #define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ |
Definition at line 690 of file defBF534.h.
| #define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ |
Definition at line 694 of file defBF534.h.
| #define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ |
Definition at line 695 of file defBF534.h.
| #define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ |
Definition at line 696 of file defBF534.h.
| #define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ |
Definition at line 697 of file defBF534.h.
| #define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ |
Definition at line 700 of file defBF534.h.
| #define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ |
Definition at line 701 of file defBF534.h.
| #define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ |
Definition at line 698 of file defBF534.h.
| #define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ |
Definition at line 699 of file defBF534.h.
| #define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ |
Definition at line 703 of file defBF534.h.
| #define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ |
Definition at line 704 of file defBF534.h.
| #define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ |
Definition at line 705 of file defBF534.h.
| #define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ |
Definition at line 706 of file defBF534.h.
| #define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ |
Definition at line 709 of file defBF534.h.
| #define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ |
Definition at line 710 of file defBF534.h.
| #define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ |
Definition at line 707 of file defBF534.h.
| #define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ |
Definition at line 708 of file defBF534.h.
| #define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ |
Definition at line 712 of file defBF534.h.
| #define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ |
Definition at line 713 of file defBF534.h.
| #define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ |
Definition at line 714 of file defBF534.h.
| #define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ |
Definition at line 715 of file defBF534.h.
| #define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ |
Definition at line 718 of file defBF534.h.
| #define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ |
Definition at line 719 of file defBF534.h.
| #define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ |
Definition at line 716 of file defBF534.h.
| #define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ |
Definition at line 717 of file defBF534.h.
| #define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ |
Definition at line 721 of file defBF534.h.
| #define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ |
Definition at line 722 of file defBF534.h.
| #define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ |
Definition at line 723 of file defBF534.h.
| #define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ |
Definition at line 724 of file defBF534.h.
| #define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ |
Definition at line 727 of file defBF534.h.
| #define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ |
Definition at line 728 of file defBF534.h.
| #define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ |
Definition at line 725 of file defBF534.h.
| #define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ |
Definition at line 726 of file defBF534.h.
| #define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ |
Definition at line 730 of file defBF534.h.
| #define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ |
Definition at line 731 of file defBF534.h.
| #define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ |
Definition at line 732 of file defBF534.h.
| #define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ |
Definition at line 733 of file defBF534.h.
| #define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ |
Definition at line 736 of file defBF534.h.
| #define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ |
Definition at line 737 of file defBF534.h.
| #define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ |
Definition at line 734 of file defBF534.h.
| #define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ |
Definition at line 735 of file defBF534.h.
| #define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ |
Definition at line 739 of file defBF534.h.
| #define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ |
Definition at line 740 of file defBF534.h.
| #define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ |
Definition at line 741 of file defBF534.h.
| #define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ |
Definition at line 742 of file defBF534.h.
| #define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ |
Definition at line 745 of file defBF534.h.
| #define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ |
Definition at line 746 of file defBF534.h.
| #define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ |
Definition at line 743 of file defBF534.h.
| #define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ |
Definition at line 744 of file defBF534.h.
| #define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ |
Definition at line 748 of file defBF534.h.
| #define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ |
Definition at line 749 of file defBF534.h.
| #define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ |
Definition at line 750 of file defBF534.h.
| #define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ |
Definition at line 751 of file defBF534.h.
| #define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ |
Definition at line 754 of file defBF534.h.
| #define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ |
Definition at line 755 of file defBF534.h.
| #define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ |
Definition at line 752 of file defBF534.h.
| #define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ |
Definition at line 753 of file defBF534.h.
| #define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ |
Definition at line 757 of file defBF534.h.
| #define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ |
Definition at line 758 of file defBF534.h.
| #define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ |
Definition at line 759 of file defBF534.h.
| #define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ |
Definition at line 760 of file defBF534.h.
| #define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ |
Definition at line 763 of file defBF534.h.
| #define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ |
Definition at line 764 of file defBF534.h.
| #define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ |
Definition at line 761 of file defBF534.h.
| #define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ |
Definition at line 762 of file defBF534.h.
| #define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ |
Definition at line 766 of file defBF534.h.
| #define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ |
Definition at line 767 of file defBF534.h.
| #define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ |
Definition at line 768 of file defBF534.h.
| #define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ |
Definition at line 769 of file defBF534.h.
| #define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ |
Definition at line 772 of file defBF534.h.
| #define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ |
Definition at line 773 of file defBF534.h.
| #define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ |
Definition at line 770 of file defBF534.h.
| #define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ |
Definition at line 771 of file defBF534.h.
| #define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ |
Definition at line 775 of file defBF534.h.
| #define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ |
Definition at line 776 of file defBF534.h.
| #define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ |
Definition at line 777 of file defBF534.h.
| #define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ |
Definition at line 778 of file defBF534.h.
| #define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ |
Definition at line 781 of file defBF534.h.
| #define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ |
Definition at line 782 of file defBF534.h.
| #define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ |
Definition at line 779 of file defBF534.h.
| #define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ |
Definition at line 780 of file defBF534.h.
| #define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ |
Definition at line 784 of file defBF534.h.
| #define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ |
Definition at line 785 of file defBF534.h.
| #define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ |
Definition at line 786 of file defBF534.h.
| #define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ |
Definition at line 787 of file defBF534.h.
| #define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ |
Definition at line 790 of file defBF534.h.
| #define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ |
Definition at line 791 of file defBF534.h.
| #define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ |
Definition at line 788 of file defBF534.h.
| #define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ |
Definition at line 789 of file defBF534.h.
| #define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ |
Definition at line 793 of file defBF534.h.
| #define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ |
Definition at line 794 of file defBF534.h.
| #define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ |
Definition at line 795 of file defBF534.h.
| #define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ |
Definition at line 796 of file defBF534.h.
| #define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ |
Definition at line 799 of file defBF534.h.
| #define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ |
Definition at line 800 of file defBF534.h.
| #define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ |
Definition at line 797 of file defBF534.h.
| #define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ |
Definition at line 798 of file defBF534.h.
| #define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ |
Definition at line 802 of file defBF534.h.
| #define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ |
Definition at line 803 of file defBF534.h.
| #define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ |
Definition at line 804 of file defBF534.h.
| #define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ |
Definition at line 805 of file defBF534.h.
| #define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ |
Definition at line 808 of file defBF534.h.
| #define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ |
Definition at line 809 of file defBF534.h.
| #define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ |
Definition at line 806 of file defBF534.h.
| #define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ |
Definition at line 807 of file defBF534.h.
| #define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ |
Definition at line 811 of file defBF534.h.
| #define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ |
Definition at line 812 of file defBF534.h.
| #define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ |
Definition at line 813 of file defBF534.h.
| #define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ |
Definition at line 814 of file defBF534.h.
| #define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ |
Definition at line 817 of file defBF534.h.
| #define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ |
Definition at line 818 of file defBF534.h.
| #define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ |
Definition at line 815 of file defBF534.h.
| #define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ |
Definition at line 816 of file defBF534.h.
| #define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ |
Definition at line 820 of file defBF534.h.
| #define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ |
Definition at line 821 of file defBF534.h.
| #define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ |
Definition at line 822 of file defBF534.h.
| #define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ |
Definition at line 823 of file defBF534.h.
| #define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ |
Definition at line 826 of file defBF534.h.
| #define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ |
Definition at line 827 of file defBF534.h.
| #define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ |
Definition at line 824 of file defBF534.h.
| #define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ |
Definition at line 825 of file defBF534.h.
| #define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ |
Definition at line 829 of file defBF534.h.
| #define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ |
Definition at line 830 of file defBF534.h.
| #define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ |
Definition at line 831 of file defBF534.h.
| #define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ |
Definition at line 832 of file defBF534.h.
| #define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ |
Definition at line 835 of file defBF534.h.
| #define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ |
Definition at line 836 of file defBF534.h.
| #define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ |
Definition at line 833 of file defBF534.h.
| #define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ |
Definition at line 834 of file defBF534.h.
| #define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ |
Definition at line 838 of file defBF534.h.
| #define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ |
Definition at line 839 of file defBF534.h.
| #define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ |
Definition at line 840 of file defBF534.h.
| #define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ |
Definition at line 841 of file defBF534.h.
| #define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ |
Definition at line 844 of file defBF534.h.
| #define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ |
Definition at line 845 of file defBF534.h.
| #define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ |
Definition at line 842 of file defBF534.h.
| #define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ |
Definition at line 843 of file defBF534.h.
| #define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ |
Definition at line 847 of file defBF534.h.
| #define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ |
Definition at line 848 of file defBF534.h.
| #define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ |
Definition at line 849 of file defBF534.h.
| #define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ |
Definition at line 850 of file defBF534.h.
| #define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ |
Definition at line 853 of file defBF534.h.
| #define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ |
Definition at line 854 of file defBF534.h.
| #define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ |
Definition at line 851 of file defBF534.h.
| #define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ |
Definition at line 852 of file defBF534.h.
| #define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ |
Definition at line 856 of file defBF534.h.
| #define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ |
Definition at line 857 of file defBF534.h.
| #define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ |
Definition at line 858 of file defBF534.h.
| #define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ |
Definition at line 859 of file defBF534.h.
| #define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ |
Definition at line 862 of file defBF534.h.
| #define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ |
Definition at line 863 of file defBF534.h.
| #define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ |
Definition at line 860 of file defBF534.h.
| #define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ |
Definition at line 861 of file defBF534.h.
| #define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ |
Definition at line 865 of file defBF534.h.
| #define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ |
Definition at line 866 of file defBF534.h.
| #define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ |
Definition at line 867 of file defBF534.h.
| #define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ |
Definition at line 868 of file defBF534.h.
| #define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ |
Definition at line 871 of file defBF534.h.
| #define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ |
Definition at line 872 of file defBF534.h.
| #define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ |
Definition at line 869 of file defBF534.h.
| #define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ |
Definition at line 870 of file defBF534.h.
| #define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ |
Definition at line 874 of file defBF534.h.
| #define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ |
Definition at line 875 of file defBF534.h.
| #define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ |
Definition at line 876 of file defBF534.h.
| #define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ |
Definition at line 877 of file defBF534.h.
| #define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ |
Definition at line 880 of file defBF534.h.
| #define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ |
Definition at line 881 of file defBF534.h.
| #define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ |
Definition at line 878 of file defBF534.h.
| #define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ |
Definition at line 879 of file defBF534.h.
| #define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ |
Definition at line 883 of file defBF534.h.
| #define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ |
Definition at line 884 of file defBF534.h.
| #define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ |
Definition at line 885 of file defBF534.h.
| #define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ |
Definition at line 886 of file defBF534.h.
| #define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ |
Definition at line 889 of file defBF534.h.
| #define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ |
Definition at line 890 of file defBF534.h.
| #define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ |
Definition at line 887 of file defBF534.h.
| #define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ |
Definition at line 888 of file defBF534.h.
| #define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ |
Definition at line 892 of file defBF534.h.
| #define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ |
Definition at line 893 of file defBF534.h.
| #define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ |
Definition at line 894 of file defBF534.h.
| #define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ |
Definition at line 895 of file defBF534.h.
| #define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ |
Definition at line 898 of file defBF534.h.
| #define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ |
Definition at line 899 of file defBF534.h.
| #define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ |
Definition at line 896 of file defBF534.h.
| #define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ |
Definition at line 897 of file defBF534.h.
| #define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ |
Definition at line 901 of file defBF534.h.
| #define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ |
Definition at line 902 of file defBF534.h.
| #define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ |
Definition at line 903 of file defBF534.h.
| #define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ |
Definition at line 904 of file defBF534.h.
| #define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ |
Definition at line 907 of file defBF534.h.
| #define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ |
Definition at line 908 of file defBF534.h.
| #define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ |
Definition at line 905 of file defBF534.h.
| #define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ |
Definition at line 906 of file defBF534.h.
| #define CAN_MB_DATA0 | ( | x | ) | (CAN_MB00_DATA0+((x)*0x20)) |
Definition at line 918 of file defBF534.h.
| #define CAN_MB_DATA1 | ( | x | ) | (CAN_MB00_DATA1+((x)*0x20)) |
Definition at line 917 of file defBF534.h.
| #define CAN_MB_DATA2 | ( | x | ) | (CAN_MB00_DATA2+((x)*0x20)) |
Definition at line 916 of file defBF534.h.
| #define CAN_MB_DATA3 | ( | x | ) | (CAN_MB00_DATA3+((x)*0x20)) |
Definition at line 915 of file defBF534.h.
| #define CAN_MB_ID0 | ( | x | ) | (CAN_MB00_ID0+((x)*0x20)) |
Definition at line 912 of file defBF534.h.
| #define CAN_MB_ID1 | ( | x | ) | (CAN_MB00_ID1+((x)*0x20)) |
Definition at line 911 of file defBF534.h.
| #define CAN_MB_LENGTH | ( | x | ) | (CAN_MB00_LENGTH+((x)*0x20)) |
Definition at line 914 of file defBF534.h.
| #define CAN_MB_TIMESTAMP | ( | x | ) | (CAN_MB00_TIMESTAMP+((x)*0x20)) |
Definition at line 913 of file defBF534.h.
| #define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ |
Definition at line 511 of file defBF534.h.
| #define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ |
Definition at line 526 of file defBF534.h.
| #define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ |
Definition at line 510 of file defBF534.h.
| #define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ |
Definition at line 525 of file defBF534.h.
| #define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ |
Definition at line 542 of file defBF534.h.
| #define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ |
Definition at line 509 of file defBF534.h.
| #define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ |
Definition at line 524 of file defBF534.h.
| #define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ |
Definition at line 501 of file defBF534.h.
| #define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ |
Definition at line 516 of file defBF534.h.
| #define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ |
Definition at line 502 of file defBF534.h.
| #define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ |
Definition at line 517 of file defBF534.h.
| #define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */ |
Definition at line 513 of file defBF534.h.
| #define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */ |
Definition at line 528 of file defBF534.h.
| #define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ |
Definition at line 512 of file defBF534.h.
| #define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ |
Definition at line 527 of file defBF534.h.
| #define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ |
Definition at line 508 of file defBF534.h.
| #define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ |
Definition at line 523 of file defBF534.h.
| #define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ |
Definition at line 507 of file defBF534.h.
| #define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ |
Definition at line 522 of file defBF534.h.
| #define CAN_STATUS 0xFFC02A8C /* Global Status Register */ |
Definition at line 534 of file defBF534.h.
| #define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ |
Definition at line 505 of file defBF534.h.
| #define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ |
Definition at line 520 of file defBF534.h.
| #define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ |
Definition at line 532 of file defBF534.h.
| #define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ |
Definition at line 504 of file defBF534.h.
| #define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ |
Definition at line 519 of file defBF534.h.
| #define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ |
Definition at line 503 of file defBF534.h.
| #define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ |
Definition at line 518 of file defBF534.h.
| #define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ |
Definition at line 548 of file defBF534.h.
| #define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ |
Definition at line 546 of file defBF534.h.
| #define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */ |
Definition at line 547 of file defBF534.h.
| #define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */ |
Definition at line 545 of file defBF534.h.
| #define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ |
Definition at line 1334 of file defBF534.h.
| #define CHIPID 0xFFC00014 /* Chip ID Register */ |
Definition at line 19 of file defBF534.h.
| #define CHIPID_FAMILY 0x0FFFF000 |
Definition at line 957 of file defBF534.h.
| #define CHIPID_MANUFACTURE 0x00000FFE |
Definition at line 958 of file defBF534.h.
| #define CHIPID_VERSION 0xF0000000 |
Definition at line 956 of file defBF534.h.
| #define CKELOW SCKELOW |
Definition at line 1469 of file defBF534.h.
| #define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ |
Definition at line 1289 of file defBF534.h.
| #define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ |
Definition at line 1290 of file defBF534.h.
| #define CLK_SEL 0x0080 /* Timer Clock Select */ |
Definition at line 1090 of file defBF534.h.
| #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ |
Definition at line 1360 of file defBF534.h.
| #define DLEN_10 0x0800 /* Data Length = 10 Bits */ |
Definition at line 1388 of file defBF534.h.
| #define DLEN_11 0x1000 /* Data Length = 11 Bits */ |
Definition at line 1389 of file defBF534.h.
| #define DLEN_12 0x1800 /* Data Length = 12 Bits */ |
Definition at line 1390 of file defBF534.h.
| #define DLEN_13 0x2000 /* Data Length = 13 Bits */ |
Definition at line 1391 of file defBF534.h.
| #define DLEN_14 0x2800 /* Data Length = 14 Bits */ |
Definition at line 1392 of file defBF534.h.
| #define DLEN_15 0x3000 /* Data Length = 15 Bits */ |
Definition at line 1393 of file defBF534.h.
| #define DLEN_16 0x3800 /* Data Length = 16 Bits */ |
Definition at line 1394 of file defBF534.h.
| #define DLEN_8 0x0000 /* Data Length = 8 Bits */ |
Definition at line 1387 of file defBF534.h.
| #define DLENGTH 0x3800 /* PPI Data Length */ |
Definition at line 1386 of file defBF534.h.
| #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ |
Definition at line 199 of file defBF534.h.
| #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ |
Definition at line 205 of file defBF534.h.
| #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ |
Definition at line 204 of file defBF534.h.
| #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ |
Definition at line 208 of file defBF534.h.
| #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ |
Definition at line 209 of file defBF534.h.
| #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ |
Definition at line 206 of file defBF534.h.
| #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ |
Definition at line 197 of file defBF534.h.
| #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ |
Definition at line 207 of file defBF534.h.
| #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ |
Definition at line 198 of file defBF534.h.
| #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ |
Definition at line 200 of file defBF534.h.
| #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ |
Definition at line 201 of file defBF534.h.
| #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ |
Definition at line 202 of file defBF534.h.
| #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ |
Definition at line 203 of file defBF534.h.
| #define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ |
Definition at line 339 of file defBF534.h.
| #define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ |
Definition at line 345 of file defBF534.h.
| #define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ |
Definition at line 344 of file defBF534.h.
| #define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ |
Definition at line 348 of file defBF534.h.
| #define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ |
Definition at line 349 of file defBF534.h.
| #define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ |
Definition at line 346 of file defBF534.h.
| #define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ |
Definition at line 337 of file defBF534.h.
| #define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ |
Definition at line 347 of file defBF534.h.
| #define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ |
Definition at line 338 of file defBF534.h.
| #define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ |
Definition at line 340 of file defBF534.h.
| #define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ |
Definition at line 341 of file defBF534.h.
| #define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ |
Definition at line 342 of file defBF534.h.
| #define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ |
Definition at line 343 of file defBF534.h.
| #define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ |
Definition at line 353 of file defBF534.h.
| #define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ |
Definition at line 359 of file defBF534.h.
| #define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ |
Definition at line 358 of file defBF534.h.
| #define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ |
Definition at line 362 of file defBF534.h.
| #define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ |
Definition at line 363 of file defBF534.h.
| #define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ |
Definition at line 360 of file defBF534.h.
| #define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ |
Definition at line 351 of file defBF534.h.
| #define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ |
Definition at line 361 of file defBF534.h.
| #define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ |
Definition at line 352 of file defBF534.h.
| #define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ |
Definition at line 354 of file defBF534.h.
| #define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ |
Definition at line 355 of file defBF534.h.
| #define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ |
Definition at line 356 of file defBF534.h.
| #define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ |
Definition at line 357 of file defBF534.h.
| #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ |
Definition at line 213 of file defBF534.h.
| #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ |
Definition at line 219 of file defBF534.h.
| #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ |
Definition at line 218 of file defBF534.h.
| #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ |
Definition at line 222 of file defBF534.h.
| #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ |
Definition at line 223 of file defBF534.h.
| #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ |
Definition at line 220 of file defBF534.h.
| #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ |
Definition at line 211 of file defBF534.h.
| #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ |
Definition at line 221 of file defBF534.h.
| #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ |
Definition at line 212 of file defBF534.h.
| #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ |
Definition at line 214 of file defBF534.h.
| #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ |
Definition at line 215 of file defBF534.h.
| #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ |
Definition at line 216 of file defBF534.h.
| #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ |
Definition at line 217 of file defBF534.h.
| #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ |
Definition at line 227 of file defBF534.h.
| #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ |
Definition at line 233 of file defBF534.h.
| #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ |
Definition at line 232 of file defBF534.h.
| #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ |
Definition at line 236 of file defBF534.h.
| #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ |
Definition at line 237 of file defBF534.h.
| #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ |
Definition at line 234 of file defBF534.h.
| #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ |
Definition at line 225 of file defBF534.h.
| #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ |
Definition at line 235 of file defBF534.h.
| #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ |
Definition at line 226 of file defBF534.h.
| #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ |
Definition at line 228 of file defBF534.h.
| #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ |
Definition at line 229 of file defBF534.h.
| #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ |
Definition at line 230 of file defBF534.h.
| #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ |
Definition at line 231 of file defBF534.h.
| #define DMA32 0x0100 /* PPI 32-bit DMA Enable */ |
Definition at line 1383 of file defBF534.h.
| #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ |
Definition at line 241 of file defBF534.h.
| #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ |
Definition at line 247 of file defBF534.h.
| #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ |
Definition at line 246 of file defBF534.h.
| #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ |
Definition at line 250 of file defBF534.h.
| #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ |
Definition at line 251 of file defBF534.h.
| #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ |
Definition at line 248 of file defBF534.h.
| #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ |
Definition at line 239 of file defBF534.h.
| #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ |
Definition at line 249 of file defBF534.h.
| #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ |
Definition at line 240 of file defBF534.h.
| #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ |
Definition at line 242 of file defBF534.h.
| #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ |
Definition at line 243 of file defBF534.h.
| #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ |
Definition at line 244 of file defBF534.h.
| #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ |
Definition at line 245 of file defBF534.h.
| #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ |
Definition at line 255 of file defBF534.h.
| #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ |
Definition at line 261 of file defBF534.h.
| #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ |
Definition at line 260 of file defBF534.h.
| #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ |
Definition at line 264 of file defBF534.h.
| #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ |
Definition at line 265 of file defBF534.h.
| #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ |
Definition at line 262 of file defBF534.h.
| #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ |
Definition at line 253 of file defBF534.h.
| #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ |
Definition at line 263 of file defBF534.h.
| #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ |
Definition at line 254 of file defBF534.h.
| #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ |
Definition at line 256 of file defBF534.h.
| #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ |
Definition at line 257 of file defBF534.h.
| #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ |
Definition at line 258 of file defBF534.h.
| #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ |
Definition at line 259 of file defBF534.h.
| #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ |
Definition at line 269 of file defBF534.h.
| #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ |
Definition at line 275 of file defBF534.h.
| #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ |
Definition at line 274 of file defBF534.h.
| #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ |
Definition at line 278 of file defBF534.h.
| #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ |
Definition at line 279 of file defBF534.h.
| #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ |
Definition at line 276 of file defBF534.h.
| #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ |
Definition at line 267 of file defBF534.h.
| #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ |
Definition at line 277 of file defBF534.h.
| #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ |
Definition at line 268 of file defBF534.h.
| #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ |
Definition at line 270 of file defBF534.h.
| #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ |
Definition at line 271 of file defBF534.h.
| #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ |
Definition at line 272 of file defBF534.h.
| #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ |
Definition at line 273 of file defBF534.h.
| #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ |
Definition at line 283 of file defBF534.h.
| #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ |
Definition at line 289 of file defBF534.h.
| #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ |
Definition at line 288 of file defBF534.h.
| #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ |
Definition at line 292 of file defBF534.h.
| #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ |
Definition at line 293 of file defBF534.h.
| #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ |
Definition at line 290 of file defBF534.h.
| #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ |
Definition at line 281 of file defBF534.h.
| #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ |
Definition at line 291 of file defBF534.h.
| #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ |
Definition at line 282 of file defBF534.h.
| #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ |
Definition at line 284 of file defBF534.h.
| #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ |
Definition at line 285 of file defBF534.h.
| #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ |
Definition at line 286 of file defBF534.h.
| #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ |
Definition at line 287 of file defBF534.h.
| #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ |
Definition at line 297 of file defBF534.h.
| #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ |
Definition at line 303 of file defBF534.h.
| #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ |
Definition at line 302 of file defBF534.h.
| #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ |
Definition at line 306 of file defBF534.h.
| #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ |
Definition at line 307 of file defBF534.h.
| #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ |
Definition at line 304 of file defBF534.h.
| #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ |
Definition at line 295 of file defBF534.h.
| #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ |
Definition at line 305 of file defBF534.h.
| #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ |
Definition at line 296 of file defBF534.h.
| #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ |
Definition at line 298 of file defBF534.h.
| #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ |
Definition at line 299 of file defBF534.h.
| #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ |
Definition at line 300 of file defBF534.h.
| #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ |
Definition at line 301 of file defBF534.h.
| #define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ |
Definition at line 311 of file defBF534.h.
| #define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ |
Definition at line 317 of file defBF534.h.
| #define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ |
Definition at line 316 of file defBF534.h.
| #define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ |
Definition at line 320 of file defBF534.h.
| #define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ |
Definition at line 321 of file defBF534.h.
| #define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ |
Definition at line 318 of file defBF534.h.
| #define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ |
Definition at line 309 of file defBF534.h.
| #define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ |
Definition at line 319 of file defBF534.h.
| #define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ |
Definition at line 310 of file defBF534.h.
| #define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ |
Definition at line 312 of file defBF534.h.
| #define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ |
Definition at line 313 of file defBF534.h.
| #define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ |
Definition at line 314 of file defBF534.h.
| #define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ |
Definition at line 315 of file defBF534.h.
| #define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ |
Definition at line 325 of file defBF534.h.
| #define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ |
Definition at line 331 of file defBF534.h.
| #define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ |
Definition at line 330 of file defBF534.h.
| #define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ |
Definition at line 334 of file defBF534.h.
| #define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ |
Definition at line 335 of file defBF534.h.
| #define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ |
Definition at line 332 of file defBF534.h.
| #define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ |
Definition at line 323 of file defBF534.h.
| #define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ |
Definition at line 333 of file defBF534.h.
| #define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ |
Definition at line 324 of file defBF534.h.
| #define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ |
Definition at line 326 of file defBF534.h.
| #define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ |
Definition at line 327 of file defBF534.h.
| #define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ |
Definition at line 328 of file defBF534.h.
| #define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ |
Definition at line 329 of file defBF534.h.
| #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ |
Definition at line 194 of file defBF534.h.
| #define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ |
Definition at line 193 of file defBF534.h.
| #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ |
Definition at line 962 of file defBF534.h.
| #define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ |
Definition at line 1346 of file defBF534.h.
| #define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ |
Definition at line 1347 of file defBF534.h.
| #define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ |
Definition at line 1344 of file defBF534.h.
| #define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ |
Definition at line 1345 of file defBF534.h.
| #define EBE 0x0001 /* Enable SDRAM External Bank */ |
Definition at line 1337 of file defBF534.h.
| #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ |
Definition at line 185 of file defBF534.h.
| #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ |
Definition at line 186 of file defBF534.h.
| #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ |
Definition at line 184 of file defBF534.h.
| #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ |
Definition at line 188 of file defBF534.h.
| #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ |
Definition at line 187 of file defBF534.h.
| #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ |
Definition at line 189 of file defBF534.h.
| #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ |
Definition at line 190 of file defBF534.h.
| #define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ |
Definition at line 1341 of file defBF534.h.
| #define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ |
Definition at line 1338 of file defBF534.h.
| #define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ |
Definition at line 1342 of file defBF534.h.
| #define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ |
Definition at line 1339 of file defBF534.h.
| #define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ |
Definition at line 1343 of file defBF534.h.
| #define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ |
Definition at line 1340 of file defBF534.h.
| #define EBUFE 0x02000000 /* Enable External Buffering Timing */ |
Definition at line 1330 of file defBF534.h.
| #define EMREN 0x10000000 /* Extended Mode Register Enable */ |
Definition at line 1332 of file defBF534.h.
| #define EMU_RUN 0x0200 /* Emulation Behavior Select */ |
Definition at line 1092 of file defBF534.h.
| #define ERR_DET 0x4000 /* Error Detected Indicator */ |
Definition at line 1403 of file defBF534.h.
| #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ |
Definition at line 1404 of file defBF534.h.
| #define ERR_TYP 0xC000 /* Error Type */ |
Definition at line 1093 of file defBF534.h.
| #define EXT_CLK 0x0003 /* External Clock Mode */ |
Definition at line 1084 of file defBF534.h.
| #define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ |
Definition at line 1331 of file defBF534.h.
| #define FLD 0x0400 /* Field Indicator */ |
Definition at line 1399 of file defBF534.h.
| #define FLD_SEL 0x0040 /* PPI Active Field Select */ |
Definition at line 1381 of file defBF534.h.
| #define FT_ERR 0x0800 /* Frame Track Error */ |
Definition at line 1400 of file defBF534.h.
| #define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ |
Definition at line 929 of file defBF534.h.
| #define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ |
Definition at line 933 of file defBF534.h.
| #define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ |
Definition at line 927 of file defBF534.h.
| #define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ |
Definition at line 928 of file defBF534.h.
| #define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ |
Definition at line 932 of file defBF534.h.
| #define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ |
Definition at line 931 of file defBF534.h.
| #define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */ |
Definition at line 930 of file defBF534.h.
| #define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ |
Definition at line 937 of file defBF534.h.
| #define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ |
Definition at line 941 of file defBF534.h.
| #define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ |
Definition at line 935 of file defBF534.h.
| #define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ |
Definition at line 936 of file defBF534.h.
| #define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ |
Definition at line 940 of file defBF534.h.
| #define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ |
Definition at line 939 of file defBF534.h.
| #define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */ |
Definition at line 938 of file defBF534.h.
| #define IRQ_ENA 0x0010 /* Interrupt Request Enable */ |
Definition at line 1087 of file defBF534.h.
| #define IWR_DISABLE | ( | x | ) | (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ |
Definition at line 1023 of file defBF534.h.
| #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ |
Definition at line 1020 of file defBF534.h.
Definition at line 1022 of file defBF534.h.
| #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ |
Definition at line 1021 of file defBF534.h.
| #define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ |
Definition at line 367 of file defBF534.h.
| #define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ |
Definition at line 373 of file defBF534.h.
| #define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ |
Definition at line 372 of file defBF534.h.
| #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ |
Definition at line 376 of file defBF534.h.
| #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ |
Definition at line 377 of file defBF534.h.
| #define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ |
Definition at line 374 of file defBF534.h.
| #define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ |
Definition at line 365 of file defBF534.h.
| #define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ |
Definition at line 375 of file defBF534.h.
| #define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ |
Definition at line 366 of file defBF534.h.
| #define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ |
Definition at line 368 of file defBF534.h.
| #define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ |
Definition at line 369 of file defBF534.h.
| #define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ |
Definition at line 370 of file defBF534.h.
| #define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ |
Definition at line 371 of file defBF534.h.
| #define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ |
Definition at line 395 of file defBF534.h.
| #define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ |
Definition at line 401 of file defBF534.h.
| #define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ |
Definition at line 400 of file defBF534.h.
| #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ |
Definition at line 404 of file defBF534.h.
| #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ |
Definition at line 405 of file defBF534.h.
| #define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ |
Definition at line 402 of file defBF534.h.
| #define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ |
Definition at line 393 of file defBF534.h.
| #define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ |
Definition at line 403 of file defBF534.h.
| #define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ |
Definition at line 394 of file defBF534.h.
| #define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ |
Definition at line 396 of file defBF534.h.
| #define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ |
Definition at line 397 of file defBF534.h.
| #define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ |
Definition at line 398 of file defBF534.h.
| #define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ |
Definition at line 399 of file defBF534.h.
| #define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ |
Definition at line 381 of file defBF534.h.
| #define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ |
Definition at line 387 of file defBF534.h.
| #define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ |
Definition at line 386 of file defBF534.h.
| #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ |
Definition at line 390 of file defBF534.h.
| #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ |
Definition at line 391 of file defBF534.h.
| #define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ |
Definition at line 388 of file defBF534.h.
| #define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ |
Definition at line 379 of file defBF534.h.
| #define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ |
Definition at line 389 of file defBF534.h.
| #define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ |
Definition at line 380 of file defBF534.h.
| #define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ |
Definition at line 382 of file defBF534.h.
| #define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ |
Definition at line 383 of file defBF534.h.
| #define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ |
Definition at line 384 of file defBF534.h.
| #define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ |
Definition at line 385 of file defBF534.h.
| #define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ |
Definition at line 409 of file defBF534.h.
| #define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ |
Definition at line 415 of file defBF534.h.
| #define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ |
Definition at line 414 of file defBF534.h.
| #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ |
Definition at line 418 of file defBF534.h.
| #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ |
Definition at line 419 of file defBF534.h.
| #define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ |
Definition at line 416 of file defBF534.h.
| #define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ |
Definition at line 407 of file defBF534.h.
| #define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ |
Definition at line 417 of file defBF534.h.
| #define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ |
Definition at line 408 of file defBF534.h.
| #define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ |
Definition at line 410 of file defBF534.h.
| #define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ |
Definition at line 411 of file defBF534.h.
| #define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ |
Definition at line 412 of file defBF534.h.
| #define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ |
Definition at line 413 of file defBF534.h.
| #define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ |
Definition at line 969 of file defBF534.h.
| #define OUT_DIS 0x0040 /* Output Pad Disable */ |
Definition at line 1089 of file defBF534.h.
| #define OVR 0x1000 /* FIFO Overflow Error */ |
Definition at line 1401 of file defBF534.h.
Definition at line 974 of file defBF534.h.
Definition at line 986 of file defBF534.h.
Definition at line 987 of file defBF534.h.
Definition at line 988 of file defBF534.h.
Definition at line 989 of file defBF534.h.
Definition at line 990 of file defBF534.h.
Definition at line 991 of file defBF534.h.
Definition at line 994 of file defBF534.h.
Definition at line 995 of file defBF534.h.
Definition at line 996 of file defBF534.h.
Definition at line 997 of file defBF534.h.
Definition at line 975 of file defBF534.h.
Definition at line 998 of file defBF534.h.
Definition at line 999 of file defBF534.h.
Definition at line 1000 of file defBF534.h.
Definition at line 1001 of file defBF534.h.
Definition at line 1004 of file defBF534.h.
Definition at line 1005 of file defBF534.h.
Definition at line 1006 of file defBF534.h.
Definition at line 1007 of file defBF534.h.
Definition at line 1008 of file defBF534.h.
Definition at line 1009 of file defBF534.h.
Definition at line 976 of file defBF534.h.
Definition at line 1010 of file defBF534.h.
Definition at line 1011 of file defBF534.h.
Definition at line 977 of file defBF534.h.
Definition at line 978 of file defBF534.h.
Definition at line 979 of file defBF534.h.
Definition at line 980 of file defBF534.h.
Definition at line 981 of file defBF534.h.
Definition at line 984 of file defBF534.h.
Definition at line 985 of file defBF534.h.
| #define PACK_EN 0x0080 /* PPI Packing Mode */ |
Definition at line 1382 of file defBF534.h.
| #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ |
Definition at line 1291 of file defBF534.h.
| #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ |
Definition at line 1293 of file defBF534.h.
| #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ |
Definition at line 1292 of file defBF534.h.
| #define PERIOD_CNT 0x0008 /* Period Count */ |
Definition at line 1086 of file defBF534.h.
| #define PFDE 0x0008 /* Port F DMA Request Enable */ |
Definition at line 1418 of file defBF534.h.
| #define PFDE_DMA 0x0008 /* Enable DMAR1:0 */ |
Definition at line 1420 of file defBF534.h.
| #define PFDE_UART 0x0000 /* Enable UART0 RX/TX */ |
Definition at line 1419 of file defBF534.h.
| #define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ |
Definition at line 1438 of file defBF534.h.
| #define PFFE_PPI 0x0100 /* Enable PPI FS3 */ |
Definition at line 1440 of file defBF534.h.
| #define PFFE_TIMER 0x0000 /* Enable TMR2 */ |
Definition at line 1439 of file defBF534.h.
| #define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ |
Definition at line 1434 of file defBF534.h.
| #define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ |
Definition at line 1436 of file defBF534.h.
| #define PFS4E_TIMER 0x0000 /* Enable TMR3 */ |
Definition at line 1435 of file defBF534.h.
| #define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ |
Definition at line 1430 of file defBF534.h.
| #define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ |
Definition at line 1432 of file defBF534.h.
| #define PFS5E_TIMER 0x0000 /* Enable TMR4 */ |
Definition at line 1431 of file defBF534.h.
| #define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ |
Definition at line 1426 of file defBF534.h.
| #define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ |
Definition at line 1428 of file defBF534.h.
| #define PFS6E_TIMER 0x0000 /* Enable TMR5 */ |
Definition at line 1427 of file defBF534.h.
| #define PFTE 0x0010 /* Port F Timer Enable */ |
Definition at line 1422 of file defBF534.h.
| #define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ |
Definition at line 1424 of file defBF534.h.
| #define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ |
Definition at line 1423 of file defBF534.h.
| #define PGDE_DMA PFDE_DMA |
Definition at line 1468 of file defBF534.h.
| #define PGDE_UART PFDE_UART |
Definition at line 1467 of file defBF534.h.
| #define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ |
Definition at line 1446 of file defBF534.h.
| #define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ |
Definition at line 1447 of file defBF534.h.
| #define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ |
Definition at line 1448 of file defBF534.h.
| #define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ |
Definition at line 1442 of file defBF534.h.
| #define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ |
Definition at line 1443 of file defBF534.h.
| #define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ |
Definition at line 1444 of file defBF534.h.
| #define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ |
Definition at line 1450 of file defBF534.h.
| #define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ |
Definition at line 1451 of file defBF534.h.
| #define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ |
Definition at line 1452 of file defBF534.h.
Definition at line 1413 of file defBF534.h.
| #define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ |
Definition at line 1415 of file defBF534.h.
| #define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ |
Definition at line 1416 of file defBF534.h.
| #define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ |
Definition at line 1414 of file defBF534.h.
| #define PJSE 0x0001 /* Port J SPI/SPORT Enable */ |
Definition at line 1409 of file defBF534.h.
| #define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ |
Definition at line 1411 of file defBF534.h.
| #define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ |
Definition at line 1410 of file defBF534.h.
| #define PLL_CTL 0xFFC00000 /* PLL Control Register */ |
Definition at line 14 of file defBF534.h.
| #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ |
Definition at line 15 of file defBF534.h.
| #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ |
Definition at line 18 of file defBF534.h.
| #define PLL_STAT 0xFFC0000C /* PLL Status Register */ |
Definition at line 17 of file defBF534.h.
| #define PMAP 0xF000 /* Peripheral Mapped To This Channel */ |
Definition at line 1361 of file defBF534.h.
| #define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ |
Definition at line 1363 of file defBF534.h.
| #define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ |
Definition at line 1364 of file defBF534.h.
| #define PMAP_PPI 0x0000 /* PPI Port DMA */ |
Definition at line 1362 of file defBF534.h.
| #define PMAP_SPI 0x7000 /* SPI Port DMA */ |
Definition at line 1369 of file defBF534.h.
| #define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ |
Definition at line 1365 of file defBF534.h.
| #define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ |
Definition at line 1366 of file defBF534.h.
| #define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ |
Definition at line 1367 of file defBF534.h.
| #define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ |
Definition at line 1368 of file defBF534.h.
| #define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ |
Definition at line 1370 of file defBF534.h.
| #define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ |
Definition at line 1371 of file defBF534.h.
| #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ |
Definition at line 1372 of file defBF534.h.
| #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ |
Definition at line 1373 of file defBF534.h.
| #define POLC 0x4000 /* PPI Clock Polarity */ |
Definition at line 1395 of file defBF534.h.
| #define POLS 0x8000 /* PPI Frame Sync Polarity */ |
Definition at line 1396 of file defBF534.h.
| #define PORT_CFG 0x0030 /* PPI Port Configuration */ |
Definition at line 1380 of file defBF534.h.
| #define PORT_DIR 0x0002 /* PPI Port Direction */ |
Definition at line 1378 of file defBF534.h.
| #define PORT_EN 0x0001 /* PPI Port Enable */ |
Definition at line 1377 of file defBF534.h.
| #define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ |
Definition at line 921 of file defBF534.h.
| #define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ |
Definition at line 117 of file defBF534.h.
| #define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ |
Definition at line 132 of file defBF534.h.
| #define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ |
Definition at line 118 of file defBF534.h.
| #define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ |
Definition at line 129 of file defBF534.h.
| #define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ |
Definition at line 131 of file defBF534.h.
| #define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ |
Definition at line 133 of file defBF534.h.
| #define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ |
Definition at line 121 of file defBF534.h.
| #define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ |
Definition at line 122 of file defBF534.h.
| #define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ |
Definition at line 123 of file defBF534.h.
| #define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ |
Definition at line 124 of file defBF534.h.
| #define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ |
Definition at line 125 of file defBF534.h.
| #define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ |
Definition at line 126 of file defBF534.h.
| #define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ |
Definition at line 127 of file defBF534.h.
| #define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ |
Definition at line 128 of file defBF534.h.
| #define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ |
Definition at line 130 of file defBF534.h.
| #define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ |
Definition at line 119 of file defBF534.h.
| #define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ |
Definition at line 120 of file defBF534.h.
| #define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ |
Definition at line 922 of file defBF534.h.
| #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ |
Definition at line 448 of file defBF534.h.
| #define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ |
Definition at line 463 of file defBF534.h.
| #define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ |
Definition at line 449 of file defBF534.h.
| #define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ |
Definition at line 460 of file defBF534.h.
| #define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ |
Definition at line 462 of file defBF534.h.
| #define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ |
Definition at line 464 of file defBF534.h.
| #define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ |
Definition at line 452 of file defBF534.h.
| #define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ |
Definition at line 453 of file defBF534.h.
| #define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ |
Definition at line 454 of file defBF534.h.
| #define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ |
Definition at line 455 of file defBF534.h.
| #define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ |
Definition at line 456 of file defBF534.h.
| #define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ |
Definition at line 457 of file defBF534.h.
| #define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ |
Definition at line 458 of file defBF534.h.
| #define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ |
Definition at line 459 of file defBF534.h.
| #define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ |
Definition at line 461 of file defBF534.h.
| #define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ |
Definition at line 450 of file defBF534.h.
| #define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ |
Definition at line 451 of file defBF534.h.
| #define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ |
Definition at line 923 of file defBF534.h.
| #define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ |
Definition at line 467 of file defBF534.h.
| #define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ |
Definition at line 482 of file defBF534.h.
| #define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ |
Definition at line 468 of file defBF534.h.
| #define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ |
Definition at line 479 of file defBF534.h.
| #define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ |
Definition at line 481 of file defBF534.h.
| #define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ |
Definition at line 483 of file defBF534.h.
| #define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ |
Definition at line 471 of file defBF534.h.
| #define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ |
Definition at line 472 of file defBF534.h.
| #define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ |
Definition at line 473 of file defBF534.h.
| #define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ |
Definition at line 474 of file defBF534.h.
| #define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ |
Definition at line 475 of file defBF534.h.
| #define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ |
Definition at line 476 of file defBF534.h.
| #define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ |
Definition at line 477 of file defBF534.h.
| #define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ |
Definition at line 478 of file defBF534.h.
| #define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ |
Definition at line 480 of file defBF534.h.
| #define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ |
Definition at line 469 of file defBF534.h.
| #define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ |
Definition at line 470 of file defBF534.h.
| #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ |
Definition at line 422 of file defBF534.h.
| #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ |
Definition at line 424 of file defBF534.h.
| #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ |
Definition at line 425 of file defBF534.h.
| #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ |
Definition at line 426 of file defBF534.h.
| #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ |
Definition at line 423 of file defBF534.h.
| #define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ |
Definition at line 1327 of file defBF534.h.
| #define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ |
Definition at line 1328 of file defBF534.h.
| #define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ |
Definition at line 1085 of file defBF534.h.
| #define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ |
Definition at line 1326 of file defBF534.h.
| #define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ |
Definition at line 1082 of file defBF534.h.
| #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ |
Definition at line 963 of file defBF534.h.
| #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ |
Definition at line 965 of file defBF534.h.
| #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ |
Definition at line 964 of file defBF534.h.
| #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ |
Definition at line 43 of file defBF534.h.
| #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ |
Definition at line 44 of file defBF534.h.
| #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ |
Definition at line 40 of file defBF534.h.
| #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ |
Definition at line 41 of file defBF534.h.
| #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ |
Definition at line 45 of file defBF534.h.
| #define RTC_STAT 0xFFC00300 /* RTC Status Register */ |
Definition at line 39 of file defBF534.h.
| #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ |
Definition at line 42 of file defBF534.h.
| #define SCTLE 0x00000001 /* Enable SDRAM Signals */ |
Definition at line 1288 of file defBF534.h.
| #define SDCI 0x0001 /* SDRAM Controller Idle */ |
Definition at line 1350 of file defBF534.h.
| #define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ |
Definition at line 1354 of file defBF534.h.
| #define SDPUA 0x0004 /* SDRAM Power-Up Active */ |
Definition at line 1352 of file defBF534.h.
| #define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ |
Definition at line 1353 of file defBF534.h.
| #define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ |
Definition at line 1351 of file defBF534.h.
| #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ |
Definition at line 26 of file defBF534.h.
| #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ |
Definition at line 27 of file defBF534.h.
| #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ |
Definition at line 28 of file defBF534.h.
| #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ |
Definition at line 29 of file defBF534.h.
| #define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ |
Definition at line 25 of file defBF534.h.
| #define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ |
Definition at line 30 of file defBF534.h.
| #define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ |
Definition at line 31 of file defBF534.h.
Definition at line 1016 of file defBF534.h.
| #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ |
Definition at line 1015 of file defBF534.h.
| #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ |
Definition at line 24 of file defBF534.h.
| #define SIC_UNMASK | ( | x | ) | (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ |
Definition at line 1017 of file defBF534.h.
| #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ |
Definition at line 1014 of file defBF534.h.
| #define SKIP_EN 0x0200 /* PPI Skip Element Enable */ |
Definition at line 1384 of file defBF534.h.
| #define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ |
Definition at line 1385 of file defBF534.h.
| #define SPI0_REGBASE 0xFFC00500 |
Definition at line 62 of file defBF534.h.
| #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ |
Definition at line 68 of file defBF534.h.
| #define SPI_CTL 0xFFC00500 /* SPI Control Register */ |
Definition at line 63 of file defBF534.h.
| #define SPI_FLG 0xFFC00504 /* SPI Flag register */ |
Definition at line 64 of file defBF534.h.
| #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ |
Definition at line 67 of file defBF534.h.
| #define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ |
Definition at line 69 of file defBF534.h.
| #define SPI_STAT 0xFFC00508 /* SPI Status register */ |
Definition at line 65 of file defBF534.h.
| #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ |
Definition at line 66 of file defBF534.h.
| #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ |
Definition at line 147 of file defBF534.h.
| #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ |
Definition at line 148 of file defBF534.h.
| #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ |
Definition at line 149 of file defBF534.h.
| #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ |
Definition at line 154 of file defBF534.h.
| #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ |
Definition at line 155 of file defBF534.h.
| #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ |
Definition at line 156 of file defBF534.h.
| #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ |
Definition at line 157 of file defBF534.h.
| #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ |
Definition at line 150 of file defBF534.h.
| #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ |
Definition at line 151 of file defBF534.h.
| #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ |
Definition at line 152 of file defBF534.h.
| #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ |
Definition at line 153 of file defBF534.h.
| #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ |
Definition at line 144 of file defBF534.h.
| #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ |
Definition at line 142 of file defBF534.h.
| #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ |
Definition at line 143 of file defBF534.h.
| #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ |
Definition at line 145 of file defBF534.h.
| #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ |
Definition at line 141 of file defBF534.h.
| #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ |
Definition at line 146 of file defBF534.h.
| #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ |
Definition at line 138 of file defBF534.h.
| #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ |
Definition at line 136 of file defBF534.h.
| #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ |
Definition at line 137 of file defBF534.h.
| #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ |
Definition at line 139 of file defBF534.h.
| #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ |
Definition at line 140 of file defBF534.h.
| #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ |
Definition at line 171 of file defBF534.h.
| #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ |
Definition at line 172 of file defBF534.h.
| #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ |
Definition at line 173 of file defBF534.h.
| #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ |
Definition at line 178 of file defBF534.h.
| #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ |
Definition at line 179 of file defBF534.h.
| #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ |
Definition at line 180 of file defBF534.h.
| #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ |
Definition at line 181 of file defBF534.h.
| #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ |
Definition at line 174 of file defBF534.h.
| #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ |
Definition at line 175 of file defBF534.h.
| #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ |
Definition at line 176 of file defBF534.h.
| #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ |
Definition at line 177 of file defBF534.h.
| #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ |
Definition at line 168 of file defBF534.h.
| #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ |
Definition at line 166 of file defBF534.h.
| #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ |
Definition at line 167 of file defBF534.h.
| #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ |
Definition at line 169 of file defBF534.h.
| #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ |
Definition at line 165 of file defBF534.h.
| #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ |
Definition at line 170 of file defBF534.h.
| #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ |
Definition at line 162 of file defBF534.h.
| #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ |
Definition at line 160 of file defBF534.h.
| #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ |
Definition at line 161 of file defBF534.h.
| #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ |
Definition at line 163 of file defBF534.h.
| #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ |
Definition at line 164 of file defBF534.h.
| #define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ |
Definition at line 1329 of file defBF534.h.
| #define SWRST 0xFFC00100 /* Software Reset Register */ |
Definition at line 22 of file defBF534.h.
| #define SYSCR 0xFFC00104 /* System Configuration Register */ |
Definition at line 23 of file defBF534.h.
| #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ |
Definition at line 961 of file defBF534.h.
| #define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ |
Definition at line 1333 of file defBF534.h.
Definition at line 1037 of file defBF534.h.
Definition at line 1038 of file defBF534.h.
Definition at line 1039 of file defBF534.h.
Definition at line 1040 of file defBF534.h.
Definition at line 1041 of file defBF534.h.
Definition at line 1042 of file defBF534.h.
Definition at line 1043 of file defBF534.h.
Definition at line 1044 of file defBF534.h.
| #define TIMEN0 0x0001 /* Enable Timer 0 */ |
Definition at line 1027 of file defBF534.h.
| #define TIMEN1 0x0002 /* Enable Timer 1 */ |
Definition at line 1028 of file defBF534.h.
| #define TIMEN2 0x0004 /* Enable Timer 2 */ |
Definition at line 1029 of file defBF534.h.
| #define TIMEN3 0x0008 /* Enable Timer 3 */ |
Definition at line 1030 of file defBF534.h.
| #define TIMEN4 0x0010 /* Enable Timer 4 */ |
Definition at line 1031 of file defBF534.h.
| #define TIMEN5 0x0020 /* Enable Timer 5 */ |
Definition at line 1032 of file defBF534.h.
| #define TIMEN6 0x0040 /* Enable Timer 6 */ |
Definition at line 1033 of file defBF534.h.
| #define TIMEN7 0x0080 /* Enable Timer 7 */ |
Definition at line 1034 of file defBF534.h.
| #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ |
Definition at line 72 of file defBF534.h.
| #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ |
Definition at line 73 of file defBF534.h.
| #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ |
Definition at line 74 of file defBF534.h.
| #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ |
Definition at line 75 of file defBF534.h.
| #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ |
Definition at line 77 of file defBF534.h.
| #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ |
Definition at line 78 of file defBF534.h.
| #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ |
Definition at line 79 of file defBF534.h.
| #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ |
Definition at line 80 of file defBF534.h.
| #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ |
Definition at line 82 of file defBF534.h.
| #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ |
Definition at line 83 of file defBF534.h.
| #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ |
Definition at line 84 of file defBF534.h.
| #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ |
Definition at line 85 of file defBF534.h.
| #define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ |
Definition at line 87 of file defBF534.h.
| #define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ |
Definition at line 88 of file defBF534.h.
| #define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ |
Definition at line 89 of file defBF534.h.
| #define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ |
Definition at line 90 of file defBF534.h.
| #define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ |
Definition at line 92 of file defBF534.h.
| #define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ |
Definition at line 93 of file defBF534.h.
| #define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ |
Definition at line 94 of file defBF534.h.
| #define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ |
Definition at line 95 of file defBF534.h.
| #define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ |
Definition at line 97 of file defBF534.h.
| #define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ |
Definition at line 98 of file defBF534.h.
| #define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ |
Definition at line 99 of file defBF534.h.
| #define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ |
Definition at line 100 of file defBF534.h.
| #define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ |
Definition at line 102 of file defBF534.h.
| #define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ |
Definition at line 103 of file defBF534.h.
| #define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ |
Definition at line 104 of file defBF534.h.
| #define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ |
Definition at line 105 of file defBF534.h.
| #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ |
Definition at line 107 of file defBF534.h.
| #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ |
Definition at line 108 of file defBF534.h.
| #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ |
Definition at line 109 of file defBF534.h.
| #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ |
Definition at line 110 of file defBF534.h.
| #define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ |
Definition at line 113 of file defBF534.h.
| #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ |
Definition at line 112 of file defBF534.h.
| #define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ |
Definition at line 114 of file defBF534.h.
| #define TIMIL0 0x00000001 /* Timer 0 Interrupt */ |
Definition at line 1047 of file defBF534.h.
| #define TIMIL1 0x00000002 /* Timer 1 Interrupt */ |
Definition at line 1048 of file defBF534.h.
| #define TIMIL2 0x00000004 /* Timer 2 Interrupt */ |
Definition at line 1049 of file defBF534.h.
| #define TIMIL3 0x00000008 /* Timer 3 Interrupt */ |
Definition at line 1050 of file defBF534.h.
| #define TIMIL4 0x00010000 /* Timer 4 Interrupt */ |
Definition at line 1059 of file defBF534.h.
| #define TIMIL5 0x00020000 /* Timer 5 Interrupt */ |
Definition at line 1060 of file defBF534.h.
| #define TIMIL6 0x00040000 /* Timer 6 Interrupt */ |
Definition at line 1061 of file defBF534.h.
| #define TIMIL7 0x00080000 /* Timer 7 Interrupt */ |
Definition at line 1062 of file defBF534.h.
| #define TIN_SEL 0x0020 /* Timer Input Select */ |
Definition at line 1088 of file defBF534.h.
| #define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ |
Definition at line 1091 of file defBF534.h.
| #define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ |
Definition at line 1051 of file defBF534.h.
| #define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ |
Definition at line 1052 of file defBF534.h.
| #define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ |
Definition at line 1053 of file defBF534.h.
| #define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ |
Definition at line 1054 of file defBF534.h.
| #define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ |
Definition at line 1063 of file defBF534.h.
| #define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ |
Definition at line 1064 of file defBF534.h.
| #define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ |
Definition at line 1065 of file defBF534.h.
| #define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ |
Definition at line 1066 of file defBF534.h.
| #define TOVL_ERR0 TOVF_ERR0 |
Definition at line 1073 of file defBF534.h.
| #define TOVL_ERR1 TOVF_ERR1 |
Definition at line 1074 of file defBF534.h.
| #define TOVL_ERR2 TOVF_ERR2 |
Definition at line 1075 of file defBF534.h.
| #define TOVL_ERR3 TOVF_ERR3 |
Definition at line 1076 of file defBF534.h.
| #define TOVL_ERR4 TOVF_ERR4 |
Definition at line 1077 of file defBF534.h.
| #define TOVL_ERR5 TOVF_ERR5 |
Definition at line 1078 of file defBF534.h.
| #define TOVL_ERR6 TOVF_ERR6 |
Definition at line 1079 of file defBF534.h.
| #define TOVL_ERR7 TOVF_ERR7 |
Definition at line 1080 of file defBF534.h.
| #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ |
Definition at line 1294 of file defBF534.h.
| #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ |
Definition at line 1303 of file defBF534.h.
| #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ |
Definition at line 1304 of file defBF534.h.
| #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ |
Definition at line 1305 of file defBF534.h.
| #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ |
Definition at line 1306 of file defBF534.h.
| #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ |
Definition at line 1307 of file defBF534.h.
| #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ |
Definition at line 1308 of file defBF534.h.
| #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ |
Definition at line 1295 of file defBF534.h.
| #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ |
Definition at line 1296 of file defBF534.h.
| #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ |
Definition at line 1297 of file defBF534.h.
| #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ |
Definition at line 1298 of file defBF534.h.
| #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ |
Definition at line 1299 of file defBF534.h.
| #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ |
Definition at line 1300 of file defBF534.h.
| #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ |
Definition at line 1301 of file defBF534.h.
| #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ |
Definition at line 1302 of file defBF534.h.
| #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ |
Definition at line 1316 of file defBF534.h.
| #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ |
Definition at line 1317 of file defBF534.h.
| #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ |
Definition at line 1318 of file defBF534.h.
| #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ |
Definition at line 1319 of file defBF534.h.
| #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ |
Definition at line 1320 of file defBF534.h.
| #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ |
Definition at line 1321 of file defBF534.h.
| #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ |
Definition at line 1322 of file defBF534.h.
| #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ |
Definition at line 1309 of file defBF534.h.
| #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ |
Definition at line 1310 of file defBF534.h.
| #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ |
Definition at line 1311 of file defBF534.h.
| #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ |
Definition at line 1312 of file defBF534.h.
| #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ |
Definition at line 1313 of file defBF534.h.
| #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ |
Definition at line 1314 of file defBF534.h.
| #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ |
Definition at line 1315 of file defBF534.h.
| #define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ |
Definition at line 1055 of file defBF534.h.
| #define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ |
Definition at line 1056 of file defBF534.h.
| #define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ |
Definition at line 1057 of file defBF534.h.
| #define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ |
Definition at line 1058 of file defBF534.h.
| #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ |
Definition at line 1067 of file defBF534.h.
| #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ |
Definition at line 1068 of file defBF534.h.
| #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ |
Definition at line 1069 of file defBF534.h.
| #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ |
Definition at line 1070 of file defBF534.h.
| #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
Definition at line 430 of file defBF534.h.
| #define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */ |
Definition at line 431 of file defBF534.h.
| #define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ |
Definition at line 440 of file defBF534.h.
| #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ |
Definition at line 441 of file defBF534.h.
| #define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ |
Definition at line 439 of file defBF534.h.
| #define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ |
Definition at line 438 of file defBF534.h.
| #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ |
Definition at line 437 of file defBF534.h.
| #define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ |
Definition at line 435 of file defBF534.h.
| #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ |
Definition at line 436 of file defBF534.h.
| #define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ |
Definition at line 445 of file defBF534.h.
| #define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ |
Definition at line 444 of file defBF534.h.
| #define TWI0_REGBASE 0xFFC01400 |
Definition at line 429 of file defBF534.h.
| #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ |
Definition at line 434 of file defBF534.h.
| #define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ |
Definition at line 432 of file defBF534.h.
| #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ |
Definition at line 433 of file defBF534.h.
| #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ |
Definition at line 443 of file defBF534.h.
| #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ |
Definition at line 442 of file defBF534.h.
| #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ |
Definition at line 1323 of file defBF534.h.
| #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ |
Definition at line 1324 of file defBF534.h.
| #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ |
Definition at line 1325 of file defBF534.h.
| #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ |
Definition at line 52 of file defBF534.h.
| #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ |
Definition at line 50 of file defBF534.h.
| #define UART0_GCTL 0xFFC00424 /* Global Control Register */ |
Definition at line 59 of file defBF534.h.
| #define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ |
Definition at line 51 of file defBF534.h.
| #define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ |
Definition at line 53 of file defBF534.h.
| #define UART0_LCR 0xFFC0040C /* Line Control Register */ |
Definition at line 54 of file defBF534.h.
| #define UART0_LSR 0xFFC00414 /* Line Status Register */ |
Definition at line 56 of file defBF534.h.
| #define UART0_MCR 0xFFC00410 /* Modem Control Register */ |
Definition at line 55 of file defBF534.h.
| #define UART0_MSR 0xFFC00418 /* Modem Status Register */ |
Definition at line 57 of file defBF534.h.
| #define UART0_RBR 0xFFC00400 /* Receive Buffer register */ |
Definition at line 49 of file defBF534.h.
| #define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ |
Definition at line 58 of file defBF534.h.
| #define UART0_THR 0xFFC00400 /* Transmit Holding register */ |
Definition at line 48 of file defBF534.h.
| #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ |
Definition at line 490 of file defBF534.h.
| #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ |
Definition at line 488 of file defBF534.h.
| #define UART1_GCTL 0xFFC02024 /* Global Control Register */ |
Definition at line 497 of file defBF534.h.
| #define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ |
Definition at line 489 of file defBF534.h.
| #define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ |
Definition at line 491 of file defBF534.h.
| #define UART1_LCR 0xFFC0200C /* Line Control Register */ |
Definition at line 492 of file defBF534.h.
| #define UART1_LSR 0xFFC02014 /* Line Status Register */ |
Definition at line 494 of file defBF534.h.
| #define UART1_MCR 0xFFC02010 /* Modem Control Register */ |
Definition at line 493 of file defBF534.h.
| #define UART1_MSR 0xFFC02018 /* Modem Status Register */ |
Definition at line 495 of file defBF534.h.
| #define UART1_RBR 0xFFC02000 /* Receive Buffer register */ |
Definition at line 487 of file defBF534.h.
| #define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ |
Definition at line 496 of file defBF534.h.
| #define UART1_THR 0xFFC02000 /* Transmit Holding register */ |
Definition at line 486 of file defBF534.h.
| #define UNDR 0x2000 /* FIFO Underrun Error */ |
Definition at line 1402 of file defBF534.h.
| #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ |
Definition at line 16 of file defBF534.h.
| #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ |
Definition at line 35 of file defBF534.h.
| #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ |
Definition at line 34 of file defBF534.h.
| #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ |
Definition at line 36 of file defBF534.h.
| #define WDTH_CAP 0x0002 /* Width Capture Input Mode */ |
Definition at line 1083 of file defBF534.h.
| #define XFR_TYPE 0x000C /* PPI Transfer Type */ |
Definition at line 1379 of file defBF534.h.
1.8.2