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Macros
defBF54x_base.h File Reference

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Macros

#define PLL_CTL   0xffc00000 /* PLL Control Register */
 
#define PLL_DIV   0xffc00004 /* PLL Divisor Register */
 
#define VR_CTL   0xffc00008 /* Voltage Regulator Control Register */
 
#define PLL_STAT   0xffc0000c /* PLL Status Register */
 
#define PLL_LOCKCNT   0xffc00010 /* PLL Lock Count Register */
 
#define CHIPID   0xffc00014
 
#define CHIPID_VERSION   0xF0000000
 
#define CHIPID_FAMILY   0x0FFFF000
 
#define CHIPID_MANUFACTURE   0x00000FFE
 
#define SWRST   0xffc00100 /* Software Reset Register */
 
#define SYSCR   0xffc00104 /* System Configuration register */
 
#define SIC_RVECT   0xffc00108
 
#define SIC_IMASK0   0xffc0010c /* System Interrupt Mask Register 0 */
 
#define SIC_IMASK1   0xffc00110 /* System Interrupt Mask Register 1 */
 
#define SIC_IMASK2   0xffc00114 /* System Interrupt Mask Register 2 */
 
#define SIC_ISR0   0xffc00118 /* System Interrupt Status Register 0 */
 
#define SIC_ISR1   0xffc0011c /* System Interrupt Status Register 1 */
 
#define SIC_ISR2   0xffc00120 /* System Interrupt Status Register 2 */
 
#define SIC_IWR0   0xffc00124 /* System Interrupt Wakeup Register 0 */
 
#define SIC_IWR1   0xffc00128 /* System Interrupt Wakeup Register 1 */
 
#define SIC_IWR2   0xffc0012c /* System Interrupt Wakeup Register 2 */
 
#define SIC_IAR0   0xffc00130 /* System Interrupt Assignment Register 0 */
 
#define SIC_IAR1   0xffc00134 /* System Interrupt Assignment Register 1 */
 
#define SIC_IAR2   0xffc00138 /* System Interrupt Assignment Register 2 */
 
#define SIC_IAR3   0xffc0013c /* System Interrupt Assignment Register 3 */
 
#define SIC_IAR4   0xffc00140 /* System Interrupt Assignment Register 4 */
 
#define SIC_IAR5   0xffc00144 /* System Interrupt Assignment Register 5 */
 
#define SIC_IAR6   0xffc00148 /* System Interrupt Assignment Register 6 */
 
#define SIC_IAR7   0xffc0014c /* System Interrupt Assignment Register 7 */
 
#define SIC_IAR8   0xffc00150 /* System Interrupt Assignment Register 8 */
 
#define SIC_IAR9   0xffc00154 /* System Interrupt Assignment Register 9 */
 
#define SIC_IAR10   0xffc00158 /* System Interrupt Assignment Register 10 */
 
#define SIC_IAR11   0xffc0015c /* System Interrupt Assignment Register 11 */
 
#define WDOG_CTL   0xffc00200 /* Watchdog Control Register */
 
#define WDOG_CNT   0xffc00204 /* Watchdog Count Register */
 
#define WDOG_STAT   0xffc00208 /* Watchdog Status Register */
 
#define RTC_STAT   0xffc00300 /* RTC Status Register */
 
#define RTC_ICTL   0xffc00304 /* RTC Interrupt Control Register */
 
#define RTC_ISTAT   0xffc00308 /* RTC Interrupt Status Register */
 
#define RTC_SWCNT   0xffc0030c /* RTC Stopwatch Count Register */
 
#define RTC_ALARM   0xffc00310 /* RTC Alarm Register */
 
#define RTC_PREN   0xffc00314 /* RTC Prescaler Enable Register */
 
#define UART0_DLL   0xffc00400 /* Divisor Latch Low Byte */
 
#define UART0_DLH   0xffc00404 /* Divisor Latch High Byte */
 
#define UART0_GCTL   0xffc00408 /* Global Control Register */
 
#define UART0_LCR   0xffc0040c /* Line Control Register */
 
#define UART0_MCR   0xffc00410 /* Modem Control Register */
 
#define UART0_LSR   0xffc00414 /* Line Status Register */
 
#define UART0_MSR   0xffc00418 /* Modem Status Register */
 
#define UART0_SCR   0xffc0041c /* Scratch Register */
 
#define UART0_IER_SET   0xffc00420 /* Interrupt Enable Register Set */
 
#define UART0_IER_CLEAR   0xffc00424 /* Interrupt Enable Register Clear */
 
#define UART0_THR   0xffc00428 /* Transmit Hold Register */
 
#define UART0_RBR   0xffc0042c /* Receive Buffer Register */
 
#define SPI0_REGBASE   0xffc00500
 
#define SPI0_CTL   0xffc00500 /* SPI0 Control Register */
 
#define SPI0_FLG   0xffc00504 /* SPI0 Flag Register */
 
#define SPI0_STAT   0xffc00508 /* SPI0 Status Register */
 
#define SPI0_TDBR   0xffc0050c /* SPI0 Transmit Data Buffer Register */
 
#define SPI0_RDBR   0xffc00510 /* SPI0 Receive Data Buffer Register */
 
#define SPI0_BAUD   0xffc00514 /* SPI0 Baud Rate Register */
 
#define SPI0_SHADOW   0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */
 
#define TWI0_REGBASE   0xffc00700
 
#define TWI0_CLKDIV   0xffc00700 /* Clock Divider Register */
 
#define TWI0_CONTROL   0xffc00704 /* TWI Control Register */
 
#define TWI0_SLAVE_CTL   0xffc00708 /* TWI Slave Mode Control Register */
 
#define TWI0_SLAVE_STAT   0xffc0070c /* TWI Slave Mode Status Register */
 
#define TWI0_SLAVE_ADDR   0xffc00710 /* TWI Slave Mode Address Register */
 
#define TWI0_MASTER_CTL   0xffc00714 /* TWI Master Mode Control Register */
 
#define TWI0_MASTER_STAT   0xffc00718 /* TWI Master Mode Status Register */
 
#define TWI0_MASTER_ADDR   0xffc0071c /* TWI Master Mode Address Register */
 
#define TWI0_INT_STAT   0xffc00720 /* TWI Interrupt Status Register */
 
#define TWI0_INT_MASK   0xffc00724 /* TWI Interrupt Mask Register */
 
#define TWI0_FIFO_CTL   0xffc00728 /* TWI FIFO Control Register */
 
#define TWI0_FIFO_STAT   0xffc0072c /* TWI FIFO Status Register */
 
#define TWI0_XMT_DATA8   0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
 
#define TWI0_XMT_DATA16   0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */
 
#define TWI0_RCV_DATA8   0xffc00788 /* TWI FIFO Receive Data Single Byte Register */
 
#define TWI0_RCV_DATA16   0xffc0078c /* TWI FIFO Receive Data Double Byte Register */
 
#define SPORT1_TCR1   0xffc00900 /* SPORT1 Transmit Configuration 1 Register */
 
#define SPORT1_TCR2   0xffc00904 /* SPORT1 Transmit Configuration 2 Register */
 
#define SPORT1_TCLKDIV   0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */
 
#define SPORT1_TFSDIV   0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */
 
#define SPORT1_TX   0xffc00910 /* SPORT1 Transmit Data Register */
 
#define SPORT1_RX   0xffc00918 /* SPORT1 Receive Data Register */
 
#define SPORT1_RCR1   0xffc00920 /* SPORT1 Receive Configuration 1 Register */
 
#define SPORT1_RCR2   0xffc00924 /* SPORT1 Receive Configuration 2 Register */
 
#define SPORT1_RCLKDIV   0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */
 
#define SPORT1_RFSDIV   0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */
 
#define SPORT1_STAT   0xffc00930 /* SPORT1 Status Register */
 
#define SPORT1_CHNL   0xffc00934 /* SPORT1 Current Channel Register */
 
#define SPORT1_MCMC1   0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */
 
#define SPORT1_MCMC2   0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */
 
#define SPORT1_MTCS0   0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */
 
#define SPORT1_MTCS1   0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */
 
#define SPORT1_MTCS2   0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */
 
#define SPORT1_MTCS3   0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */
 
#define SPORT1_MRCS0   0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */
 
#define SPORT1_MRCS1   0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */
 
#define SPORT1_MRCS2   0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */
 
#define SPORT1_MRCS3   0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */
 
#define EBIU_AMGCTL   0xffc00a00 /* Asynchronous Memory Global Control Register */
 
#define EBIU_AMBCTL0   0xffc00a04 /* Asynchronous Memory Bank Control Register */
 
#define EBIU_AMBCTL1   0xffc00a08 /* Asynchronous Memory Bank Control Register */
 
#define EBIU_MBSCTL   0xffc00a0c /* Asynchronous Memory Bank Select Control Register */
 
#define EBIU_ARBSTAT   0xffc00a10 /* Asynchronous Memory Arbiter Status Register */
 
#define EBIU_MODE   0xffc00a14 /* Asynchronous Mode Control Register */
 
#define EBIU_FCTL   0xffc00a18 /* Asynchronous Memory Flash Control Register */
 
#define EBIU_DDRCTL0   0xffc00a20 /* DDR Memory Control 0 Register */
 
#define EBIU_DDRCTL1   0xffc00a24 /* DDR Memory Control 1 Register */
 
#define EBIU_DDRCTL2   0xffc00a28 /* DDR Memory Control 2 Register */
 
#define EBIU_DDRCTL3   0xffc00a2c /* DDR Memory Control 3 Register */
 
#define EBIU_DDRQUE   0xffc00a30 /* DDR Queue Configuration Register */
 
#define EBIU_ERRADD   0xffc00a34 /* DDR Error Address Register */
 
#define EBIU_ERRMST   0xffc00a38 /* DDR Error Master Register */
 
#define EBIU_RSTCTL   0xffc00a3c /* DDR Reset Control Register */
 
#define EBIU_DDRBRC0   0xffc00a60 /* DDR Bank0 Read Count Register */
 
#define EBIU_DDRBRC1   0xffc00a64 /* DDR Bank1 Read Count Register */
 
#define EBIU_DDRBRC2   0xffc00a68 /* DDR Bank2 Read Count Register */
 
#define EBIU_DDRBRC3   0xffc00a6c /* DDR Bank3 Read Count Register */
 
#define EBIU_DDRBRC4   0xffc00a70 /* DDR Bank4 Read Count Register */
 
#define EBIU_DDRBRC5   0xffc00a74 /* DDR Bank5 Read Count Register */
 
#define EBIU_DDRBRC6   0xffc00a78 /* DDR Bank6 Read Count Register */
 
#define EBIU_DDRBRC7   0xffc00a7c /* DDR Bank7 Read Count Register */
 
#define EBIU_DDRBWC0   0xffc00a80 /* DDR Bank0 Write Count Register */
 
#define EBIU_DDRBWC1   0xffc00a84 /* DDR Bank1 Write Count Register */
 
#define EBIU_DDRBWC2   0xffc00a88 /* DDR Bank2 Write Count Register */
 
#define EBIU_DDRBWC3   0xffc00a8c /* DDR Bank3 Write Count Register */
 
#define EBIU_DDRBWC4   0xffc00a90 /* DDR Bank4 Write Count Register */
 
#define EBIU_DDRBWC5   0xffc00a94 /* DDR Bank5 Write Count Register */
 
#define EBIU_DDRBWC6   0xffc00a98 /* DDR Bank6 Write Count Register */
 
#define EBIU_DDRBWC7   0xffc00a9c /* DDR Bank7 Write Count Register */
 
#define EBIU_DDRACCT   0xffc00aa0 /* DDR Activation Count Register */
 
#define EBIU_DDRTACT   0xffc00aa8 /* DDR Turn Around Count Register */
 
#define EBIU_DDRARCT   0xffc00aac /* DDR Auto-refresh Count Register */
 
#define EBIU_DDRGC0   0xffc00ab0 /* DDR Grant Count 0 Register */
 
#define EBIU_DDRGC1   0xffc00ab4 /* DDR Grant Count 1 Register */
 
#define EBIU_DDRGC2   0xffc00ab8 /* DDR Grant Count 2 Register */
 
#define EBIU_DDRGC3   0xffc00abc /* DDR Grant Count 3 Register */
 
#define EBIU_DDRMCEN   0xffc00ac0 /* DDR Metrics Counter Enable Register */
 
#define EBIU_DDRMCCL   0xffc00ac4 /* DDR Metrics Counter Clear Register */
 
#define DMAC0_TC_PER   0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
 
#define DMAC0_TC_CNT   0xffc00b10 /* DMA Controller 0 Current Counts Register */
 
#define DMA0_NEXT_DESC_PTR   0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */
 
#define DMA0_START_ADDR   0xffc00c04 /* DMA Channel 0 Start Address Register */
 
#define DMA0_CONFIG   0xffc00c08 /* DMA Channel 0 Configuration Register */
 
#define DMA0_X_COUNT   0xffc00c10 /* DMA Channel 0 X Count Register */
 
#define DMA0_X_MODIFY   0xffc00c14 /* DMA Channel 0 X Modify Register */
 
#define DMA0_Y_COUNT   0xffc00c18 /* DMA Channel 0 Y Count Register */
 
#define DMA0_Y_MODIFY   0xffc00c1c /* DMA Channel 0 Y Modify Register */
 
#define DMA0_CURR_DESC_PTR   0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */
 
#define DMA0_CURR_ADDR   0xffc00c24 /* DMA Channel 0 Current Address Register */
 
#define DMA0_IRQ_STATUS   0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */
 
#define DMA0_PERIPHERAL_MAP   0xffc00c2c /* DMA Channel 0 Peripheral Map Register */
 
#define DMA0_CURR_X_COUNT   0xffc00c30 /* DMA Channel 0 Current X Count Register */
 
#define DMA0_CURR_Y_COUNT   0xffc00c38 /* DMA Channel 0 Current Y Count Register */
 
#define DMA1_NEXT_DESC_PTR   0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */
 
#define DMA1_START_ADDR   0xffc00c44 /* DMA Channel 1 Start Address Register */
 
#define DMA1_CONFIG   0xffc00c48 /* DMA Channel 1 Configuration Register */
 
#define DMA1_X_COUNT   0xffc00c50 /* DMA Channel 1 X Count Register */
 
#define DMA1_X_MODIFY   0xffc00c54 /* DMA Channel 1 X Modify Register */
 
#define DMA1_Y_COUNT   0xffc00c58 /* DMA Channel 1 Y Count Register */
 
#define DMA1_Y_MODIFY   0xffc00c5c /* DMA Channel 1 Y Modify Register */
 
#define DMA1_CURR_DESC_PTR   0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */
 
#define DMA1_CURR_ADDR   0xffc00c64 /* DMA Channel 1 Current Address Register */
 
#define DMA1_IRQ_STATUS   0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */
 
#define DMA1_PERIPHERAL_MAP   0xffc00c6c /* DMA Channel 1 Peripheral Map Register */
 
#define DMA1_CURR_X_COUNT   0xffc00c70 /* DMA Channel 1 Current X Count Register */
 
#define DMA1_CURR_Y_COUNT   0xffc00c78 /* DMA Channel 1 Current Y Count Register */
 
#define DMA2_NEXT_DESC_PTR   0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */
 
#define DMA2_START_ADDR   0xffc00c84 /* DMA Channel 2 Start Address Register */
 
#define DMA2_CONFIG   0xffc00c88 /* DMA Channel 2 Configuration Register */
 
#define DMA2_X_COUNT   0xffc00c90 /* DMA Channel 2 X Count Register */
 
#define DMA2_X_MODIFY   0xffc00c94 /* DMA Channel 2 X Modify Register */
 
#define DMA2_Y_COUNT   0xffc00c98 /* DMA Channel 2 Y Count Register */
 
#define DMA2_Y_MODIFY   0xffc00c9c /* DMA Channel 2 Y Modify Register */
 
#define DMA2_CURR_DESC_PTR   0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */
 
#define DMA2_CURR_ADDR   0xffc00ca4 /* DMA Channel 2 Current Address Register */
 
#define DMA2_IRQ_STATUS   0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */
 
#define DMA2_PERIPHERAL_MAP   0xffc00cac /* DMA Channel 2 Peripheral Map Register */
 
#define DMA2_CURR_X_COUNT   0xffc00cb0 /* DMA Channel 2 Current X Count Register */
 
#define DMA2_CURR_Y_COUNT   0xffc00cb8 /* DMA Channel 2 Current Y Count Register */
 
#define DMA3_NEXT_DESC_PTR   0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */
 
#define DMA3_START_ADDR   0xffc00cc4 /* DMA Channel 3 Start Address Register */
 
#define DMA3_CONFIG   0xffc00cc8 /* DMA Channel 3 Configuration Register */
 
#define DMA3_X_COUNT   0xffc00cd0 /* DMA Channel 3 X Count Register */
 
#define DMA3_X_MODIFY   0xffc00cd4 /* DMA Channel 3 X Modify Register */
 
#define DMA3_Y_COUNT   0xffc00cd8 /* DMA Channel 3 Y Count Register */
 
#define DMA3_Y_MODIFY   0xffc00cdc /* DMA Channel 3 Y Modify Register */
 
#define DMA3_CURR_DESC_PTR   0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */
 
#define DMA3_CURR_ADDR   0xffc00ce4 /* DMA Channel 3 Current Address Register */
 
#define DMA3_IRQ_STATUS   0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */
 
#define DMA3_PERIPHERAL_MAP   0xffc00cec /* DMA Channel 3 Peripheral Map Register */
 
#define DMA3_CURR_X_COUNT   0xffc00cf0 /* DMA Channel 3 Current X Count Register */
 
#define DMA3_CURR_Y_COUNT   0xffc00cf8 /* DMA Channel 3 Current Y Count Register */
 
#define DMA4_NEXT_DESC_PTR   0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */
 
#define DMA4_START_ADDR   0xffc00d04 /* DMA Channel 4 Start Address Register */
 
#define DMA4_CONFIG   0xffc00d08 /* DMA Channel 4 Configuration Register */
 
#define DMA4_X_COUNT   0xffc00d10 /* DMA Channel 4 X Count Register */
 
#define DMA4_X_MODIFY   0xffc00d14 /* DMA Channel 4 X Modify Register */
 
#define DMA4_Y_COUNT   0xffc00d18 /* DMA Channel 4 Y Count Register */
 
#define DMA4_Y_MODIFY   0xffc00d1c /* DMA Channel 4 Y Modify Register */
 
#define DMA4_CURR_DESC_PTR   0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */
 
#define DMA4_CURR_ADDR   0xffc00d24 /* DMA Channel 4 Current Address Register */
 
#define DMA4_IRQ_STATUS   0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */
 
#define DMA4_PERIPHERAL_MAP   0xffc00d2c /* DMA Channel 4 Peripheral Map Register */
 
#define DMA4_CURR_X_COUNT   0xffc00d30 /* DMA Channel 4 Current X Count Register */
 
#define DMA4_CURR_Y_COUNT   0xffc00d38 /* DMA Channel 4 Current Y Count Register */
 
#define DMA5_NEXT_DESC_PTR   0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */
 
#define DMA5_START_ADDR   0xffc00d44 /* DMA Channel 5 Start Address Register */
 
#define DMA5_CONFIG   0xffc00d48 /* DMA Channel 5 Configuration Register */
 
#define DMA5_X_COUNT   0xffc00d50 /* DMA Channel 5 X Count Register */
 
#define DMA5_X_MODIFY   0xffc00d54 /* DMA Channel 5 X Modify Register */
 
#define DMA5_Y_COUNT   0xffc00d58 /* DMA Channel 5 Y Count Register */
 
#define DMA5_Y_MODIFY   0xffc00d5c /* DMA Channel 5 Y Modify Register */
 
#define DMA5_CURR_DESC_PTR   0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */
 
#define DMA5_CURR_ADDR   0xffc00d64 /* DMA Channel 5 Current Address Register */
 
#define DMA5_IRQ_STATUS   0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */
 
#define DMA5_PERIPHERAL_MAP   0xffc00d6c /* DMA Channel 5 Peripheral Map Register */
 
#define DMA5_CURR_X_COUNT   0xffc00d70 /* DMA Channel 5 Current X Count Register */
 
#define DMA5_CURR_Y_COUNT   0xffc00d78 /* DMA Channel 5 Current Y Count Register */
 
#define DMA6_NEXT_DESC_PTR   0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */
 
#define DMA6_START_ADDR   0xffc00d84 /* DMA Channel 6 Start Address Register */
 
#define DMA6_CONFIG   0xffc00d88 /* DMA Channel 6 Configuration Register */
 
#define DMA6_X_COUNT   0xffc00d90 /* DMA Channel 6 X Count Register */
 
#define DMA6_X_MODIFY   0xffc00d94 /* DMA Channel 6 X Modify Register */
 
#define DMA6_Y_COUNT   0xffc00d98 /* DMA Channel 6 Y Count Register */
 
#define DMA6_Y_MODIFY   0xffc00d9c /* DMA Channel 6 Y Modify Register */
 
#define DMA6_CURR_DESC_PTR   0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */
 
#define DMA6_CURR_ADDR   0xffc00da4 /* DMA Channel 6 Current Address Register */
 
#define DMA6_IRQ_STATUS   0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */
 
#define DMA6_PERIPHERAL_MAP   0xffc00dac /* DMA Channel 6 Peripheral Map Register */
 
#define DMA6_CURR_X_COUNT   0xffc00db0 /* DMA Channel 6 Current X Count Register */
 
#define DMA6_CURR_Y_COUNT   0xffc00db8 /* DMA Channel 6 Current Y Count Register */
 
#define DMA7_NEXT_DESC_PTR   0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */
 
#define DMA7_START_ADDR   0xffc00dc4 /* DMA Channel 7 Start Address Register */
 
#define DMA7_CONFIG   0xffc00dc8 /* DMA Channel 7 Configuration Register */
 
#define DMA7_X_COUNT   0xffc00dd0 /* DMA Channel 7 X Count Register */
 
#define DMA7_X_MODIFY   0xffc00dd4 /* DMA Channel 7 X Modify Register */
 
#define DMA7_Y_COUNT   0xffc00dd8 /* DMA Channel 7 Y Count Register */
 
#define DMA7_Y_MODIFY   0xffc00ddc /* DMA Channel 7 Y Modify Register */
 
#define DMA7_CURR_DESC_PTR   0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */
 
#define DMA7_CURR_ADDR   0xffc00de4 /* DMA Channel 7 Current Address Register */
 
#define DMA7_IRQ_STATUS   0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */
 
#define DMA7_PERIPHERAL_MAP   0xffc00dec /* DMA Channel 7 Peripheral Map Register */
 
#define DMA7_CURR_X_COUNT   0xffc00df0 /* DMA Channel 7 Current X Count Register */
 
#define DMA7_CURR_Y_COUNT   0xffc00df8 /* DMA Channel 7 Current Y Count Register */
 
#define DMA8_NEXT_DESC_PTR   0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */
 
#define DMA8_START_ADDR   0xffc00e04 /* DMA Channel 8 Start Address Register */
 
#define DMA8_CONFIG   0xffc00e08 /* DMA Channel 8 Configuration Register */
 
#define DMA8_X_COUNT   0xffc00e10 /* DMA Channel 8 X Count Register */
 
#define DMA8_X_MODIFY   0xffc00e14 /* DMA Channel 8 X Modify Register */
 
#define DMA8_Y_COUNT   0xffc00e18 /* DMA Channel 8 Y Count Register */
 
#define DMA8_Y_MODIFY   0xffc00e1c /* DMA Channel 8 Y Modify Register */
 
#define DMA8_CURR_DESC_PTR   0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */
 
#define DMA8_CURR_ADDR   0xffc00e24 /* DMA Channel 8 Current Address Register */
 
#define DMA8_IRQ_STATUS   0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */
 
#define DMA8_PERIPHERAL_MAP   0xffc00e2c /* DMA Channel 8 Peripheral Map Register */
 
#define DMA8_CURR_X_COUNT   0xffc00e30 /* DMA Channel 8 Current X Count Register */
 
#define DMA8_CURR_Y_COUNT   0xffc00e38 /* DMA Channel 8 Current Y Count Register */
 
#define DMA9_NEXT_DESC_PTR   0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */
 
#define DMA9_START_ADDR   0xffc00e44 /* DMA Channel 9 Start Address Register */
 
#define DMA9_CONFIG   0xffc00e48 /* DMA Channel 9 Configuration Register */
 
#define DMA9_X_COUNT   0xffc00e50 /* DMA Channel 9 X Count Register */
 
#define DMA9_X_MODIFY   0xffc00e54 /* DMA Channel 9 X Modify Register */
 
#define DMA9_Y_COUNT   0xffc00e58 /* DMA Channel 9 Y Count Register */
 
#define DMA9_Y_MODIFY   0xffc00e5c /* DMA Channel 9 Y Modify Register */
 
#define DMA9_CURR_DESC_PTR   0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */
 
#define DMA9_CURR_ADDR   0xffc00e64 /* DMA Channel 9 Current Address Register */
 
#define DMA9_IRQ_STATUS   0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */
 
#define DMA9_PERIPHERAL_MAP   0xffc00e6c /* DMA Channel 9 Peripheral Map Register */
 
#define DMA9_CURR_X_COUNT   0xffc00e70 /* DMA Channel 9 Current X Count Register */
 
#define DMA9_CURR_Y_COUNT   0xffc00e78 /* DMA Channel 9 Current Y Count Register */
 
#define DMA10_NEXT_DESC_PTR   0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */
 
#define DMA10_START_ADDR   0xffc00e84 /* DMA Channel 10 Start Address Register */
 
#define DMA10_CONFIG   0xffc00e88 /* DMA Channel 10 Configuration Register */
 
#define DMA10_X_COUNT   0xffc00e90 /* DMA Channel 10 X Count Register */
 
#define DMA10_X_MODIFY   0xffc00e94 /* DMA Channel 10 X Modify Register */
 
#define DMA10_Y_COUNT   0xffc00e98 /* DMA Channel 10 Y Count Register */
 
#define DMA10_Y_MODIFY   0xffc00e9c /* DMA Channel 10 Y Modify Register */
 
#define DMA10_CURR_DESC_PTR   0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */
 
#define DMA10_CURR_ADDR   0xffc00ea4 /* DMA Channel 10 Current Address Register */
 
#define DMA10_IRQ_STATUS   0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */
 
#define DMA10_PERIPHERAL_MAP   0xffc00eac /* DMA Channel 10 Peripheral Map Register */
 
#define DMA10_CURR_X_COUNT   0xffc00eb0 /* DMA Channel 10 Current X Count Register */
 
#define DMA10_CURR_Y_COUNT   0xffc00eb8 /* DMA Channel 10 Current Y Count Register */
 
#define DMA11_NEXT_DESC_PTR   0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */
 
#define DMA11_START_ADDR   0xffc00ec4 /* DMA Channel 11 Start Address Register */
 
#define DMA11_CONFIG   0xffc00ec8 /* DMA Channel 11 Configuration Register */
 
#define DMA11_X_COUNT   0xffc00ed0 /* DMA Channel 11 X Count Register */
 
#define DMA11_X_MODIFY   0xffc00ed4 /* DMA Channel 11 X Modify Register */
 
#define DMA11_Y_COUNT   0xffc00ed8 /* DMA Channel 11 Y Count Register */
 
#define DMA11_Y_MODIFY   0xffc00edc /* DMA Channel 11 Y Modify Register */
 
#define DMA11_CURR_DESC_PTR   0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */
 
#define DMA11_CURR_ADDR   0xffc00ee4 /* DMA Channel 11 Current Address Register */
 
#define DMA11_IRQ_STATUS   0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */
 
#define DMA11_PERIPHERAL_MAP   0xffc00eec /* DMA Channel 11 Peripheral Map Register */
 
#define DMA11_CURR_X_COUNT   0xffc00ef0 /* DMA Channel 11 Current X Count Register */
 
#define DMA11_CURR_Y_COUNT   0xffc00ef8 /* DMA Channel 11 Current Y Count Register */
 
#define MDMA_D0_NEXT_DESC_PTR   0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
 
#define MDMA_D0_START_ADDR   0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */
 
#define MDMA_D0_CONFIG   0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */
 
#define MDMA_D0_X_COUNT   0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */
 
#define MDMA_D0_X_MODIFY   0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */
 
#define MDMA_D0_Y_COUNT   0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */
 
#define MDMA_D0_Y_MODIFY   0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */
 
#define MDMA_D0_CURR_DESC_PTR   0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
 
#define MDMA_D0_CURR_ADDR   0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */
 
#define MDMA_D0_IRQ_STATUS   0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
 
#define MDMA_D0_PERIPHERAL_MAP   0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */
 
#define MDMA_D0_CURR_X_COUNT   0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */
 
#define MDMA_D0_CURR_Y_COUNT   0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */
 
#define MDMA_S0_NEXT_DESC_PTR   0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
 
#define MDMA_S0_START_ADDR   0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */
 
#define MDMA_S0_CONFIG   0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */
 
#define MDMA_S0_X_COUNT   0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */
 
#define MDMA_S0_X_MODIFY   0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */
 
#define MDMA_S0_Y_COUNT   0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */
 
#define MDMA_S0_Y_MODIFY   0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */
 
#define MDMA_S0_CURR_DESC_PTR   0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
 
#define MDMA_S0_CURR_ADDR   0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */
 
#define MDMA_S0_IRQ_STATUS   0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
 
#define MDMA_S0_PERIPHERAL_MAP   0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */
 
#define MDMA_S0_CURR_X_COUNT   0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */
 
#define MDMA_S0_CURR_Y_COUNT   0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */
 
#define MDMA_D1_NEXT_DESC_PTR   0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
 
#define MDMA_D1_START_ADDR   0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */
 
#define MDMA_D1_CONFIG   0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */
 
#define MDMA_D1_X_COUNT   0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */
 
#define MDMA_D1_X_MODIFY   0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */
 
#define MDMA_D1_Y_COUNT   0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */
 
#define MDMA_D1_Y_MODIFY   0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */
 
#define MDMA_D1_CURR_DESC_PTR   0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
 
#define MDMA_D1_CURR_ADDR   0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */
 
#define MDMA_D1_IRQ_STATUS   0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
 
#define MDMA_D1_PERIPHERAL_MAP   0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */
 
#define MDMA_D1_CURR_X_COUNT   0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */
 
#define MDMA_D1_CURR_Y_COUNT   0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */
 
#define MDMA_S1_NEXT_DESC_PTR   0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
 
#define MDMA_S1_START_ADDR   0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */
 
#define MDMA_S1_CONFIG   0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */
 
#define MDMA_S1_X_COUNT   0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */
 
#define MDMA_S1_X_MODIFY   0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */
 
#define MDMA_S1_Y_COUNT   0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */
 
#define MDMA_S1_Y_MODIFY   0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */
 
#define MDMA_S1_CURR_DESC_PTR   0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
 
#define MDMA_S1_CURR_ADDR   0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */
 
#define MDMA_S1_IRQ_STATUS   0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
 
#define MDMA_S1_PERIPHERAL_MAP   0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */
 
#define MDMA_S1_CURR_X_COUNT   0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */
 
#define MDMA_S1_CURR_Y_COUNT   0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */
 
#define UART3_DLL   0xffc03100 /* Divisor Latch Low Byte */
 
#define UART3_DLH   0xffc03104 /* Divisor Latch High Byte */
 
#define UART3_GCTL   0xffc03108 /* Global Control Register */
 
#define UART3_LCR   0xffc0310c /* Line Control Register */
 
#define UART3_MCR   0xffc03110 /* Modem Control Register */
 
#define UART3_LSR   0xffc03114 /* Line Status Register */
 
#define UART3_MSR   0xffc03118 /* Modem Status Register */
 
#define UART3_SCR   0xffc0311c /* Scratch Register */
 
#define UART3_IER_SET   0xffc03120 /* Interrupt Enable Register Set */
 
#define UART3_IER_CLEAR   0xffc03124 /* Interrupt Enable Register Clear */
 
#define UART3_THR   0xffc03128 /* Transmit Hold Register */
 
#define UART3_RBR   0xffc0312c /* Receive Buffer Register */
 
#define EPPI1_STATUS   0xffc01300 /* EPPI1 Status Register */
 
#define EPPI1_HCOUNT   0xffc01304 /* EPPI1 Horizontal Transfer Count Register */
 
#define EPPI1_HDELAY   0xffc01308 /* EPPI1 Horizontal Delay Count Register */
 
#define EPPI1_VCOUNT   0xffc0130c /* EPPI1 Vertical Transfer Count Register */
 
#define EPPI1_VDELAY   0xffc01310 /* EPPI1 Vertical Delay Count Register */
 
#define EPPI1_FRAME   0xffc01314 /* EPPI1 Lines per Frame Register */
 
#define EPPI1_LINE   0xffc01318 /* EPPI1 Samples per Line Register */
 
#define EPPI1_CLKDIV   0xffc0131c /* EPPI1 Clock Divide Register */
 
#define EPPI1_CONTROL   0xffc01320 /* EPPI1 Control Register */
 
#define EPPI1_FS1W_HBL   0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
 
#define EPPI1_FS1P_AVPL   0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
 
#define EPPI1_FS2W_LVB   0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
 
#define EPPI1_FS2P_LAVF   0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
 
#define EPPI1_CLIP   0xffc01334 /* EPPI1 Clipping Register */
 
#define PINT0_MASK_SET   0xffc01400 /* Pin Interrupt 0 Mask Set Register */
 
#define PINT0_MASK_CLEAR   0xffc01404 /* Pin Interrupt 0 Mask Clear Register */
 
#define PINT0_REQUEST   0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */
 
#define PINT0_ASSIGN   0xffc0140c /* Pin Interrupt 0 Port Assign Register */
 
#define PINT0_EDGE_SET   0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
 
#define PINT0_EDGE_CLEAR   0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
 
#define PINT0_INVERT_SET   0xffc01418 /* Pin Interrupt 0 Inversion Set Register */
 
#define PINT0_INVERT_CLEAR   0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */
 
#define PINT0_PINSTATE   0xffc01420 /* Pin Interrupt 0 Pin Status Register */
 
#define PINT0_LATCH   0xffc01424 /* Pin Interrupt 0 Latch Register */
 
#define PINT1_MASK_SET   0xffc01430 /* Pin Interrupt 1 Mask Set Register */
 
#define PINT1_MASK_CLEAR   0xffc01434 /* Pin Interrupt 1 Mask Clear Register */
 
#define PINT1_REQUEST   0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */
 
#define PINT1_ASSIGN   0xffc0143c /* Pin Interrupt 1 Port Assign Register */
 
#define PINT1_EDGE_SET   0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
 
#define PINT1_EDGE_CLEAR   0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
 
#define PINT1_INVERT_SET   0xffc01448 /* Pin Interrupt 1 Inversion Set Register */
 
#define PINT1_INVERT_CLEAR   0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */
 
#define PINT1_PINSTATE   0xffc01450 /* Pin Interrupt 1 Pin Status Register */
 
#define PINT1_LATCH   0xffc01454 /* Pin Interrupt 1 Latch Register */
 
#define PINT2_MASK_SET   0xffc01460 /* Pin Interrupt 2 Mask Set Register */
 
#define PINT2_MASK_CLEAR   0xffc01464 /* Pin Interrupt 2 Mask Clear Register */
 
#define PINT2_REQUEST   0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */
 
#define PINT2_ASSIGN   0xffc0146c /* Pin Interrupt 2 Port Assign Register */
 
#define PINT2_EDGE_SET   0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
 
#define PINT2_EDGE_CLEAR   0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
 
#define PINT2_INVERT_SET   0xffc01478 /* Pin Interrupt 2 Inversion Set Register */
 
#define PINT2_INVERT_CLEAR   0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */
 
#define PINT2_PINSTATE   0xffc01480 /* Pin Interrupt 2 Pin Status Register */
 
#define PINT2_LATCH   0xffc01484 /* Pin Interrupt 2 Latch Register */
 
#define PINT3_MASK_SET   0xffc01490 /* Pin Interrupt 3 Mask Set Register */
 
#define PINT3_MASK_CLEAR   0xffc01494 /* Pin Interrupt 3 Mask Clear Register */
 
#define PINT3_REQUEST   0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */
 
#define PINT3_ASSIGN   0xffc0149c /* Pin Interrupt 3 Port Assign Register */
 
#define PINT3_EDGE_SET   0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
 
#define PINT3_EDGE_CLEAR   0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
 
#define PINT3_INVERT_SET   0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */
 
#define PINT3_INVERT_CLEAR   0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */
 
#define PINT3_PINSTATE   0xffc014b0 /* Pin Interrupt 3 Pin Status Register */
 
#define PINT3_LATCH   0xffc014b4 /* Pin Interrupt 3 Latch Register */
 
#define PORTA_FER   0xffc014c0 /* Function Enable Register */
 
#define PORTA   0xffc014c4 /* GPIO Data Register */
 
#define PORTA_SET   0xffc014c8 /* GPIO Data Set Register */
 
#define PORTA_CLEAR   0xffc014cc /* GPIO Data Clear Register */
 
#define PORTA_DIR_SET   0xffc014d0 /* GPIO Direction Set Register */
 
#define PORTA_DIR_CLEAR   0xffc014d4 /* GPIO Direction Clear Register */
 
#define PORTA_INEN   0xffc014d8 /* GPIO Input Enable Register */
 
#define PORTA_MUX   0xffc014dc /* Multiplexer Control Register */
 
#define PORTB_FER   0xffc014e0 /* Function Enable Register */
 
#define PORTB   0xffc014e4 /* GPIO Data Register */
 
#define PORTB_SET   0xffc014e8 /* GPIO Data Set Register */
 
#define PORTB_CLEAR   0xffc014ec /* GPIO Data Clear Register */
 
#define PORTB_DIR_SET   0xffc014f0 /* GPIO Direction Set Register */
 
#define PORTB_DIR_CLEAR   0xffc014f4 /* GPIO Direction Clear Register */
 
#define PORTB_INEN   0xffc014f8 /* GPIO Input Enable Register */
 
#define PORTB_MUX   0xffc014fc /* Multiplexer Control Register */
 
#define PORTC_FER   0xffc01500 /* Function Enable Register */
 
#define PORTC   0xffc01504 /* GPIO Data Register */
 
#define PORTC_SET   0xffc01508 /* GPIO Data Set Register */
 
#define PORTC_CLEAR   0xffc0150c /* GPIO Data Clear Register */
 
#define PORTC_DIR_SET   0xffc01510 /* GPIO Direction Set Register */
 
#define PORTC_DIR_CLEAR   0xffc01514 /* GPIO Direction Clear Register */
 
#define PORTC_INEN   0xffc01518 /* GPIO Input Enable Register */
 
#define PORTC_MUX   0xffc0151c /* Multiplexer Control Register */
 
#define PORTD_FER   0xffc01520 /* Function Enable Register */
 
#define PORTD   0xffc01524 /* GPIO Data Register */
 
#define PORTD_SET   0xffc01528 /* GPIO Data Set Register */
 
#define PORTD_CLEAR   0xffc0152c /* GPIO Data Clear Register */
 
#define PORTD_DIR_SET   0xffc01530 /* GPIO Direction Set Register */
 
#define PORTD_DIR_CLEAR   0xffc01534 /* GPIO Direction Clear Register */
 
#define PORTD_INEN   0xffc01538 /* GPIO Input Enable Register */
 
#define PORTD_MUX   0xffc0153c /* Multiplexer Control Register */
 
#define PORTE_FER   0xffc01540 /* Function Enable Register */
 
#define PORTE   0xffc01544 /* GPIO Data Register */
 
#define PORTE_SET   0xffc01548 /* GPIO Data Set Register */
 
#define PORTE_CLEAR   0xffc0154c /* GPIO Data Clear Register */
 
#define PORTE_DIR_SET   0xffc01550 /* GPIO Direction Set Register */
 
#define PORTE_DIR_CLEAR   0xffc01554 /* GPIO Direction Clear Register */
 
#define PORTE_INEN   0xffc01558 /* GPIO Input Enable Register */
 
#define PORTE_MUX   0xffc0155c /* Multiplexer Control Register */
 
#define PORTF_FER   0xffc01560 /* Function Enable Register */
 
#define PORTF   0xffc01564 /* GPIO Data Register */
 
#define PORTF_SET   0xffc01568 /* GPIO Data Set Register */
 
#define PORTF_CLEAR   0xffc0156c /* GPIO Data Clear Register */
 
#define PORTF_DIR_SET   0xffc01570 /* GPIO Direction Set Register */
 
#define PORTF_DIR_CLEAR   0xffc01574 /* GPIO Direction Clear Register */
 
#define PORTF_INEN   0xffc01578 /* GPIO Input Enable Register */
 
#define PORTF_MUX   0xffc0157c /* Multiplexer Control Register */
 
#define PORTG_FER   0xffc01580 /* Function Enable Register */
 
#define PORTG   0xffc01584 /* GPIO Data Register */
 
#define PORTG_SET   0xffc01588 /* GPIO Data Set Register */
 
#define PORTG_CLEAR   0xffc0158c /* GPIO Data Clear Register */
 
#define PORTG_DIR_SET   0xffc01590 /* GPIO Direction Set Register */
 
#define PORTG_DIR_CLEAR   0xffc01594 /* GPIO Direction Clear Register */
 
#define PORTG_INEN   0xffc01598 /* GPIO Input Enable Register */
 
#define PORTG_MUX   0xffc0159c /* Multiplexer Control Register */
 
#define PORTH_FER   0xffc015a0 /* Function Enable Register */
 
#define PORTH   0xffc015a4 /* GPIO Data Register */
 
#define PORTH_SET   0xffc015a8 /* GPIO Data Set Register */
 
#define PORTH_CLEAR   0xffc015ac /* GPIO Data Clear Register */
 
#define PORTH_DIR_SET   0xffc015b0 /* GPIO Direction Set Register */
 
#define PORTH_DIR_CLEAR   0xffc015b4 /* GPIO Direction Clear Register */
 
#define PORTH_INEN   0xffc015b8 /* GPIO Input Enable Register */
 
#define PORTH_MUX   0xffc015bc /* Multiplexer Control Register */
 
#define PORTI_FER   0xffc015c0 /* Function Enable Register */
 
#define PORTI   0xffc015c4 /* GPIO Data Register */
 
#define PORTI_SET   0xffc015c8 /* GPIO Data Set Register */
 
#define PORTI_CLEAR   0xffc015cc /* GPIO Data Clear Register */
 
#define PORTI_DIR_SET   0xffc015d0 /* GPIO Direction Set Register */
 
#define PORTI_DIR_CLEAR   0xffc015d4 /* GPIO Direction Clear Register */
 
#define PORTI_INEN   0xffc015d8 /* GPIO Input Enable Register */
 
#define PORTI_MUX   0xffc015dc /* Multiplexer Control Register */
 
#define PORTJ_FER   0xffc015e0 /* Function Enable Register */
 
#define PORTJ   0xffc015e4 /* GPIO Data Register */
 
#define PORTJ_SET   0xffc015e8 /* GPIO Data Set Register */
 
#define PORTJ_CLEAR   0xffc015ec /* GPIO Data Clear Register */
 
#define PORTJ_DIR_SET   0xffc015f0 /* GPIO Direction Set Register */
 
#define PORTJ_DIR_CLEAR   0xffc015f4 /* GPIO Direction Clear Register */
 
#define PORTJ_INEN   0xffc015f8 /* GPIO Input Enable Register */
 
#define PORTJ_MUX   0xffc015fc /* Multiplexer Control Register */
 
#define TIMER0_CONFIG   0xffc01600 /* Timer 0 Configuration Register */
 
#define TIMER0_COUNTER   0xffc01604 /* Timer 0 Counter Register */
 
#define TIMER0_PERIOD   0xffc01608 /* Timer 0 Period Register */
 
#define TIMER0_WIDTH   0xffc0160c /* Timer 0 Width Register */
 
#define TIMER1_CONFIG   0xffc01610 /* Timer 1 Configuration Register */
 
#define TIMER1_COUNTER   0xffc01614 /* Timer 1 Counter Register */
 
#define TIMER1_PERIOD   0xffc01618 /* Timer 1 Period Register */
 
#define TIMER1_WIDTH   0xffc0161c /* Timer 1 Width Register */
 
#define TIMER2_CONFIG   0xffc01620 /* Timer 2 Configuration Register */
 
#define TIMER2_COUNTER   0xffc01624 /* Timer 2 Counter Register */
 
#define TIMER2_PERIOD   0xffc01628 /* Timer 2 Period Register */
 
#define TIMER2_WIDTH   0xffc0162c /* Timer 2 Width Register */
 
#define TIMER3_CONFIG   0xffc01630 /* Timer 3 Configuration Register */
 
#define TIMER3_COUNTER   0xffc01634 /* Timer 3 Counter Register */
 
#define TIMER3_PERIOD   0xffc01638 /* Timer 3 Period Register */
 
#define TIMER3_WIDTH   0xffc0163c /* Timer 3 Width Register */
 
#define TIMER4_CONFIG   0xffc01640 /* Timer 4 Configuration Register */
 
#define TIMER4_COUNTER   0xffc01644 /* Timer 4 Counter Register */
 
#define TIMER4_PERIOD   0xffc01648 /* Timer 4 Period Register */
 
#define TIMER4_WIDTH   0xffc0164c /* Timer 4 Width Register */
 
#define TIMER5_CONFIG   0xffc01650 /* Timer 5 Configuration Register */
 
#define TIMER5_COUNTER   0xffc01654 /* Timer 5 Counter Register */
 
#define TIMER5_PERIOD   0xffc01658 /* Timer 5 Period Register */
 
#define TIMER5_WIDTH   0xffc0165c /* Timer 5 Width Register */
 
#define TIMER6_CONFIG   0xffc01660 /* Timer 6 Configuration Register */
 
#define TIMER6_COUNTER   0xffc01664 /* Timer 6 Counter Register */
 
#define TIMER6_PERIOD   0xffc01668 /* Timer 6 Period Register */
 
#define TIMER6_WIDTH   0xffc0166c /* Timer 6 Width Register */
 
#define TIMER7_CONFIG   0xffc01670 /* Timer 7 Configuration Register */
 
#define TIMER7_COUNTER   0xffc01674 /* Timer 7 Counter Register */
 
#define TIMER7_PERIOD   0xffc01678 /* Timer 7 Period Register */
 
#define TIMER7_WIDTH   0xffc0167c /* Timer 7 Width Register */
 
#define TIMER_ENABLE0   0xffc01680 /* Timer Group of 8 Enable Register */
 
#define TIMER_DISABLE0   0xffc01684 /* Timer Group of 8 Disable Register */
 
#define TIMER_STATUS0   0xffc01688 /* Timer Group of 8 Status Register */
 
#define DMAC1_TC_PER   0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
 
#define DMAC1_TC_CNT   0xffc01b10 /* DMA Controller 1 Current Counts Register */
 
#define DMA12_NEXT_DESC_PTR   0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */
 
#define DMA12_START_ADDR   0xffc01c04 /* DMA Channel 12 Start Address Register */
 
#define DMA12_CONFIG   0xffc01c08 /* DMA Channel 12 Configuration Register */
 
#define DMA12_X_COUNT   0xffc01c10 /* DMA Channel 12 X Count Register */
 
#define DMA12_X_MODIFY   0xffc01c14 /* DMA Channel 12 X Modify Register */
 
#define DMA12_Y_COUNT   0xffc01c18 /* DMA Channel 12 Y Count Register */
 
#define DMA12_Y_MODIFY   0xffc01c1c /* DMA Channel 12 Y Modify Register */
 
#define DMA12_CURR_DESC_PTR   0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */
 
#define DMA12_CURR_ADDR   0xffc01c24 /* DMA Channel 12 Current Address Register */
 
#define DMA12_IRQ_STATUS   0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */
 
#define DMA12_PERIPHERAL_MAP   0xffc01c2c /* DMA Channel 12 Peripheral Map Register */
 
#define DMA12_CURR_X_COUNT   0xffc01c30 /* DMA Channel 12 Current X Count Register */
 
#define DMA12_CURR_Y_COUNT   0xffc01c38 /* DMA Channel 12 Current Y Count Register */
 
#define DMA13_NEXT_DESC_PTR   0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */
 
#define DMA13_START_ADDR   0xffc01c44 /* DMA Channel 13 Start Address Register */
 
#define DMA13_CONFIG   0xffc01c48 /* DMA Channel 13 Configuration Register */
 
#define DMA13_X_COUNT   0xffc01c50 /* DMA Channel 13 X Count Register */
 
#define DMA13_X_MODIFY   0xffc01c54 /* DMA Channel 13 X Modify Register */
 
#define DMA13_Y_COUNT   0xffc01c58 /* DMA Channel 13 Y Count Register */
 
#define DMA13_Y_MODIFY   0xffc01c5c /* DMA Channel 13 Y Modify Register */
 
#define DMA13_CURR_DESC_PTR   0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */
 
#define DMA13_CURR_ADDR   0xffc01c64 /* DMA Channel 13 Current Address Register */
 
#define DMA13_IRQ_STATUS   0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */
 
#define DMA13_PERIPHERAL_MAP   0xffc01c6c /* DMA Channel 13 Peripheral Map Register */
 
#define DMA13_CURR_X_COUNT   0xffc01c70 /* DMA Channel 13 Current X Count Register */
 
#define DMA13_CURR_Y_COUNT   0xffc01c78 /* DMA Channel 13 Current Y Count Register */
 
#define DMA14_NEXT_DESC_PTR   0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */
 
#define DMA14_START_ADDR   0xffc01c84 /* DMA Channel 14 Start Address Register */
 
#define DMA14_CONFIG   0xffc01c88 /* DMA Channel 14 Configuration Register */
 
#define DMA14_X_COUNT   0xffc01c90 /* DMA Channel 14 X Count Register */
 
#define DMA14_X_MODIFY   0xffc01c94 /* DMA Channel 14 X Modify Register */
 
#define DMA14_Y_COUNT   0xffc01c98 /* DMA Channel 14 Y Count Register */
 
#define DMA14_Y_MODIFY   0xffc01c9c /* DMA Channel 14 Y Modify Register */
 
#define DMA14_CURR_DESC_PTR   0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */
 
#define DMA14_CURR_ADDR   0xffc01ca4 /* DMA Channel 14 Current Address Register */
 
#define DMA14_IRQ_STATUS   0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */
 
#define DMA14_PERIPHERAL_MAP   0xffc01cac /* DMA Channel 14 Peripheral Map Register */
 
#define DMA14_CURR_X_COUNT   0xffc01cb0 /* DMA Channel 14 Current X Count Register */
 
#define DMA14_CURR_Y_COUNT   0xffc01cb8 /* DMA Channel 14 Current Y Count Register */
 
#define DMA15_NEXT_DESC_PTR   0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */
 
#define DMA15_START_ADDR   0xffc01cc4 /* DMA Channel 15 Start Address Register */
 
#define DMA15_CONFIG   0xffc01cc8 /* DMA Channel 15 Configuration Register */
 
#define DMA15_X_COUNT   0xffc01cd0 /* DMA Channel 15 X Count Register */
 
#define DMA15_X_MODIFY   0xffc01cd4 /* DMA Channel 15 X Modify Register */
 
#define DMA15_Y_COUNT   0xffc01cd8 /* DMA Channel 15 Y Count Register */
 
#define DMA15_Y_MODIFY   0xffc01cdc /* DMA Channel 15 Y Modify Register */
 
#define DMA15_CURR_DESC_PTR   0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */
 
#define DMA15_CURR_ADDR   0xffc01ce4 /* DMA Channel 15 Current Address Register */
 
#define DMA15_IRQ_STATUS   0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */
 
#define DMA15_PERIPHERAL_MAP   0xffc01cec /* DMA Channel 15 Peripheral Map Register */
 
#define DMA15_CURR_X_COUNT   0xffc01cf0 /* DMA Channel 15 Current X Count Register */
 
#define DMA15_CURR_Y_COUNT   0xffc01cf8 /* DMA Channel 15 Current Y Count Register */
 
#define DMA16_NEXT_DESC_PTR   0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */
 
#define DMA16_START_ADDR   0xffc01d04 /* DMA Channel 16 Start Address Register */
 
#define DMA16_CONFIG   0xffc01d08 /* DMA Channel 16 Configuration Register */
 
#define DMA16_X_COUNT   0xffc01d10 /* DMA Channel 16 X Count Register */
 
#define DMA16_X_MODIFY   0xffc01d14 /* DMA Channel 16 X Modify Register */
 
#define DMA16_Y_COUNT   0xffc01d18 /* DMA Channel 16 Y Count Register */
 
#define DMA16_Y_MODIFY   0xffc01d1c /* DMA Channel 16 Y Modify Register */
 
#define DMA16_CURR_DESC_PTR   0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */
 
#define DMA16_CURR_ADDR   0xffc01d24 /* DMA Channel 16 Current Address Register */
 
#define DMA16_IRQ_STATUS   0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */
 
#define DMA16_PERIPHERAL_MAP   0xffc01d2c /* DMA Channel 16 Peripheral Map Register */
 
#define DMA16_CURR_X_COUNT   0xffc01d30 /* DMA Channel 16 Current X Count Register */
 
#define DMA16_CURR_Y_COUNT   0xffc01d38 /* DMA Channel 16 Current Y Count Register */
 
#define DMA17_NEXT_DESC_PTR   0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */
 
#define DMA17_START_ADDR   0xffc01d44 /* DMA Channel 17 Start Address Register */
 
#define DMA17_CONFIG   0xffc01d48 /* DMA Channel 17 Configuration Register */
 
#define DMA17_X_COUNT   0xffc01d50 /* DMA Channel 17 X Count Register */
 
#define DMA17_X_MODIFY   0xffc01d54 /* DMA Channel 17 X Modify Register */
 
#define DMA17_Y_COUNT   0xffc01d58 /* DMA Channel 17 Y Count Register */
 
#define DMA17_Y_MODIFY   0xffc01d5c /* DMA Channel 17 Y Modify Register */
 
#define DMA17_CURR_DESC_PTR   0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */
 
#define DMA17_CURR_ADDR   0xffc01d64 /* DMA Channel 17 Current Address Register */
 
#define DMA17_IRQ_STATUS   0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */
 
#define DMA17_PERIPHERAL_MAP   0xffc01d6c /* DMA Channel 17 Peripheral Map Register */
 
#define DMA17_CURR_X_COUNT   0xffc01d70 /* DMA Channel 17 Current X Count Register */
 
#define DMA17_CURR_Y_COUNT   0xffc01d78 /* DMA Channel 17 Current Y Count Register */
 
#define DMA18_NEXT_DESC_PTR   0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */
 
#define DMA18_START_ADDR   0xffc01d84 /* DMA Channel 18 Start Address Register */
 
#define DMA18_CONFIG   0xffc01d88 /* DMA Channel 18 Configuration Register */
 
#define DMA18_X_COUNT   0xffc01d90 /* DMA Channel 18 X Count Register */
 
#define DMA18_X_MODIFY   0xffc01d94 /* DMA Channel 18 X Modify Register */
 
#define DMA18_Y_COUNT   0xffc01d98 /* DMA Channel 18 Y Count Register */
 
#define DMA18_Y_MODIFY   0xffc01d9c /* DMA Channel 18 Y Modify Register */
 
#define DMA18_CURR_DESC_PTR   0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */
 
#define DMA18_CURR_ADDR   0xffc01da4 /* DMA Channel 18 Current Address Register */
 
#define DMA18_IRQ_STATUS   0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */
 
#define DMA18_PERIPHERAL_MAP   0xffc01dac /* DMA Channel 18 Peripheral Map Register */
 
#define DMA18_CURR_X_COUNT   0xffc01db0 /* DMA Channel 18 Current X Count Register */
 
#define DMA18_CURR_Y_COUNT   0xffc01db8 /* DMA Channel 18 Current Y Count Register */
 
#define DMA19_NEXT_DESC_PTR   0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */
 
#define DMA19_START_ADDR   0xffc01dc4 /* DMA Channel 19 Start Address Register */
 
#define DMA19_CONFIG   0xffc01dc8 /* DMA Channel 19 Configuration Register */
 
#define DMA19_X_COUNT   0xffc01dd0 /* DMA Channel 19 X Count Register */
 
#define DMA19_X_MODIFY   0xffc01dd4 /* DMA Channel 19 X Modify Register */
 
#define DMA19_Y_COUNT   0xffc01dd8 /* DMA Channel 19 Y Count Register */
 
#define DMA19_Y_MODIFY   0xffc01ddc /* DMA Channel 19 Y Modify Register */
 
#define DMA19_CURR_DESC_PTR   0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */
 
#define DMA19_CURR_ADDR   0xffc01de4 /* DMA Channel 19 Current Address Register */
 
#define DMA19_IRQ_STATUS   0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */
 
#define DMA19_PERIPHERAL_MAP   0xffc01dec /* DMA Channel 19 Peripheral Map Register */
 
#define DMA19_CURR_X_COUNT   0xffc01df0 /* DMA Channel 19 Current X Count Register */
 
#define DMA19_CURR_Y_COUNT   0xffc01df8 /* DMA Channel 19 Current Y Count Register */
 
#define DMA20_NEXT_DESC_PTR   0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */
 
#define DMA20_START_ADDR   0xffc01e04 /* DMA Channel 20 Start Address Register */
 
#define DMA20_CONFIG   0xffc01e08 /* DMA Channel 20 Configuration Register */
 
#define DMA20_X_COUNT   0xffc01e10 /* DMA Channel 20 X Count Register */
 
#define DMA20_X_MODIFY   0xffc01e14 /* DMA Channel 20 X Modify Register */
 
#define DMA20_Y_COUNT   0xffc01e18 /* DMA Channel 20 Y Count Register */
 
#define DMA20_Y_MODIFY   0xffc01e1c /* DMA Channel 20 Y Modify Register */
 
#define DMA20_CURR_DESC_PTR   0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */
 
#define DMA20_CURR_ADDR   0xffc01e24 /* DMA Channel 20 Current Address Register */
 
#define DMA20_IRQ_STATUS   0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */
 
#define DMA20_PERIPHERAL_MAP   0xffc01e2c /* DMA Channel 20 Peripheral Map Register */
 
#define DMA20_CURR_X_COUNT   0xffc01e30 /* DMA Channel 20 Current X Count Register */
 
#define DMA20_CURR_Y_COUNT   0xffc01e38 /* DMA Channel 20 Current Y Count Register */
 
#define DMA21_NEXT_DESC_PTR   0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */
 
#define DMA21_START_ADDR   0xffc01e44 /* DMA Channel 21 Start Address Register */
 
#define DMA21_CONFIG   0xffc01e48 /* DMA Channel 21 Configuration Register */
 
#define DMA21_X_COUNT   0xffc01e50 /* DMA Channel 21 X Count Register */
 
#define DMA21_X_MODIFY   0xffc01e54 /* DMA Channel 21 X Modify Register */
 
#define DMA21_Y_COUNT   0xffc01e58 /* DMA Channel 21 Y Count Register */
 
#define DMA21_Y_MODIFY   0xffc01e5c /* DMA Channel 21 Y Modify Register */
 
#define DMA21_CURR_DESC_PTR   0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */
 
#define DMA21_CURR_ADDR   0xffc01e64 /* DMA Channel 21 Current Address Register */
 
#define DMA21_IRQ_STATUS   0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */
 
#define DMA21_PERIPHERAL_MAP   0xffc01e6c /* DMA Channel 21 Peripheral Map Register */
 
#define DMA21_CURR_X_COUNT   0xffc01e70 /* DMA Channel 21 Current X Count Register */
 
#define DMA21_CURR_Y_COUNT   0xffc01e78 /* DMA Channel 21 Current Y Count Register */
 
#define DMA22_NEXT_DESC_PTR   0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */
 
#define DMA22_START_ADDR   0xffc01e84 /* DMA Channel 22 Start Address Register */
 
#define DMA22_CONFIG   0xffc01e88 /* DMA Channel 22 Configuration Register */
 
#define DMA22_X_COUNT   0xffc01e90 /* DMA Channel 22 X Count Register */
 
#define DMA22_X_MODIFY   0xffc01e94 /* DMA Channel 22 X Modify Register */
 
#define DMA22_Y_COUNT   0xffc01e98 /* DMA Channel 22 Y Count Register */
 
#define DMA22_Y_MODIFY   0xffc01e9c /* DMA Channel 22 Y Modify Register */
 
#define DMA22_CURR_DESC_PTR   0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */
 
#define DMA22_CURR_ADDR   0xffc01ea4 /* DMA Channel 22 Current Address Register */
 
#define DMA22_IRQ_STATUS   0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */
 
#define DMA22_PERIPHERAL_MAP   0xffc01eac /* DMA Channel 22 Peripheral Map Register */
 
#define DMA22_CURR_X_COUNT   0xffc01eb0 /* DMA Channel 22 Current X Count Register */
 
#define DMA22_CURR_Y_COUNT   0xffc01eb8 /* DMA Channel 22 Current Y Count Register */
 
#define DMA23_NEXT_DESC_PTR   0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */
 
#define DMA23_START_ADDR   0xffc01ec4 /* DMA Channel 23 Start Address Register */
 
#define DMA23_CONFIG   0xffc01ec8 /* DMA Channel 23 Configuration Register */
 
#define DMA23_X_COUNT   0xffc01ed0 /* DMA Channel 23 X Count Register */
 
#define DMA23_X_MODIFY   0xffc01ed4 /* DMA Channel 23 X Modify Register */
 
#define DMA23_Y_COUNT   0xffc01ed8 /* DMA Channel 23 Y Count Register */
 
#define DMA23_Y_MODIFY   0xffc01edc /* DMA Channel 23 Y Modify Register */
 
#define DMA23_CURR_DESC_PTR   0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */
 
#define DMA23_CURR_ADDR   0xffc01ee4 /* DMA Channel 23 Current Address Register */
 
#define DMA23_IRQ_STATUS   0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */
 
#define DMA23_PERIPHERAL_MAP   0xffc01eec /* DMA Channel 23 Peripheral Map Register */
 
#define DMA23_CURR_X_COUNT   0xffc01ef0 /* DMA Channel 23 Current X Count Register */
 
#define DMA23_CURR_Y_COUNT   0xffc01ef8 /* DMA Channel 23 Current Y Count Register */
 
#define MDMA_D2_NEXT_DESC_PTR   0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
 
#define MDMA_D2_START_ADDR   0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */
 
#define MDMA_D2_CONFIG   0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */
 
#define MDMA_D2_X_COUNT   0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */
 
#define MDMA_D2_X_MODIFY   0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */
 
#define MDMA_D2_Y_COUNT   0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */
 
#define MDMA_D2_Y_MODIFY   0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */
 
#define MDMA_D2_CURR_DESC_PTR   0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
 
#define MDMA_D2_CURR_ADDR   0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */
 
#define MDMA_D2_IRQ_STATUS   0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
 
#define MDMA_D2_PERIPHERAL_MAP   0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */
 
#define MDMA_D2_CURR_X_COUNT   0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */
 
#define MDMA_D2_CURR_Y_COUNT   0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */
 
#define MDMA_S2_NEXT_DESC_PTR   0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
 
#define MDMA_S2_START_ADDR   0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */
 
#define MDMA_S2_CONFIG   0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */
 
#define MDMA_S2_X_COUNT   0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */
 
#define MDMA_S2_X_MODIFY   0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */
 
#define MDMA_S2_Y_COUNT   0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */
 
#define MDMA_S2_Y_MODIFY   0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */
 
#define MDMA_S2_CURR_DESC_PTR   0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
 
#define MDMA_S2_CURR_ADDR   0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */
 
#define MDMA_S2_IRQ_STATUS   0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
 
#define MDMA_S2_PERIPHERAL_MAP   0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */
 
#define MDMA_S2_CURR_X_COUNT   0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */
 
#define MDMA_S2_CURR_Y_COUNT   0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */
 
#define MDMA_D3_NEXT_DESC_PTR   0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
 
#define MDMA_D3_START_ADDR   0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */
 
#define MDMA_D3_CONFIG   0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */
 
#define MDMA_D3_X_COUNT   0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */
 
#define MDMA_D3_X_MODIFY   0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */
 
#define MDMA_D3_Y_COUNT   0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */
 
#define MDMA_D3_Y_MODIFY   0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */
 
#define MDMA_D3_CURR_DESC_PTR   0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
 
#define MDMA_D3_CURR_ADDR   0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */
 
#define MDMA_D3_IRQ_STATUS   0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
 
#define MDMA_D3_PERIPHERAL_MAP   0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */
 
#define MDMA_D3_CURR_X_COUNT   0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */
 
#define MDMA_D3_CURR_Y_COUNT   0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */
 
#define MDMA_S3_NEXT_DESC_PTR   0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
 
#define MDMA_S3_START_ADDR   0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */
 
#define MDMA_S3_CONFIG   0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */
 
#define MDMA_S3_X_COUNT   0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */
 
#define MDMA_S3_X_MODIFY   0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */
 
#define MDMA_S3_Y_COUNT   0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */
 
#define MDMA_S3_Y_MODIFY   0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */
 
#define MDMA_S3_CURR_DESC_PTR   0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
 
#define MDMA_S3_CURR_ADDR   0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */
 
#define MDMA_S3_IRQ_STATUS   0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
 
#define MDMA_S3_PERIPHERAL_MAP   0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */
 
#define MDMA_S3_CURR_X_COUNT   0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */
 
#define MDMA_S3_CURR_Y_COUNT   0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */
 
#define UART1_DLL   0xffc02000 /* Divisor Latch Low Byte */
 
#define UART1_DLH   0xffc02004 /* Divisor Latch High Byte */
 
#define UART1_GCTL   0xffc02008 /* Global Control Register */
 
#define UART1_LCR   0xffc0200c /* Line Control Register */
 
#define UART1_MCR   0xffc02010 /* Modem Control Register */
 
#define UART1_LSR   0xffc02014 /* Line Status Register */
 
#define UART1_MSR   0xffc02018 /* Modem Status Register */
 
#define UART1_SCR   0xffc0201c /* Scratch Register */
 
#define UART1_IER_SET   0xffc02020 /* Interrupt Enable Register Set */
 
#define UART1_IER_CLEAR   0xffc02024 /* Interrupt Enable Register Clear */
 
#define UART1_THR   0xffc02028 /* Transmit Hold Register */
 
#define UART1_RBR   0xffc0202c /* Receive Buffer Register */
 
#define SPI1_REGBASE   0xffc02300
 
#define SPI1_CTL   0xffc02300 /* SPI1 Control Register */
 
#define SPI1_FLG   0xffc02304 /* SPI1 Flag Register */
 
#define SPI1_STAT   0xffc02308 /* SPI1 Status Register */
 
#define SPI1_TDBR   0xffc0230c /* SPI1 Transmit Data Buffer Register */
 
#define SPI1_RDBR   0xffc02310 /* SPI1 Receive Data Buffer Register */
 
#define SPI1_BAUD   0xffc02314 /* SPI1 Baud Rate Register */
 
#define SPI1_SHADOW   0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */
 
#define SPORT2_TCR1   0xffc02500 /* SPORT2 Transmit Configuration 1 Register */
 
#define SPORT2_TCR2   0xffc02504 /* SPORT2 Transmit Configuration 2 Register */
 
#define SPORT2_TCLKDIV   0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */
 
#define SPORT2_TFSDIV   0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */
 
#define SPORT2_TX   0xffc02510 /* SPORT2 Transmit Data Register */
 
#define SPORT2_RX   0xffc02518 /* SPORT2 Receive Data Register */
 
#define SPORT2_RCR1   0xffc02520 /* SPORT2 Receive Configuration 1 Register */
 
#define SPORT2_RCR2   0xffc02524 /* SPORT2 Receive Configuration 2 Register */
 
#define SPORT2_RCLKDIV   0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */
 
#define SPORT2_RFSDIV   0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */
 
#define SPORT2_STAT   0xffc02530 /* SPORT2 Status Register */
 
#define SPORT2_CHNL   0xffc02534 /* SPORT2 Current Channel Register */
 
#define SPORT2_MCMC1   0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */
 
#define SPORT2_MCMC2   0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */
 
#define SPORT2_MTCS0   0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */
 
#define SPORT2_MTCS1   0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */
 
#define SPORT2_MTCS2   0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */
 
#define SPORT2_MTCS3   0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */
 
#define SPORT2_MRCS0   0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */
 
#define SPORT2_MRCS1   0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */
 
#define SPORT2_MRCS2   0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */
 
#define SPORT2_MRCS3   0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */
 
#define SPORT3_TCR1   0xffc02600 /* SPORT3 Transmit Configuration 1 Register */
 
#define SPORT3_TCR2   0xffc02604 /* SPORT3 Transmit Configuration 2 Register */
 
#define SPORT3_TCLKDIV   0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */
 
#define SPORT3_TFSDIV   0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */
 
#define SPORT3_TX   0xffc02610 /* SPORT3 Transmit Data Register */
 
#define SPORT3_RX   0xffc02618 /* SPORT3 Receive Data Register */
 
#define SPORT3_RCR1   0xffc02620 /* SPORT3 Receive Configuration 1 Register */
 
#define SPORT3_RCR2   0xffc02624 /* SPORT3 Receive Configuration 2 Register */
 
#define SPORT3_RCLKDIV   0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */
 
#define SPORT3_RFSDIV   0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */
 
#define SPORT3_STAT   0xffc02630 /* SPORT3 Status Register */
 
#define SPORT3_CHNL   0xffc02634 /* SPORT3 Current Channel Register */
 
#define SPORT3_MCMC1   0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */
 
#define SPORT3_MCMC2   0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */
 
#define SPORT3_MTCS0   0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */
 
#define SPORT3_MTCS1   0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */
 
#define SPORT3_MTCS2   0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */
 
#define SPORT3_MTCS3   0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */
 
#define SPORT3_MRCS0   0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */
 
#define SPORT3_MRCS1   0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */
 
#define SPORT3_MRCS2   0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */
 
#define SPORT3_MRCS3   0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */
 
#define EPPI2_STATUS   0xffc02900 /* EPPI2 Status Register */
 
#define EPPI2_HCOUNT   0xffc02904 /* EPPI2 Horizontal Transfer Count Register */
 
#define EPPI2_HDELAY   0xffc02908 /* EPPI2 Horizontal Delay Count Register */
 
#define EPPI2_VCOUNT   0xffc0290c /* EPPI2 Vertical Transfer Count Register */
 
#define EPPI2_VDELAY   0xffc02910 /* EPPI2 Vertical Delay Count Register */
 
#define EPPI2_FRAME   0xffc02914 /* EPPI2 Lines per Frame Register */
 
#define EPPI2_LINE   0xffc02918 /* EPPI2 Samples per Line Register */
 
#define EPPI2_CLKDIV   0xffc0291c /* EPPI2 Clock Divide Register */
 
#define EPPI2_CONTROL   0xffc02920 /* EPPI2 Control Register */
 
#define EPPI2_FS1W_HBL   0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
 
#define EPPI2_FS1P_AVPL   0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
 
#define EPPI2_FS2W_LVB   0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
 
#define EPPI2_FS2P_LAVF   0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
 
#define EPPI2_CLIP   0xffc02934 /* EPPI2 Clipping Register */
 
#define CAN0_MC1   0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */
 
#define CAN0_MD1   0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */
 
#define CAN0_TRS1   0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */
 
#define CAN0_TRR1   0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */
 
#define CAN0_TA1   0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
 
#define CAN0_AA1   0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */
 
#define CAN0_RMP1   0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */
 
#define CAN0_RML1   0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */
 
#define CAN0_MBTIF1   0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
 
#define CAN0_MBRIF1   0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
 
#define CAN0_MBIM1   0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
 
#define CAN0_RFH1   0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
 
#define CAN0_OPSS1   0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
 
#define CAN0_MC2   0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */
 
#define CAN0_MD2   0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */
 
#define CAN0_TRS2   0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */
 
#define CAN0_TRR2   0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */
 
#define CAN0_TA2   0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
 
#define CAN0_AA2   0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */
 
#define CAN0_RMP2   0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */
 
#define CAN0_RML2   0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */
 
#define CAN0_MBTIF2   0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
 
#define CAN0_MBRIF2   0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
 
#define CAN0_MBIM2   0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
 
#define CAN0_RFH2   0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
 
#define CAN0_OPSS2   0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
 
#define CAN0_CLOCK   0xffc02a80 /* CAN Controller 0 Clock Register */
 
#define CAN0_TIMING   0xffc02a84 /* CAN Controller 0 Timing Register */
 
#define CAN0_DEBUG   0xffc02a88 /* CAN Controller 0 Debug Register */
 
#define CAN0_STATUS   0xffc02a8c /* CAN Controller 0 Global Status Register */
 
#define CAN0_CEC   0xffc02a90 /* CAN Controller 0 Error Counter Register */
 
#define CAN0_GIS   0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */
 
#define CAN0_GIM   0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */
 
#define CAN0_GIF   0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */
 
#define CAN0_CONTROL   0xffc02aa0 /* CAN Controller 0 Master Control Register */
 
#define CAN0_INTR   0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */
 
#define CAN0_MBTD   0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */
 
#define CAN0_EWR   0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */
 
#define CAN0_ESR   0xffc02ab4 /* CAN Controller 0 Error Status Register */
 
#define CAN0_UCCNT   0xffc02ac4 /* CAN Controller 0 Universal Counter Register */
 
#define CAN0_UCRC   0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */
 
#define CAN0_UCCNF   0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */
 
#define CAN0_AM00L   0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
 
#define CAN0_AM00H   0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
 
#define CAN0_AM01L   0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
 
#define CAN0_AM01H   0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
 
#define CAN0_AM02L   0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
 
#define CAN0_AM02H   0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
 
#define CAN0_AM03L   0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
 
#define CAN0_AM03H   0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
 
#define CAN0_AM04L   0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
 
#define CAN0_AM04H   0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
 
#define CAN0_AM05L   0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
 
#define CAN0_AM05H   0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
 
#define CAN0_AM06L   0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
 
#define CAN0_AM06H   0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
 
#define CAN0_AM07L   0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
 
#define CAN0_AM07H   0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
 
#define CAN0_AM08L   0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
 
#define CAN0_AM08H   0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
 
#define CAN0_AM09L   0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
 
#define CAN0_AM09H   0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
 
#define CAN0_AM10L   0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
 
#define CAN0_AM10H   0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
 
#define CAN0_AM11L   0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
 
#define CAN0_AM11H   0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
 
#define CAN0_AM12L   0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
 
#define CAN0_AM12H   0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
 
#define CAN0_AM13L   0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
 
#define CAN0_AM13H   0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
 
#define CAN0_AM14L   0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
 
#define CAN0_AM14H   0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
 
#define CAN0_AM15L   0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
 
#define CAN0_AM15H   0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
 
#define CAN0_AM16L   0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
 
#define CAN0_AM16H   0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
 
#define CAN0_AM17L   0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
 
#define CAN0_AM17H   0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
 
#define CAN0_AM18L   0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
 
#define CAN0_AM18H   0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
 
#define CAN0_AM19L   0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
 
#define CAN0_AM19H   0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
 
#define CAN0_AM20L   0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
 
#define CAN0_AM20H   0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
 
#define CAN0_AM21L   0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
 
#define CAN0_AM21H   0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
 
#define CAN0_AM22L   0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
 
#define CAN0_AM22H   0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
 
#define CAN0_AM23L   0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
 
#define CAN0_AM23H   0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
 
#define CAN0_AM24L   0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
 
#define CAN0_AM24H   0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
 
#define CAN0_AM25L   0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
 
#define CAN0_AM25H   0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
 
#define CAN0_AM26L   0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
 
#define CAN0_AM26H   0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
 
#define CAN0_AM27L   0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
 
#define CAN0_AM27H   0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
 
#define CAN0_AM28L   0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
 
#define CAN0_AM28H   0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
 
#define CAN0_AM29L   0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
 
#define CAN0_AM29H   0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
 
#define CAN0_AM30L   0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
 
#define CAN0_AM30H   0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
 
#define CAN0_AM31L   0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
 
#define CAN0_AM31H   0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
 
#define CAN0_MB00_DATA0   0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
 
#define CAN0_MB00_DATA1   0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
 
#define CAN0_MB00_DATA2   0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
 
#define CAN0_MB00_DATA3   0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */
 
#define CAN0_MB00_LENGTH   0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */
 
#define CAN0_MB00_TIMESTAMP   0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
 
#define CAN0_MB00_ID0   0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */
 
#define CAN0_MB00_ID1   0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */
 
#define CAN0_MB01_DATA0   0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
 
#define CAN0_MB01_DATA1   0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
 
#define CAN0_MB01_DATA2   0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
 
#define CAN0_MB01_DATA3   0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */
 
#define CAN0_MB01_LENGTH   0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */
 
#define CAN0_MB01_TIMESTAMP   0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
 
#define CAN0_MB01_ID0   0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */
 
#define CAN0_MB01_ID1   0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */
 
#define CAN0_MB02_DATA0   0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
 
#define CAN0_MB02_DATA1   0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
 
#define CAN0_MB02_DATA2   0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
 
#define CAN0_MB02_DATA3   0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */
 
#define CAN0_MB02_LENGTH   0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */
 
#define CAN0_MB02_TIMESTAMP   0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
 
#define CAN0_MB02_ID0   0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */
 
#define CAN0_MB02_ID1   0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */
 
#define CAN0_MB03_DATA0   0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
 
#define CAN0_MB03_DATA1   0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
 
#define CAN0_MB03_DATA2   0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
 
#define CAN0_MB03_DATA3   0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */
 
#define CAN0_MB03_LENGTH   0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */
 
#define CAN0_MB03_TIMESTAMP   0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
 
#define CAN0_MB03_ID0   0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */
 
#define CAN0_MB03_ID1   0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */
 
#define CAN0_MB04_DATA0   0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
 
#define CAN0_MB04_DATA1   0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
 
#define CAN0_MB04_DATA2   0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
 
#define CAN0_MB04_DATA3   0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */
 
#define CAN0_MB04_LENGTH   0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */
 
#define CAN0_MB04_TIMESTAMP   0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
 
#define CAN0_MB04_ID0   0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */
 
#define CAN0_MB04_ID1   0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */
 
#define CAN0_MB05_DATA0   0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
 
#define CAN0_MB05_DATA1   0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
 
#define CAN0_MB05_DATA2   0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
 
#define CAN0_MB05_DATA3   0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */
 
#define CAN0_MB05_LENGTH   0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */
 
#define CAN0_MB05_TIMESTAMP   0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
 
#define CAN0_MB05_ID0   0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */
 
#define CAN0_MB05_ID1   0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */
 
#define CAN0_MB06_DATA0   0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
 
#define CAN0_MB06_DATA1   0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
 
#define CAN0_MB06_DATA2   0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
 
#define CAN0_MB06_DATA3   0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */
 
#define CAN0_MB06_LENGTH   0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */
 
#define CAN0_MB06_TIMESTAMP   0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
 
#define CAN0_MB06_ID0   0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */
 
#define CAN0_MB06_ID1   0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */
 
#define CAN0_MB07_DATA0   0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
 
#define CAN0_MB07_DATA1   0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
 
#define CAN0_MB07_DATA2   0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
 
#define CAN0_MB07_DATA3   0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */
 
#define CAN0_MB07_LENGTH   0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */
 
#define CAN0_MB07_TIMESTAMP   0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
 
#define CAN0_MB07_ID0   0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */
 
#define CAN0_MB07_ID1   0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */
 
#define CAN0_MB08_DATA0   0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
 
#define CAN0_MB08_DATA1   0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
 
#define CAN0_MB08_DATA2   0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
 
#define CAN0_MB08_DATA3   0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */
 
#define CAN0_MB08_LENGTH   0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */
 
#define CAN0_MB08_TIMESTAMP   0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
 
#define CAN0_MB08_ID0   0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */
 
#define CAN0_MB08_ID1   0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */
 
#define CAN0_MB09_DATA0   0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
 
#define CAN0_MB09_DATA1   0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
 
#define CAN0_MB09_DATA2   0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
 
#define CAN0_MB09_DATA3   0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */
 
#define CAN0_MB09_LENGTH   0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */
 
#define CAN0_MB09_TIMESTAMP   0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
 
#define CAN0_MB09_ID0   0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */
 
#define CAN0_MB09_ID1   0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */
 
#define CAN0_MB10_DATA0   0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
 
#define CAN0_MB10_DATA1   0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
 
#define CAN0_MB10_DATA2   0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
 
#define CAN0_MB10_DATA3   0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */
 
#define CAN0_MB10_LENGTH   0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */
 
#define CAN0_MB10_TIMESTAMP   0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
 
#define CAN0_MB10_ID0   0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */
 
#define CAN0_MB10_ID1   0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */
 
#define CAN0_MB11_DATA0   0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
 
#define CAN0_MB11_DATA1   0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
 
#define CAN0_MB11_DATA2   0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
 
#define CAN0_MB11_DATA3   0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */
 
#define CAN0_MB11_LENGTH   0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */
 
#define CAN0_MB11_TIMESTAMP   0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
 
#define CAN0_MB11_ID0   0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */
 
#define CAN0_MB11_ID1   0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */
 
#define CAN0_MB12_DATA0   0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
 
#define CAN0_MB12_DATA1   0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
 
#define CAN0_MB12_DATA2   0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
 
#define CAN0_MB12_DATA3   0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */
 
#define CAN0_MB12_LENGTH   0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */
 
#define CAN0_MB12_TIMESTAMP   0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
 
#define CAN0_MB12_ID0   0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */
 
#define CAN0_MB12_ID1   0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */
 
#define CAN0_MB13_DATA0   0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
 
#define CAN0_MB13_DATA1   0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
 
#define CAN0_MB13_DATA2   0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
 
#define CAN0_MB13_DATA3   0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */
 
#define CAN0_MB13_LENGTH   0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */
 
#define CAN0_MB13_TIMESTAMP   0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
 
#define CAN0_MB13_ID0   0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */
 
#define CAN0_MB13_ID1   0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */
 
#define CAN0_MB14_DATA0   0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
 
#define CAN0_MB14_DATA1   0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
 
#define CAN0_MB14_DATA2   0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
 
#define CAN0_MB14_DATA3   0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */
 
#define CAN0_MB14_LENGTH   0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */
 
#define CAN0_MB14_TIMESTAMP   0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
 
#define CAN0_MB14_ID0   0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */
 
#define CAN0_MB14_ID1   0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */
 
#define CAN0_MB15_DATA0   0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
 
#define CAN0_MB15_DATA1   0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
 
#define CAN0_MB15_DATA2   0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
 
#define CAN0_MB15_DATA3   0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */
 
#define CAN0_MB15_LENGTH   0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */
 
#define CAN0_MB15_TIMESTAMP   0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
 
#define CAN0_MB15_ID0   0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */
 
#define CAN0_MB15_ID1   0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */
 
#define CAN0_MB16_DATA0   0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
 
#define CAN0_MB16_DATA1   0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
 
#define CAN0_MB16_DATA2   0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
 
#define CAN0_MB16_DATA3   0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */
 
#define CAN0_MB16_LENGTH   0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */
 
#define CAN0_MB16_TIMESTAMP   0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
 
#define CAN0_MB16_ID0   0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */
 
#define CAN0_MB16_ID1   0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */
 
#define CAN0_MB17_DATA0   0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
 
#define CAN0_MB17_DATA1   0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
 
#define CAN0_MB17_DATA2   0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
 
#define CAN0_MB17_DATA3   0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */
 
#define CAN0_MB17_LENGTH   0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */
 
#define CAN0_MB17_TIMESTAMP   0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
 
#define CAN0_MB17_ID0   0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */
 
#define CAN0_MB17_ID1   0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */
 
#define CAN0_MB18_DATA0   0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
 
#define CAN0_MB18_DATA1   0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
 
#define CAN0_MB18_DATA2   0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
 
#define CAN0_MB18_DATA3   0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */
 
#define CAN0_MB18_LENGTH   0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */
 
#define CAN0_MB18_TIMESTAMP   0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
 
#define CAN0_MB18_ID0   0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */
 
#define CAN0_MB18_ID1   0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */
 
#define CAN0_MB19_DATA0   0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
 
#define CAN0_MB19_DATA1   0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
 
#define CAN0_MB19_DATA2   0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
 
#define CAN0_MB19_DATA3   0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */
 
#define CAN0_MB19_LENGTH   0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */
 
#define CAN0_MB19_TIMESTAMP   0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
 
#define CAN0_MB19_ID0   0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */
 
#define CAN0_MB19_ID1   0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */
 
#define CAN0_MB20_DATA0   0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
 
#define CAN0_MB20_DATA1   0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
 
#define CAN0_MB20_DATA2   0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
 
#define CAN0_MB20_DATA3   0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */
 
#define CAN0_MB20_LENGTH   0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */
 
#define CAN0_MB20_TIMESTAMP   0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
 
#define CAN0_MB20_ID0   0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */
 
#define CAN0_MB20_ID1   0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */
 
#define CAN0_MB21_DATA0   0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
 
#define CAN0_MB21_DATA1   0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
 
#define CAN0_MB21_DATA2   0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
 
#define CAN0_MB21_DATA3   0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */
 
#define CAN0_MB21_LENGTH   0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */
 
#define CAN0_MB21_TIMESTAMP   0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
 
#define CAN0_MB21_ID0   0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */
 
#define CAN0_MB21_ID1   0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */
 
#define CAN0_MB22_DATA0   0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
 
#define CAN0_MB22_DATA1   0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
 
#define CAN0_MB22_DATA2   0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
 
#define CAN0_MB22_DATA3   0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */
 
#define CAN0_MB22_LENGTH   0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */
 
#define CAN0_MB22_TIMESTAMP   0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
 
#define CAN0_MB22_ID0   0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */
 
#define CAN0_MB22_ID1   0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */
 
#define CAN0_MB23_DATA0   0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
 
#define CAN0_MB23_DATA1   0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
 
#define CAN0_MB23_DATA2   0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
 
#define CAN0_MB23_DATA3   0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */
 
#define CAN0_MB23_LENGTH   0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */
 
#define CAN0_MB23_TIMESTAMP   0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
 
#define CAN0_MB23_ID0   0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */
 
#define CAN0_MB23_ID1   0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */
 
#define CAN0_MB24_DATA0   0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
 
#define CAN0_MB24_DATA1   0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
 
#define CAN0_MB24_DATA2   0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
 
#define CAN0_MB24_DATA3   0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */
 
#define CAN0_MB24_LENGTH   0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */
 
#define CAN0_MB24_TIMESTAMP   0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
 
#define CAN0_MB24_ID0   0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */
 
#define CAN0_MB24_ID1   0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */
 
#define CAN0_MB25_DATA0   0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
 
#define CAN0_MB25_DATA1   0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
 
#define CAN0_MB25_DATA2   0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
 
#define CAN0_MB25_DATA3   0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */
 
#define CAN0_MB25_LENGTH   0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */
 
#define CAN0_MB25_TIMESTAMP   0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
 
#define CAN0_MB25_ID0   0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */
 
#define CAN0_MB25_ID1   0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */
 
#define CAN0_MB26_DATA0   0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
 
#define CAN0_MB26_DATA1   0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
 
#define CAN0_MB26_DATA2   0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
 
#define CAN0_MB26_DATA3   0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */
 
#define CAN0_MB26_LENGTH   0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */
 
#define CAN0_MB26_TIMESTAMP   0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
 
#define CAN0_MB26_ID0   0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */
 
#define CAN0_MB26_ID1   0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */
 
#define CAN0_MB27_DATA0   0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
 
#define CAN0_MB27_DATA1   0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
 
#define CAN0_MB27_DATA2   0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
 
#define CAN0_MB27_DATA3   0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */
 
#define CAN0_MB27_LENGTH   0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */
 
#define CAN0_MB27_TIMESTAMP   0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
 
#define CAN0_MB27_ID0   0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */
 
#define CAN0_MB27_ID1   0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */
 
#define CAN0_MB28_DATA0   0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
 
#define CAN0_MB28_DATA1   0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
 
#define CAN0_MB28_DATA2   0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
 
#define CAN0_MB28_DATA3   0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */
 
#define CAN0_MB28_LENGTH   0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */
 
#define CAN0_MB28_TIMESTAMP   0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
 
#define CAN0_MB28_ID0   0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */
 
#define CAN0_MB28_ID1   0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */
 
#define CAN0_MB29_DATA0   0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
 
#define CAN0_MB29_DATA1   0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
 
#define CAN0_MB29_DATA2   0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
 
#define CAN0_MB29_DATA3   0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */
 
#define CAN0_MB29_LENGTH   0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */
 
#define CAN0_MB29_TIMESTAMP   0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
 
#define CAN0_MB29_ID0   0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */
 
#define CAN0_MB29_ID1   0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */
 
#define CAN0_MB30_DATA0   0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
 
#define CAN0_MB30_DATA1   0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
 
#define CAN0_MB30_DATA2   0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
 
#define CAN0_MB30_DATA3   0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */
 
#define CAN0_MB30_LENGTH   0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */
 
#define CAN0_MB30_TIMESTAMP   0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
 
#define CAN0_MB30_ID0   0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */
 
#define CAN0_MB30_ID1   0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */
 
#define CAN0_MB31_DATA0   0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
 
#define CAN0_MB31_DATA1   0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
 
#define CAN0_MB31_DATA2   0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
 
#define CAN0_MB31_DATA3   0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */
 
#define CAN0_MB31_LENGTH   0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */
 
#define CAN0_MB31_TIMESTAMP   0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
 
#define CAN0_MB31_ID0   0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */
 
#define CAN0_MB31_ID1   0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */
 
#define UART3_DLL   0xffc03100 /* Divisor Latch Low Byte */
 
#define UART3_DLH   0xffc03104 /* Divisor Latch High Byte */
 
#define UART3_GCTL   0xffc03108 /* Global Control Register */
 
#define UART3_LCR   0xffc0310c /* Line Control Register */
 
#define UART3_MCR   0xffc03110 /* Modem Control Register */
 
#define UART3_LSR   0xffc03114 /* Line Status Register */
 
#define UART3_MSR   0xffc03118 /* Modem Status Register */
 
#define UART3_SCR   0xffc0311c /* Scratch Register */
 
#define UART3_IER_SET   0xffc03120 /* Interrupt Enable Register Set */
 
#define UART3_IER_CLEAR   0xffc03124 /* Interrupt Enable Register Clear */
 
#define UART3_THR   0xffc03128 /* Transmit Hold Register */
 
#define UART3_RBR   0xffc0312c /* Receive Buffer Register */
 
#define NFC_CTL   0xffc03b00 /* NAND Control Register */
 
#define NFC_STAT   0xffc03b04 /* NAND Status Register */
 
#define NFC_IRQSTAT   0xffc03b08 /* NAND Interrupt Status Register */
 
#define NFC_IRQMASK   0xffc03b0c /* NAND Interrupt Mask Register */
 
#define NFC_ECC0   0xffc03b10 /* NAND ECC Register 0 */
 
#define NFC_ECC1   0xffc03b14 /* NAND ECC Register 1 */
 
#define NFC_ECC2   0xffc03b18 /* NAND ECC Register 2 */
 
#define NFC_ECC3   0xffc03b1c /* NAND ECC Register 3 */
 
#define NFC_COUNT   0xffc03b20 /* NAND ECC Count Register */
 
#define NFC_RST   0xffc03b24 /* NAND ECC Reset Register */
 
#define NFC_PGCTL   0xffc03b28 /* NAND Page Control Register */
 
#define NFC_READ   0xffc03b2c /* NAND Read Data Register */
 
#define NFC_ADDR   0xffc03b40 /* NAND Address Register */
 
#define NFC_CMD   0xffc03b44 /* NAND Command Register */
 
#define NFC_DATA_WR   0xffc03b48 /* NAND Data Write Register */
 
#define NFC_DATA_RD   0xffc03b4c /* NAND Data Read Register */
 
#define CNT_CONFIG   0xffc04200 /* Configuration Register */
 
#define CNT_IMASK   0xffc04204 /* Interrupt Mask Register */
 
#define CNT_STATUS   0xffc04208 /* Status Register */
 
#define CNT_COMMAND   0xffc0420c /* Command Register */
 
#define CNT_DEBOUNCE   0xffc04210 /* Debounce Register */
 
#define CNT_COUNTER   0xffc04214 /* Counter Register */
 
#define CNT_MAX   0xffc04218 /* Maximal Count Register */
 
#define CNT_MIN   0xffc0421c /* Minimal Count Register */
 
#define OTP_CONTROL   0xffc04300 /* OTP/Fuse Control Register */
 
#define OTP_BEN   0xffc04304 /* OTP/Fuse Byte Enable */
 
#define OTP_STATUS   0xffc04308 /* OTP/Fuse Status */
 
#define OTP_TIMING   0xffc0430c /* OTP/Fuse Access Timing */
 
#define SECURE_SYSSWT   0xffc04320 /* Secure System Switches */
 
#define SECURE_CONTROL   0xffc04324 /* Secure Control */
 
#define SECURE_STATUS   0xffc04328 /* Secure Status */
 
#define DMAC1_PERIMUX   0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */
 
#define OTP_DATA0   0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 
#define OTP_DATA1   0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 
#define OTP_DATA2   0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 
#define OTP_DATA3   0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 
#define SIC_UNMASK_ALL   0x00000000 /* Unmask all peripheral interrupts */
 
#define SIC_MASK_ALL   0xFFFFFFFF /* Mask all peripheral interrupts */
 
#define SIC_MASK(x)   (1 << (x)) /* Mask Peripheral #x interrupt */
 
#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
 
#define IWR_DISABLE_ALL   0x00000000 /* Wakeup Disable all peripherals */
 
#define IWR_ENABLE_ALL   0xFFFFFFFF /* Wakeup Enable all peripherals */
 
#define IWR_ENABLE(x)   (1 << (x)) /* Wakeup Enable Peripheral #x */
 
#define IWR_DISABLE(x)   (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
 
#define PLL_WAKEUP   0x1 /* PLL Wakeup */
 
#define DMA0_ERR   0x2 /* DMA Controller 0 Error */
 
#define EPPI0_ERR   0x4 /* EPPI0 Error */
 
#define SPORT0_ERR   0x8 /* SPORT0 Error */
 
#define SPORT1_ERR   0x10 /* SPORT1 Error */
 
#define SPI0_ERR   0x20 /* SPI0 Error */
 
#define UART0_ERR   0x40 /* UART0 Error */
 
#define RTC   0x80 /* Real-Time Clock */
 
#define DMA12   0x100 /* DMA Channel 12 */
 
#define DMA0   0x200 /* DMA Channel 0 */
 
#define DMA1   0x400 /* DMA Channel 1 */
 
#define DMA2   0x800 /* DMA Channel 2 */
 
#define DMA3   0x1000 /* DMA Channel 3 */
 
#define DMA4   0x2000 /* DMA Channel 4 */
 
#define DMA6   0x4000 /* DMA Channel 6 */
 
#define DMA7   0x8000 /* DMA Channel 7 */
 
#define PINT0   0x80000 /* Pin Interrupt 0 */
 
#define PINT1   0x100000 /* Pin Interrupt 1 */
 
#define MDMA0   0x200000 /* Memory DMA Stream 0 */
 
#define MDMA1   0x400000 /* Memory DMA Stream 1 */
 
#define WDOG   0x800000 /* Watchdog Timer */
 
#define DMA1_ERR   0x1000000 /* DMA Controller 1 Error */
 
#define SPORT2_ERR   0x2000000 /* SPORT2 Error */
 
#define SPORT3_ERR   0x4000000 /* SPORT3 Error */
 
#define MXVR_SD   0x8000000 /* MXVR Synchronous Data */
 
#define SPI1_ERR   0x10000000 /* SPI1 Error */
 
#define SPI2_ERR   0x20000000 /* SPI2 Error */
 
#define UART1_ERR   0x40000000 /* UART1 Error */
 
#define UART2_ERR   0x80000000 /* UART2 Error */
 
#define CAN0_ERR   0x1 /* CAN0 Error */
 
#define DMA18   0x2 /* DMA Channel 18 */
 
#define DMA19   0x4 /* DMA Channel 19 */
 
#define DMA20   0x8 /* DMA Channel 20 */
 
#define DMA21   0x10 /* DMA Channel 21 */
 
#define DMA13   0x20 /* DMA Channel 13 */
 
#define DMA14   0x40 /* DMA Channel 14 */
 
#define DMA5   0x80 /* DMA Channel 5 */
 
#define DMA23   0x100 /* DMA Channel 23 */
 
#define DMA8   0x200 /* DMA Channel 8 */
 
#define DMA9   0x400 /* DMA Channel 9 */
 
#define DMA10   0x800 /* DMA Channel 10 */
 
#define DMA11   0x1000 /* DMA Channel 11 */
 
#define TWI0   0x2000 /* TWI0 */
 
#define TWI1   0x4000 /* TWI1 */
 
#define CAN0_RX   0x8000 /* CAN0 Receive */
 
#define CAN0_TX   0x10000 /* CAN0 Transmit */
 
#define MDMA2   0x20000 /* Memory DMA Stream 0 */
 
#define MDMA3   0x40000 /* Memory DMA Stream 1 */
 
#define MXVR_STAT   0x80000 /* MXVR Status */
 
#define MXVR_CM   0x100000 /* MXVR Control Message */
 
#define MXVR_AP   0x200000 /* MXVR Asynchronous Packet */
 
#define EPPI1_ERR   0x400000 /* EPPI1 Error */
 
#define EPPI2_ERR   0x800000 /* EPPI2 Error */
 
#define UART3_ERR   0x1000000 /* UART3 Error */
 
#define HOST_ERR   0x2000000 /* Host DMA Port Error */
 
#define USB_ERR   0x4000000 /* USB Error */
 
#define PIXC_ERR   0x8000000 /* Pixel Compositor Error */
 
#define NFC_ERR   0x10000000 /* Nand Flash Controller Error */
 
#define ATAPI_ERR   0x20000000 /* ATAPI Error */
 
#define CAN1_ERR   0x40000000 /* CAN1 Error */
 
#define DMAR0_ERR   0x80000000 /* DMAR0 Overflow Error */
 
#define DMAR1_ERR   0x80000000 /* DMAR1 Overflow Error */
 
#define DMAR0   0x80000000 /* DMAR0 Block */
 
#define DMAR1   0x80000000 /* DMAR1 Block */
 
#define DMA15   0x1 /* DMA Channel 15 */
 
#define DMA16   0x2 /* DMA Channel 16 */
 
#define DMA17   0x4 /* DMA Channel 17 */
 
#define DMA22   0x8 /* DMA Channel 22 */
 
#define CNT   0x10 /* Counter */
 
#define KEY   0x20 /* Keypad */
 
#define CAN1_RX   0x40 /* CAN1 Receive */
 
#define CAN1_TX   0x80 /* CAN1 Transmit */
 
#define SDH_INT_MASK0   0x100 /* SDH Mask 0 */
 
#define SDH_INT_MASK1   0x200 /* SDH Mask 1 */
 
#define USB_EINT   0x400 /* USB Exception */
 
#define USB_INT0   0x800 /* USB Interrupt 0 */
 
#define USB_INT1   0x1000 /* USB Interrupt 1 */
 
#define USB_INT2   0x2000 /* USB Interrupt 2 */
 
#define USB_DMAINT   0x4000 /* USB DMA */
 
#define OTPSEC   0x8000 /* OTP Access Complete */
 
#define TIMER0   0x400000 /* Timer 0 */
 
#define TIMER1   0x800000 /* Timer 1 */
 
#define TIMER2   0x1000000 /* Timer 2 */
 
#define TIMER3   0x2000000 /* Timer 3 */
 
#define TIMER4   0x4000000 /* Timer 4 */
 
#define TIMER5   0x8000000 /* Timer 5 */
 
#define TIMER6   0x10000000 /* Timer 6 */
 
#define TIMER7   0x20000000 /* Timer 7 */
 
#define PINT2   0x40000000 /* Pin Interrupt 2 */
 
#define PINT3   0x80000000 /* Pin Interrupt 3 */
 
#define CTYPE   0x40 /* DMA Channel Type */
 
#define PMAP   0xf000 /* Peripheral Mapped To This Channel */
 
#define DCB_TRAFFIC_PERIOD   0xf /* DCB Traffic Control Period */
 
#define DEB_TRAFFIC_PERIOD   0xf0 /* DEB Traffic Control Period */
 
#define DAB_TRAFFIC_PERIOD   0x700 /* DAB Traffic Control Period */
 
#define MDMA_ROUND_ROBIN_PERIOD   0xf800 /* MDMA Round Robin Period */
 
#define DCB_TRAFFIC_COUNT   0xf /* DCB Traffic Control Count */
 
#define DEB_TRAFFIC_COUNT   0xf0 /* DEB Traffic Control Count */
 
#define DAB_TRAFFIC_COUNT   0x700 /* DAB Traffic Control Count */
 
#define MDMA_ROUND_ROBIN_COUNT   0xf800 /* MDMA Round Robin Count */
 
#define PMUXSDH   0x1 /* Peripheral Select for DMA22 channel */
 
#define AMCKEN   0x0001 /* Enable CLKOUT */
 
#define AMBEN_NONE   0x0000 /* All Banks Disabled */
 
#define AMBEN_B0   0x0002 /* Enable Async Memory Bank 0 only */
 
#define AMBEN_B0_B1   0x0004 /* Enable Async Memory Banks 0 & 1 only */
 
#define AMBEN_B0_B1_B2   0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
 
#define AMBEN_ALL   0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
 
#define B0RDYEN   0x1 /* Bank 0 ARDY Enable */
 
#define B0RDYPOL   0x2 /* Bank 0 ARDY Polarity */
 
#define B0TT   0xc /* Bank 0 transition time */
 
#define B0ST   0x30 /* Bank 0 Setup time */
 
#define B0HT   0xc0 /* Bank 0 Hold time */
 
#define B0RAT   0xf00 /* Bank 0 Read access time */
 
#define B0WAT   0xf000 /* Bank 0 write access time */
 
#define B1RDYEN   0x10000 /* Bank 1 ARDY Enable */
 
#define B1RDYPOL   0x20000 /* Bank 1 ARDY Polarity */
 
#define B1TT   0xc0000 /* Bank 1 transition time */
 
#define B1ST   0x300000 /* Bank 1 Setup time */
 
#define B1HT   0xc00000 /* Bank 1 Hold time */
 
#define B1RAT   0xf000000 /* Bank 1 Read access time */
 
#define B1WAT   0xf0000000 /* Bank 1 write access time */
 
#define B2RDYEN   0x1 /* Bank 2 ARDY Enable */
 
#define B2RDYPOL   0x2 /* Bank 2 ARDY Polarity */
 
#define B2TT   0xc /* Bank 2 transition time */
 
#define B2ST   0x30 /* Bank 2 Setup time */
 
#define B2HT   0xc0 /* Bank 2 Hold time */
 
#define B2RAT   0xf00 /* Bank 2 Read access time */
 
#define B2WAT   0xf000 /* Bank 2 write access time */
 
#define B3RDYEN   0x10000 /* Bank 3 ARDY Enable */
 
#define B3RDYPOL   0x20000 /* Bank 3 ARDY Polarity */
 
#define B3TT   0xc0000 /* Bank 3 transition time */
 
#define B3ST   0x300000 /* Bank 3 Setup time */
 
#define B3HT   0xc00000 /* Bank 3 Hold time */
 
#define B3RAT   0xf000000 /* Bank 3 Read access time */
 
#define B3WAT   0xf0000000 /* Bank 3 write access time */
 
#define AMSB0CTL   0x3 /* Async Memory Bank 0 select */
 
#define AMSB1CTL   0xc /* Async Memory Bank 1 select */
 
#define AMSB2CTL   0x30 /* Async Memory Bank 2 select */
 
#define AMSB3CTL   0xc0 /* Async Memory Bank 3 select */
 
#define B0MODE   0x3 /* Async Memory Bank 0 Access Mode */
 
#define B1MODE   0xc /* Async Memory Bank 1 Access Mode */
 
#define B2MODE   0x30 /* Async Memory Bank 2 Access Mode */
 
#define B3MODE   0xc0 /* Async Memory Bank 3 Access Mode */
 
#define TESTSETLOCK   0x1 /* Test set lock */
 
#define BCLK   0x6 /* Burst clock frequency */
 
#define PGWS   0x38 /* Page wait states */
 
#define PGSZ   0x40 /* Page size */
 
#define RDDL   0x380 /* Read data delay */
 
#define ARBSTAT   0x1 /* Arbitration status */
 
#define BGSTAT   0x2 /* Bus grant status */
 
#define TREFI   0x3fff /* Refresh Interval */
 
#define TRFC   0x3c000 /* Auto-refresh command period */
 
#define TRP   0x3c0000 /* Pre charge-to-active command period */
 
#define TRAS   0x3c00000 /* Min Active-to-pre charge time */
 
#define TRC   0x3c000000 /* Active-to-active time */
 
#define DDR_TRAS(x)   ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
 
#define DDR_TRP(x)   ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
 
#define DDR_TRC(x)   ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
 
#define DDR_TRFC(x)   ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
 
#define DDR_TREFI(x)   (x&TREFI) /* DDR tRFC = (1~15) cycles */
 
#define TRCD   0xf /* Active-to-Read/write delay */
 
#define TMRD   0xf0 /* Mode register set to active */
 
#define TWR   0x300 /* Write Recovery time */
 
#define DDRDATWIDTH   0x3000 /* DDR data width */
 
#define EXTBANKS   0xc000 /* External banks */
 
#define DDRDEVWIDTH   0x30000 /* DDR device width */
 
#define DDRDEVSIZE   0xc0000 /* DDR device size */
 
#define TWTR   0xf0000000 /* Write-to-read delay */
 
#define DDR_TWTR(x)   ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
 
#define DDR_TMRD(x)   ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
 
#define DDR_TWR(x)   ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
 
#define DDR_TRCD(x)   (x&TRCD) /* DDR tRCD = (1~15) cycles */
 
#define DDR_DATWIDTH   0x2000 /* DDR data width */
 
#define EXTBANK_1   0 /* 1 external bank */
 
#define EXTBANK_2   0x4000 /* 2 external banks */
 
#define DEVSZ_64   0x40000 /* DDR External Bank Size = 64MB */
 
#define DEVSZ_128   0x80000 /* DDR External Bank Size = 128MB */
 
#define DEVSZ_256   0xc0000 /* DDR External Bank Size = 256MB */
 
#define DEVSZ_512   0 /* DDR External Bank Size = 512MB */
 
#define DEVWD_4   0 /* DDR Device Width = 4 Bits */
 
#define DEVWD_8   0x10000 /* DDR Device Width = 8 Bits */
 
#define DEVWD_16   0x20000 /* DDR Device Width = 16 Bits */
 
#define BURSTLENGTH   0x7 /* Burst length */
 
#define CASLATENCY   0x70 /* CAS latency */
 
#define DLLRESET   0x100 /* DLL Reset */
 
#define REGE   0x1000 /* Register mode enable */
 
#define CL_1_5   0x50 /* DDR CAS Latency = 1.5 cycles */
 
#define CL_2   0x20 /* DDR CAS Latency = 2 cycles */
 
#define CL_2_5   0x60 /* DDR CAS Latency = 2.5 cycles */
 
#define CL_3   0x30 /* DDR CAS Latency = 3 cycles */
 
#define PASR   0x7 /* Partial array self-refresh */
 
#define DEB1_PFLEN   0x3 /* Pre fetch length for DEB1 accesses */
 
#define DEB2_PFLEN   0xc /* Pre fetch length for DEB2 accesses */
 
#define DEB3_PFLEN   0x30 /* Pre fetch length for DEB3 accesses */
 
#define DEB_ARB_PRIORITY   0x700 /* Arbitration between DEB busses */
 
#define DEB1_URGENT   0x1000 /* DEB1 Urgent */
 
#define DEB2_URGENT   0x2000 /* DEB2 Urgent */
 
#define DEB3_URGENT   0x4000 /* DEB3 Urgent */
 
#define DEB1_ERROR   0x1 /* DEB1 Error */
 
#define DEB2_ERROR   0x2 /* DEB2 Error */
 
#define DEB3_ERROR   0x4 /* DEB3 Error */
 
#define CORE_ERROR   0x8 /* Core error */
 
#define DEB_MERROR   0x10 /* DEB1 Error (2nd) */
 
#define DEB2_MERROR   0x20 /* DEB2 Error (2nd) */
 
#define DEB3_MERROR   0x40 /* DEB3 Error (2nd) */
 
#define CORE_MERROR   0x80 /* Core Error (2nd) */
 
#define DDRSRESET   0x1 /* DDR soft reset */
 
#define PFTCHSRESET   0x4 /* DDR prefetch reset */
 
#define SRREQ   0x8 /* Self-refresh request */
 
#define SRACK   0x10 /* Self-refresh acknowledge */
 
#define MDDRENABLE   0x20 /* Mobile DDR enable */
 
#define B0WCENABLE   0x1 /* Bank 0 write count enable */
 
#define B1WCENABLE   0x2 /* Bank 1 write count enable */
 
#define B2WCENABLE   0x4 /* Bank 2 write count enable */
 
#define B3WCENABLE   0x8 /* Bank 3 write count enable */
 
#define B4WCENABLE   0x10 /* Bank 4 write count enable */
 
#define B5WCENABLE   0x20 /* Bank 5 write count enable */
 
#define B6WCENABLE   0x40 /* Bank 6 write count enable */
 
#define B7WCENABLE   0x80 /* Bank 7 write count enable */
 
#define B0RCENABLE   0x100 /* Bank 0 read count enable */
 
#define B1RCENABLE   0x200 /* Bank 1 read count enable */
 
#define B2RCENABLE   0x400 /* Bank 2 read count enable */
 
#define B3RCENABLE   0x800 /* Bank 3 read count enable */
 
#define B4RCENABLE   0x1000 /* Bank 4 read count enable */
 
#define B5RCENABLE   0x2000 /* Bank 5 read count enable */
 
#define B6RCENABLE   0x4000 /* Bank 6 read count enable */
 
#define B7RCENABLE   0x8000 /* Bank 7 read count enable */
 
#define ROWACTCENABLE   0x10000 /* DDR Row activate count enable */
 
#define RWTCENABLE   0x20000 /* DDR R/W Turn around count enable */
 
#define ARCENABLE   0x40000 /* DDR Auto-refresh count enable */
 
#define GC0ENABLE   0x100000 /* DDR Grant count 0 enable */
 
#define GC1ENABLE   0x200000 /* DDR Grant count 1 enable */
 
#define GC2ENABLE   0x400000 /* DDR Grant count 2 enable */
 
#define GC3ENABLE   0x800000 /* DDR Grant count 3 enable */
 
#define GCCONTROL   0x3000000 /* DDR Grant Count Control */
 
#define CB0WCOUNT   0x1 /* Clear write count 0 */
 
#define CB1WCOUNT   0x2 /* Clear write count 1 */
 
#define CB2WCOUNT   0x4 /* Clear write count 2 */
 
#define CB3WCOUNT   0x8 /* Clear write count 3 */
 
#define CB4WCOUNT   0x10 /* Clear write count 4 */
 
#define CB5WCOUNT   0x20 /* Clear write count 5 */
 
#define CB6WCOUNT   0x40 /* Clear write count 6 */
 
#define CB7WCOUNT   0x80 /* Clear write count 7 */
 
#define CBRCOUNT   0x100 /* Clear read count 0 */
 
#define CB1RCOUNT   0x200 /* Clear read count 1 */
 
#define CB2RCOUNT   0x400 /* Clear read count 2 */
 
#define CB3RCOUNT   0x800 /* Clear read count 3 */
 
#define CB4RCOUNT   0x1000 /* Clear read count 4 */
 
#define CB5RCOUNT   0x2000 /* Clear read count 5 */
 
#define CB6RCOUNT   0x4000 /* Clear read count 6 */
 
#define CB7RCOUNT   0x8000 /* Clear read count 7 */
 
#define CRACOUNT   0x10000 /* Clear row activation count */
 
#define CRWTACOUNT   0x20000 /* Clear R/W turn-around count */
 
#define CARCOUNT   0x40000 /* Clear auto-refresh count */
 
#define CG0COUNT   0x100000 /* Clear grant count 0 */
 
#define CG1COUNT   0x200000 /* Clear grant count 1 */
 
#define CG2COUNT   0x400000 /* Clear grant count 2 */
 
#define CG3COUNT   0x800000 /* Clear grant count 3 */
 
#define Px0   0x1 /* GPIO 0 */
 
#define Px1   0x2 /* GPIO 1 */
 
#define Px2   0x4 /* GPIO 2 */
 
#define Px3   0x8 /* GPIO 3 */
 
#define Px4   0x10 /* GPIO 4 */
 
#define Px5   0x20 /* GPIO 5 */
 
#define Px6   0x40 /* GPIO 6 */
 
#define Px7   0x80 /* GPIO 7 */
 
#define Px8   0x100 /* GPIO 8 */
 
#define Px9   0x200 /* GPIO 9 */
 
#define Px10   0x400 /* GPIO 10 */
 
#define Px11   0x800 /* GPIO 11 */
 
#define Px12   0x1000 /* GPIO 12 */
 
#define Px13   0x2000 /* GPIO 13 */
 
#define Px14   0x4000 /* GPIO 14 */
 
#define Px15   0x8000 /* GPIO 15 */
 
#define PxM0   0x3 /* GPIO Mux 0 */
 
#define PxM1   0xc /* GPIO Mux 1 */
 
#define PxM2   0x30 /* GPIO Mux 2 */
 
#define PxM3   0xc0 /* GPIO Mux 3 */
 
#define PxM4   0x300 /* GPIO Mux 4 */
 
#define PxM5   0xc00 /* GPIO Mux 5 */
 
#define PxM6   0x3000 /* GPIO Mux 6 */
 
#define PxM7   0xc000 /* GPIO Mux 7 */
 
#define PxM8   0x30000 /* GPIO Mux 8 */
 
#define PxM9   0xc0000 /* GPIO Mux 9 */
 
#define PxM10   0x300000 /* GPIO Mux 10 */
 
#define PxM11   0xc00000 /* GPIO Mux 11 */
 
#define PxM12   0x3000000 /* GPIO Mux 12 */
 
#define PxM13   0xc000000 /* GPIO Mux 13 */
 
#define PxM14   0x30000000 /* GPIO Mux 14 */
 
#define PxM15   0xc0000000 /* GPIO Mux 15 */
 
#define IB0   0x1 /* Interrupt Bit 0 */
 
#define IB1   0x2 /* Interrupt Bit 1 */
 
#define IB2   0x4 /* Interrupt Bit 2 */
 
#define IB3   0x8 /* Interrupt Bit 3 */
 
#define IB4   0x10 /* Interrupt Bit 4 */
 
#define IB5   0x20 /* Interrupt Bit 5 */
 
#define IB6   0x40 /* Interrupt Bit 6 */
 
#define IB7   0x80 /* Interrupt Bit 7 */
 
#define IB8   0x100 /* Interrupt Bit 8 */
 
#define IB9   0x200 /* Interrupt Bit 9 */
 
#define IB10   0x400 /* Interrupt Bit 10 */
 
#define IB11   0x800 /* Interrupt Bit 11 */
 
#define IB12   0x1000 /* Interrupt Bit 12 */
 
#define IB13   0x2000 /* Interrupt Bit 13 */
 
#define IB14   0x4000 /* Interrupt Bit 14 */
 
#define IB15   0x8000 /* Interrupt Bit 15 */
 
#define TMODE   0x3 /* Timer Mode */
 
#define PULSE_HI   0x4 /* Pulse Polarity */
 
#define PERIOD_CNT   0x8 /* Period Count */
 
#define IRQ_ENA   0x10 /* Interrupt Request Enable */
 
#define TIN_SEL   0x20 /* Timer Input Select */
 
#define OUT_DIS   0x40 /* Output Pad Disable */
 
#define CLK_SEL   0x80 /* Timer Clock Select */
 
#define TOGGLE_HI   0x100 /* Toggle Mode */
 
#define EMU_RUN   0x200 /* Emulation Behavior Select */
 
#define ERR_TYP   0xc000 /* Error Type */
 
#define TIMEN0   0x1 /* Timer 0 Enable */
 
#define TIMEN1   0x2 /* Timer 1 Enable */
 
#define TIMEN2   0x4 /* Timer 2 Enable */
 
#define TIMEN3   0x8 /* Timer 3 Enable */
 
#define TIMEN4   0x10 /* Timer 4 Enable */
 
#define TIMEN5   0x20 /* Timer 5 Enable */
 
#define TIMEN6   0x40 /* Timer 6 Enable */
 
#define TIMEN7   0x80 /* Timer 7 Enable */
 
#define TIMDIS0   0x1 /* Timer 0 Disable */
 
#define TIMDIS1   0x2 /* Timer 1 Disable */
 
#define TIMDIS2   0x4 /* Timer 2 Disable */
 
#define TIMDIS3   0x8 /* Timer 3 Disable */
 
#define TIMDIS4   0x10 /* Timer 4 Disable */
 
#define TIMDIS5   0x20 /* Timer 5 Disable */
 
#define TIMDIS6   0x40 /* Timer 6 Disable */
 
#define TIMDIS7   0x80 /* Timer 7 Disable */
 
#define TIMIL0   0x1 /* Timer 0 Interrupt */
 
#define TIMIL1   0x2 /* Timer 1 Interrupt */
 
#define TIMIL2   0x4 /* Timer 2 Interrupt */
 
#define TIMIL3   0x8 /* Timer 3 Interrupt */
 
#define TOVF_ERR0   0x10 /* Timer 0 Counter Overflow */
 
#define TOVF_ERR1   0x20 /* Timer 1 Counter Overflow */
 
#define TOVF_ERR2   0x40 /* Timer 2 Counter Overflow */
 
#define TOVF_ERR3   0x80 /* Timer 3 Counter Overflow */
 
#define TRUN0   0x1000 /* Timer 0 Slave Enable Status */
 
#define TRUN1   0x2000 /* Timer 1 Slave Enable Status */
 
#define TRUN2   0x4000 /* Timer 2 Slave Enable Status */
 
#define TRUN3   0x8000 /* Timer 3 Slave Enable Status */
 
#define TIMIL4   0x10000 /* Timer 4 Interrupt */
 
#define TIMIL5   0x20000 /* Timer 5 Interrupt */
 
#define TIMIL6   0x40000 /* Timer 6 Interrupt */
 
#define TIMIL7   0x80000 /* Timer 7 Interrupt */
 
#define TOVF_ERR4   0x100000 /* Timer 4 Counter Overflow */
 
#define TOVF_ERR5   0x200000 /* Timer 5 Counter Overflow */
 
#define TOVF_ERR6   0x400000 /* Timer 6 Counter Overflow */
 
#define TOVF_ERR7   0x800000 /* Timer 7 Counter Overflow */
 
#define TRUN4   0x10000000 /* Timer 4 Slave Enable Status */
 
#define TRUN5   0x20000000 /* Timer 5 Slave Enable Status */
 
#define TRUN6   0x40000000 /* Timer 6 Slave Enable Status */
 
#define TRUN7   0x80000000 /* Timer 7 Slave Enable Status */
 
#define EMUDABL   0x1 /* Emulation Disable. */
 
#define RSTDABL   0x2 /* Reset Disable */
 
#define L1IDABL   0x1c /* L1 Instruction Memory Disable. */
 
#define L1DADABL   0xe0 /* L1 Data Bank A Memory Disable. */
 
#define L1DBDABL   0x700 /* L1 Data Bank B Memory Disable. */
 
#define DMA0OVR   0x800 /* DMA0 Memory Access Override */
 
#define DMA1OVR   0x1000 /* DMA1 Memory Access Override */
 
#define EMUOVR   0x4000 /* Emulation Override */
 
#define OTPSEN   0x8000 /* OTP Secrets Enable. */
 
#define L2DABL   0x70000 /* L2 Memory Disable. */
 
#define SECURE0   0x1 /* SECURE 0 */
 
#define SECURE1   0x2 /* SECURE 1 */
 
#define SECURE2   0x4 /* SECURE 2 */
 
#define SECURE3   0x8 /* SECURE 3 */
 
#define SECMODE   0x3 /* Secured Mode Control State */
 
#define NMI   0x4 /* Non Maskable Interrupt */
 
#define AFVALID   0x8 /* Authentication Firmware Valid */
 
#define AFEXIT   0x10 /* Authentication Firmware Exit */
 
#define SECSTAT   0xe0 /* Secure Status */
 
#define SYSTEM_RESET   0x0007 /* Initiates A System Software Reset */
 
#define DOUBLE_FAULT   0x0008 /* Core Double Fault Causes Reset */
 
#define RESET_DOUBLE   0x2000 /* SW Reset Generated By Core Double-Fault */
 
#define RESET_WDOG   0x4000 /* SW Reset Generated By Watchdog Timer */
 
#define RESET_SOFTWARE   0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
 
#define CFIFO_ERR   0x1 /* Chroma FIFO Error */
 
#define YFIFO_ERR   0x2 /* Luma FIFO Error */
 
#define LTERR_OVR   0x4 /* Line Track Overflow */
 
#define LTERR_UNDR   0x8 /* Line Track Underflow */
 
#define FTERR_OVR   0x10 /* Frame Track Overflow */
 
#define FTERR_UNDR   0x20 /* Frame Track Underflow */
 
#define ERR_NCOR   0x40 /* Preamble Error Not Corrected */
 
#define DMA1URQ   0x80 /* DMA1 Urgent Request */
 
#define DMA0URQ   0x100 /* DMA0 Urgent Request */
 
#define ERR_DET   0x4000 /* Preamble Error Detected */
 
#define FLD   0x8000 /* Field */
 
#define EPPI_EN   0x1 /* Enable */
 
#define EPPI_DIR   0x2 /* Direction */
 
#define XFR_TYPE   0xc /* Operating Mode */
 
#define FS_CFG   0x30 /* Frame Sync Configuration */
 
#define FLD_SEL   0x40 /* Field Select/Trigger */
 
#define ITU_TYPE   0x80 /* ITU Interlaced or Progressive */
 
#define BLANKGEN   0x100 /* ITU Output Mode with Internal Blanking Generation */
 
#define ICLKGEN   0x200 /* Internal Clock Generation */
 
#define IFSGEN   0x400 /* Internal Frame Sync Generation */
 
#define POLC   0x1800 /* Frame Sync and Data Driving/Sampling Edges */
 
#define POLS   0x6000 /* Frame Sync Polarity */
 
#define DLENGTH   0x38000 /* Data Length */
 
#define SKIP_EN   0x40000 /* Skip Enable */
 
#define SKIP_EO   0x80000 /* Skip Even or Odd */
 
#define PACKEN   0x100000 /* Packing/Unpacking Enable */
 
#define SWAPEN   0x200000 /* Swap Enable */
 
#define SIGN_EXT   0x400000 /* Sign Extension or Zero-filled / Data Split Format */
 
#define SPLT_EVEN_ODD   0x800000 /* Split Even and Odd Data Samples */
 
#define SUBSPLT_ODD   0x1000000 /* Sub-split Odd Samples */
 
#define DMACFG   0x2000000 /* One or Two DMA Channels Mode */
 
#define RGB_FMT_EN   0x4000000 /* RGB Formatting Enable */
 
#define FIFO_RWM   0x18000000 /* FIFO Regular Watermarks */
 
#define FIFO_UWM   0x60000000 /* FIFO Urgent Watermarks */
 
#define DLEN_8   (0 << 15) /* 000 - 8 bits */
 
#define DLEN_10   (1 << 15) /* 001 - 10 bits */
 
#define DLEN_12   (2 << 15) /* 010 - 12 bits */
 
#define DLEN_14   (3 << 15) /* 011 - 14 bits */
 
#define DLEN_16   (4 << 15) /* 100 - 16 bits */
 
#define DLEN_18   (5 << 15) /* 101 - 18 bits */
 
#define DLEN_24   (6 << 15) /* 110 - 24 bits */
 
#define F1VB_BD   0xff /* Vertical Blanking before Field 1 Active Data */
 
#define F1VB_AD   0xff00 /* Vertical Blanking after Field 1 Active Data */
 
#define F2VB_BD   0xff0000 /* Vertical Blanking before Field 2 Active Data */
 
#define F2VB_AD   0xff000000 /* Vertical Blanking after Field 2 Active Data */
 
#define F1_ACT   0xffff /* Number of Lines of Active Data in Field 1 */
 
#define F2_ACT   0xffff0000 /* Number of Lines of Active Data in Field 2 */
 
#define LOW_ODD   0xff /* Lower Limit for Odd Bytes (Chroma) */
 
#define HIGH_ODD   0xff00 /* Upper Limit for Odd Bytes (Chroma) */
 
#define LOW_EVEN   0xff0000 /* Lower Limit for Even Bytes (Luma) */
 
#define HIGH_EVEN   0xff000000 /* Upper Limit for Even Bytes (Luma) */
 
#define BCODE_WAKEUP   0x0000 /* boot according to wake-up condition */
 
#define BCODE_FULLBOOT   0x0010 /* always perform full boot */
 
#define BCODE_QUICKBOOT   0x0020 /* always perform quick boot */
 
#define BCODE_NOBOOT   0x0030 /* always perform full boot */
 
#define PWM_OUT   0x0001
 
#define WDTH_CAP   0x0002
 
#define EXT_CLK   0x0003
 
#define PIQ0   0x00000001
 
#define PIQ1   0x00000002
 
#define PIQ2   0x00000004
 
#define PIQ3   0x00000008
 
#define PIQ4   0x00000010
 
#define PIQ5   0x00000020
 
#define PIQ6   0x00000040
 
#define PIQ7   0x00000080
 
#define PIQ8   0x00000100
 
#define PIQ9   0x00000200
 
#define PIQ10   0x00000400
 
#define PIQ11   0x00000800
 
#define PIQ12   0x00001000
 
#define PIQ13   0x00002000
 
#define PIQ14   0x00004000
 
#define PIQ15   0x00008000
 
#define PIQ16   0x00010000
 
#define PIQ17   0x00020000
 
#define PIQ18   0x00040000
 
#define PIQ19   0x00080000
 
#define PIQ20   0x00100000
 
#define PIQ21   0x00200000
 
#define PIQ22   0x00400000
 
#define PIQ23   0x00800000
 
#define PIQ24   0x01000000
 
#define PIQ25   0x02000000
 
#define PIQ26   0x04000000
 
#define PIQ27   0x08000000
 
#define PIQ28   0x10000000
 
#define PIQ29   0x20000000
 
#define PIQ30   0x40000000
 
#define PIQ31   0x80000000
 
#define MUX0   0x00000003
 
#define MUX0_0   0x00000000
 
#define MUX0_1   0x00000001
 
#define MUX0_2   0x00000002
 
#define MUX0_3   0x00000003
 
#define MUX1   0x0000000C
 
#define MUX1_0   0x00000000
 
#define MUX1_1   0x00000004
 
#define MUX1_2   0x00000008
 
#define MUX1_3   0x0000000C
 
#define MUX2   0x00000030
 
#define MUX2_0   0x00000000
 
#define MUX2_1   0x00000010
 
#define MUX2_2   0x00000020
 
#define MUX2_3   0x00000030
 
#define MUX3   0x000000C0
 
#define MUX3_0   0x00000000
 
#define MUX3_1   0x00000040
 
#define MUX3_2   0x00000080
 
#define MUX3_3   0x000000C0
 
#define MUX4   0x00000300
 
#define MUX4_0   0x00000000
 
#define MUX4_1   0x00000100
 
#define MUX4_2   0x00000200
 
#define MUX4_3   0x00000300
 
#define MUX5   0x00000C00
 
#define MUX5_0   0x00000000
 
#define MUX5_1   0x00000400
 
#define MUX5_2   0x00000800
 
#define MUX5_3   0x00000C00
 
#define MUX6   0x00003000
 
#define MUX6_0   0x00000000
 
#define MUX6_1   0x00001000
 
#define MUX6_2   0x00002000
 
#define MUX6_3   0x00003000
 
#define MUX7   0x0000C000
 
#define MUX7_0   0x00000000
 
#define MUX7_1   0x00004000
 
#define MUX7_2   0x00008000
 
#define MUX7_3   0x0000C000
 
#define MUX8   0x00030000
 
#define MUX8_0   0x00000000
 
#define MUX8_1   0x00010000
 
#define MUX8_2   0x00020000
 
#define MUX8_3   0x00030000
 
#define MUX9   0x000C0000
 
#define MUX9_0   0x00000000
 
#define MUX9_1   0x00040000
 
#define MUX9_2   0x00080000
 
#define MUX9_3   0x000C0000
 
#define MUX10   0x00300000
 
#define MUX10_0   0x00000000
 
#define MUX10_1   0x00100000
 
#define MUX10_2   0x00200000
 
#define MUX10_3   0x00300000
 
#define MUX11   0x00C00000
 
#define MUX11_0   0x00000000
 
#define MUX11_1   0x00400000
 
#define MUX11_2   0x00800000
 
#define MUX11_3   0x00C00000
 
#define MUX12   0x03000000
 
#define MUX12_0   0x00000000
 
#define MUX12_1   0x01000000
 
#define MUX12_2   0x02000000
 
#define MUX12_3   0x03000000
 
#define MUX13   0x0C000000
 
#define MUX13_0   0x00000000
 
#define MUX13_1   0x04000000
 
#define MUX13_2   0x08000000
 
#define MUX13_3   0x0C000000
 
#define MUX14   0x30000000
 
#define MUX14_0   0x00000000
 
#define MUX14_1   0x10000000
 
#define MUX14_2   0x20000000
 
#define MUX14_3   0x30000000
 
#define MUX15   0xC0000000
 
#define MUX15_0   0x00000000
 
#define MUX15_1   0x40000000
 
#define MUX15_2   0x80000000
 
#define MUX15_3   0xC0000000
 
#define MUX(b15, b14, b13, b12, b11, b10, b9, b8, b7, b6, b5, b4, b3, b2, b1, b0)
 
#define B0MAP   0x000000FF /* Byte 0 Lower Half Port Mapping */
 
#define B0MAP_PAL   0x00000000 /* Map Port A Low to Byte 0 */
 
#define B0MAP_PBL   0x00000001 /* Map Port B Low to Byte 0 */
 
#define B1MAP   0x0000FF00 /* Byte 1 Upper Half Port Mapping */
 
#define B1MAP_PAH   0x00000000 /* Map Port A High to Byte 1 */
 
#define B1MAP_PBH   0x00000100 /* Map Port B High to Byte 1 */
 
#define B2MAP   0x00FF0000 /* Byte 2 Lower Half Port Mapping */
 
#define B2MAP_PAL   0x00000000 /* Map Port A Low to Byte 2 */
 
#define B2MAP_PBL   0x00010000 /* Map Port B Low to Byte 2 */
 
#define B3MAP   0xFF000000 /* Byte 3 Upper Half Port Mapping */
 
#define B3MAP_PAH   0x00000000 /* Map Port A High to Byte 3 */
 
#define B3MAP_PBH   0x01000000 /* Map Port B High to Byte 3 */
 
#define B0MAP_PCL   0x00000000 /* Map Port C Low to Byte 0 */
 
#define B0MAP_PDL   0x00000001 /* Map Port D Low to Byte 0 */
 
#define B0MAP_PEL   0x00000002 /* Map Port E Low to Byte 0 */
 
#define B0MAP_PFL   0x00000003 /* Map Port F Low to Byte 0 */
 
#define B0MAP_PGL   0x00000004 /* Map Port G Low to Byte 0 */
 
#define B0MAP_PHL   0x00000005 /* Map Port H Low to Byte 0 */
 
#define B0MAP_PIL   0x00000006 /* Map Port I Low to Byte 0 */
 
#define B0MAP_PJL   0x00000007 /* Map Port J Low to Byte 0 */
 
#define B1MAP_PCH   0x00000000 /* Map Port C High to Byte 1 */
 
#define B1MAP_PDH   0x00000100 /* Map Port D High to Byte 1 */
 
#define B1MAP_PEH   0x00000200 /* Map Port E High to Byte 1 */
 
#define B1MAP_PFH   0x00000300 /* Map Port F High to Byte 1 */
 
#define B1MAP_PGH   0x00000400 /* Map Port G High to Byte 1 */
 
#define B1MAP_PHH   0x00000500 /* Map Port H High to Byte 1 */
 
#define B1MAP_PIH   0x00000600 /* Map Port I High to Byte 1 */
 
#define B1MAP_PJH   0x00000700 /* Map Port J High to Byte 1 */
 
#define B2MAP_PCL   0x00000000 /* Map Port C Low to Byte 2 */
 
#define B2MAP_PDL   0x00010000 /* Map Port D Low to Byte 2 */
 
#define B2MAP_PEL   0x00020000 /* Map Port E Low to Byte 2 */
 
#define B2MAP_PFL   0x00030000 /* Map Port F Low to Byte 2 */
 
#define B2MAP_PGL   0x00040000 /* Map Port G Low to Byte 2 */
 
#define B2MAP_PHL   0x00050000 /* Map Port H Low to Byte 2 */
 
#define B2MAP_PIL   0x00060000 /* Map Port I Low to Byte 2 */
 
#define B2MAP_PJL   0x00070000 /* Map Port J Low to Byte 2 */
 
#define B3MAP_PCH   0x00000000 /* Map Port C High to Byte 3 */
 
#define B3MAP_PDH   0x01000000 /* Map Port D High to Byte 3 */
 
#define B3MAP_PEH   0x02000000 /* Map Port E High to Byte 3 */
 
#define B3MAP_PFH   0x03000000 /* Map Port F High to Byte 3 */
 
#define B3MAP_PGH   0x04000000 /* Map Port G High to Byte 3 */
 
#define B3MAP_PHH   0x05000000 /* Map Port H High to Byte 3 */
 
#define B3MAP_PIH   0x06000000 /* Map Port I High to Byte 3 */
 
#define B3MAP_PJH   0x07000000 /* Map Port J High to Byte 3 */
 

Macro Definition Documentation

#define AFEXIT   0x10 /* Authentication Firmware Exit */

Definition at line 1987 of file defBF54x_base.h.

#define AFVALID   0x8 /* Authentication Firmware Valid */

Definition at line 1986 of file defBF54x_base.h.

#define AMBEN_ALL   0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */

Definition at line 1643 of file defBF54x_base.h.

#define AMBEN_B0   0x0002 /* Enable Async Memory Bank 0 only */

Definition at line 1640 of file defBF54x_base.h.

#define AMBEN_B0_B1   0x0004 /* Enable Async Memory Banks 0 & 1 only */

Definition at line 1641 of file defBF54x_base.h.

#define AMBEN_B0_B1_B2   0x0006 /* Enable Async Memory Banks 0, 1, and 2 */

Definition at line 1642 of file defBF54x_base.h.

#define AMBEN_NONE   0x0000 /* All Banks Disabled */

Definition at line 1639 of file defBF54x_base.h.

#define AMCKEN   0x0001 /* Enable CLKOUT */

Definition at line 1638 of file defBF54x_base.h.

#define AMSB0CTL   0x3 /* Async Memory Bank 0 select */

Definition at line 1682 of file defBF54x_base.h.

#define AMSB1CTL   0xc /* Async Memory Bank 1 select */

Definition at line 1683 of file defBF54x_base.h.

#define AMSB2CTL   0x30 /* Async Memory Bank 2 select */

Definition at line 1684 of file defBF54x_base.h.

#define AMSB3CTL   0xc0 /* Async Memory Bank 3 select */

Definition at line 1685 of file defBF54x_base.h.

#define ARBSTAT   0x1 /* Arbitration status */

Definition at line 1704 of file defBF54x_base.h.

#define ARCENABLE   0x40000 /* DDR Auto-refresh count enable */

Definition at line 1809 of file defBF54x_base.h.

#define ATAPI_ERR   0x20000000 /* ATAPI Error */

Definition at line 1577 of file defBF54x_base.h.

#define B0HT   0xc0 /* Bank 0 Hold time */

Definition at line 1652 of file defBF54x_base.h.

#define B0MAP   0x000000FF /* Byte 0 Lower Half Port Mapping */

Definition at line 2243 of file defBF54x_base.h.

#define B0MAP_PAL   0x00000000 /* Map Port A Low to Byte 0 */

Definition at line 2244 of file defBF54x_base.h.

#define B0MAP_PBL   0x00000001 /* Map Port B Low to Byte 0 */

Definition at line 2245 of file defBF54x_base.h.

#define B0MAP_PCL   0x00000000 /* Map Port C Low to Byte 0 */

Definition at line 2258 of file defBF54x_base.h.

#define B0MAP_PDL   0x00000001 /* Map Port D Low to Byte 0 */

Definition at line 2259 of file defBF54x_base.h.

#define B0MAP_PEL   0x00000002 /* Map Port E Low to Byte 0 */

Definition at line 2260 of file defBF54x_base.h.

#define B0MAP_PFL   0x00000003 /* Map Port F Low to Byte 0 */

Definition at line 2261 of file defBF54x_base.h.

#define B0MAP_PGL   0x00000004 /* Map Port G Low to Byte 0 */

Definition at line 2262 of file defBF54x_base.h.

#define B0MAP_PHL   0x00000005 /* Map Port H Low to Byte 0 */

Definition at line 2263 of file defBF54x_base.h.

#define B0MAP_PIL   0x00000006 /* Map Port I Low to Byte 0 */

Definition at line 2264 of file defBF54x_base.h.

#define B0MAP_PJL   0x00000007 /* Map Port J Low to Byte 0 */

Definition at line 2265 of file defBF54x_base.h.

#define B0MODE   0x3 /* Async Memory Bank 0 Access Mode */

Definition at line 1689 of file defBF54x_base.h.

#define B0RAT   0xf00 /* Bank 0 Read access time */

Definition at line 1653 of file defBF54x_base.h.

#define B0RCENABLE   0x100 /* Bank 0 read count enable */

Definition at line 1799 of file defBF54x_base.h.

#define B0RDYEN   0x1 /* Bank 0 ARDY Enable */

Definition at line 1648 of file defBF54x_base.h.

#define B0RDYPOL   0x2 /* Bank 0 ARDY Polarity */

Definition at line 1649 of file defBF54x_base.h.

#define B0ST   0x30 /* Bank 0 Setup time */

Definition at line 1651 of file defBF54x_base.h.

#define B0TT   0xc /* Bank 0 transition time */

Definition at line 1650 of file defBF54x_base.h.

#define B0WAT   0xf000 /* Bank 0 write access time */

Definition at line 1654 of file defBF54x_base.h.

#define B0WCENABLE   0x1 /* Bank 0 write count enable */

Definition at line 1791 of file defBF54x_base.h.

#define B1HT   0xc00000 /* Bank 1 Hold time */

Definition at line 1659 of file defBF54x_base.h.

#define B1MAP   0x0000FF00 /* Byte 1 Upper Half Port Mapping */

Definition at line 2246 of file defBF54x_base.h.

#define B1MAP_PAH   0x00000000 /* Map Port A High to Byte 1 */

Definition at line 2247 of file defBF54x_base.h.

#define B1MAP_PBH   0x00000100 /* Map Port B High to Byte 1 */

Definition at line 2248 of file defBF54x_base.h.

#define B1MAP_PCH   0x00000000 /* Map Port C High to Byte 1 */

Definition at line 2267 of file defBF54x_base.h.

#define B1MAP_PDH   0x00000100 /* Map Port D High to Byte 1 */

Definition at line 2268 of file defBF54x_base.h.

#define B1MAP_PEH   0x00000200 /* Map Port E High to Byte 1 */

Definition at line 2269 of file defBF54x_base.h.

#define B1MAP_PFH   0x00000300 /* Map Port F High to Byte 1 */

Definition at line 2270 of file defBF54x_base.h.

#define B1MAP_PGH   0x00000400 /* Map Port G High to Byte 1 */

Definition at line 2271 of file defBF54x_base.h.

#define B1MAP_PHH   0x00000500 /* Map Port H High to Byte 1 */

Definition at line 2272 of file defBF54x_base.h.

#define B1MAP_PIH   0x00000600 /* Map Port I High to Byte 1 */

Definition at line 2273 of file defBF54x_base.h.

#define B1MAP_PJH   0x00000700 /* Map Port J High to Byte 1 */

Definition at line 2274 of file defBF54x_base.h.

#define B1MODE   0xc /* Async Memory Bank 1 Access Mode */

Definition at line 1690 of file defBF54x_base.h.

#define B1RAT   0xf000000 /* Bank 1 Read access time */

Definition at line 1660 of file defBF54x_base.h.

#define B1RCENABLE   0x200 /* Bank 1 read count enable */

Definition at line 1800 of file defBF54x_base.h.

#define B1RDYEN   0x10000 /* Bank 1 ARDY Enable */

Definition at line 1655 of file defBF54x_base.h.

#define B1RDYPOL   0x20000 /* Bank 1 ARDY Polarity */

Definition at line 1656 of file defBF54x_base.h.

#define B1ST   0x300000 /* Bank 1 Setup time */

Definition at line 1658 of file defBF54x_base.h.

#define B1TT   0xc0000 /* Bank 1 transition time */

Definition at line 1657 of file defBF54x_base.h.

#define B1WAT   0xf0000000 /* Bank 1 write access time */

Definition at line 1661 of file defBF54x_base.h.

#define B1WCENABLE   0x2 /* Bank 1 write count enable */

Definition at line 1792 of file defBF54x_base.h.

#define B2HT   0xc0 /* Bank 2 Hold time */

Definition at line 1669 of file defBF54x_base.h.

#define B2MAP   0x00FF0000 /* Byte 2 Lower Half Port Mapping */

Definition at line 2249 of file defBF54x_base.h.

#define B2MAP_PAL   0x00000000 /* Map Port A Low to Byte 2 */

Definition at line 2250 of file defBF54x_base.h.

#define B2MAP_PBL   0x00010000 /* Map Port B Low to Byte 2 */

Definition at line 2251 of file defBF54x_base.h.

#define B2MAP_PCL   0x00000000 /* Map Port C Low to Byte 2 */

Definition at line 2276 of file defBF54x_base.h.

#define B2MAP_PDL   0x00010000 /* Map Port D Low to Byte 2 */

Definition at line 2277 of file defBF54x_base.h.

#define B2MAP_PEL   0x00020000 /* Map Port E Low to Byte 2 */

Definition at line 2278 of file defBF54x_base.h.

#define B2MAP_PFL   0x00030000 /* Map Port F Low to Byte 2 */

Definition at line 2279 of file defBF54x_base.h.

#define B2MAP_PGL   0x00040000 /* Map Port G Low to Byte 2 */

Definition at line 2280 of file defBF54x_base.h.

#define B2MAP_PHL   0x00050000 /* Map Port H Low to Byte 2 */

Definition at line 2281 of file defBF54x_base.h.

#define B2MAP_PIL   0x00060000 /* Map Port I Low to Byte 2 */

Definition at line 2282 of file defBF54x_base.h.

#define B2MAP_PJL   0x00070000 /* Map Port J Low to Byte 2 */

Definition at line 2283 of file defBF54x_base.h.

#define B2MODE   0x30 /* Async Memory Bank 2 Access Mode */

Definition at line 1691 of file defBF54x_base.h.

#define B2RAT   0xf00 /* Bank 2 Read access time */

Definition at line 1670 of file defBF54x_base.h.

#define B2RCENABLE   0x400 /* Bank 2 read count enable */

Definition at line 1801 of file defBF54x_base.h.

#define B2RDYEN   0x1 /* Bank 2 ARDY Enable */

Definition at line 1665 of file defBF54x_base.h.

#define B2RDYPOL   0x2 /* Bank 2 ARDY Polarity */

Definition at line 1666 of file defBF54x_base.h.

#define B2ST   0x30 /* Bank 2 Setup time */

Definition at line 1668 of file defBF54x_base.h.

#define B2TT   0xc /* Bank 2 transition time */

Definition at line 1667 of file defBF54x_base.h.

#define B2WAT   0xf000 /* Bank 2 write access time */

Definition at line 1671 of file defBF54x_base.h.

#define B2WCENABLE   0x4 /* Bank 2 write count enable */

Definition at line 1793 of file defBF54x_base.h.

#define B3HT   0xc00000 /* Bank 3 Hold time */

Definition at line 1676 of file defBF54x_base.h.

#define B3MAP   0xFF000000 /* Byte 3 Upper Half Port Mapping */

Definition at line 2252 of file defBF54x_base.h.

#define B3MAP_PAH   0x00000000 /* Map Port A High to Byte 3 */

Definition at line 2253 of file defBF54x_base.h.

#define B3MAP_PBH   0x01000000 /* Map Port B High to Byte 3 */

Definition at line 2254 of file defBF54x_base.h.

#define B3MAP_PCH   0x00000000 /* Map Port C High to Byte 3 */

Definition at line 2285 of file defBF54x_base.h.

#define B3MAP_PDH   0x01000000 /* Map Port D High to Byte 3 */

Definition at line 2286 of file defBF54x_base.h.

#define B3MAP_PEH   0x02000000 /* Map Port E High to Byte 3 */

Definition at line 2287 of file defBF54x_base.h.

#define B3MAP_PFH   0x03000000 /* Map Port F High to Byte 3 */

Definition at line 2288 of file defBF54x_base.h.

#define B3MAP_PGH   0x04000000 /* Map Port G High to Byte 3 */

Definition at line 2289 of file defBF54x_base.h.

#define B3MAP_PHH   0x05000000 /* Map Port H High to Byte 3 */

Definition at line 2290 of file defBF54x_base.h.

#define B3MAP_PIH   0x06000000 /* Map Port I High to Byte 3 */

Definition at line 2291 of file defBF54x_base.h.

#define B3MAP_PJH   0x07000000 /* Map Port J High to Byte 3 */

Definition at line 2292 of file defBF54x_base.h.

#define B3MODE   0xc0 /* Async Memory Bank 3 Access Mode */

Definition at line 1692 of file defBF54x_base.h.

#define B3RAT   0xf000000 /* Bank 3 Read access time */

Definition at line 1677 of file defBF54x_base.h.

#define B3RCENABLE   0x800 /* Bank 3 read count enable */

Definition at line 1802 of file defBF54x_base.h.

#define B3RDYEN   0x10000 /* Bank 3 ARDY Enable */

Definition at line 1672 of file defBF54x_base.h.

#define B3RDYPOL   0x20000 /* Bank 3 ARDY Polarity */

Definition at line 1673 of file defBF54x_base.h.

#define B3ST   0x300000 /* Bank 3 Setup time */

Definition at line 1675 of file defBF54x_base.h.

#define B3TT   0xc0000 /* Bank 3 transition time */

Definition at line 1674 of file defBF54x_base.h.

#define B3WAT   0xf0000000 /* Bank 3 write access time */

Definition at line 1678 of file defBF54x_base.h.

#define B3WCENABLE   0x8 /* Bank 3 write count enable */

Definition at line 1794 of file defBF54x_base.h.

#define B4RCENABLE   0x1000 /* Bank 4 read count enable */

Definition at line 1803 of file defBF54x_base.h.

#define B4WCENABLE   0x10 /* Bank 4 write count enable */

Definition at line 1795 of file defBF54x_base.h.

#define B5RCENABLE   0x2000 /* Bank 5 read count enable */

Definition at line 1804 of file defBF54x_base.h.

#define B5WCENABLE   0x20 /* Bank 5 write count enable */

Definition at line 1796 of file defBF54x_base.h.

#define B6RCENABLE   0x4000 /* Bank 6 read count enable */

Definition at line 1805 of file defBF54x_base.h.

#define B6WCENABLE   0x40 /* Bank 6 write count enable */

Definition at line 1797 of file defBF54x_base.h.

#define B7RCENABLE   0x8000 /* Bank 7 read count enable */

Definition at line 1806 of file defBF54x_base.h.

#define B7WCENABLE   0x80 /* Bank 7 write count enable */

Definition at line 1798 of file defBF54x_base.h.

#define BCLK   0x6 /* Burst clock frequency */

Definition at line 1697 of file defBF54x_base.h.

#define BCODE_FULLBOOT   0x0010 /* always perform full boot */

Definition at line 2073 of file defBF54x_base.h.

#define BCODE_NOBOOT   0x0030 /* always perform full boot */

Definition at line 2075 of file defBF54x_base.h.

#define BCODE_QUICKBOOT   0x0020 /* always perform quick boot */

Definition at line 2074 of file defBF54x_base.h.

#define BCODE_WAKEUP   0x0000 /* boot according to wake-up condition */

Definition at line 2072 of file defBF54x_base.h.

#define BGSTAT   0x2 /* Bus grant status */

Definition at line 1705 of file defBF54x_base.h.

#define BLANKGEN   0x100 /* ITU Output Mode with Internal Blanking Generation */

Definition at line 2019 of file defBF54x_base.h.

#define BURSTLENGTH   0x7 /* Burst length */

Definition at line 1747 of file defBF54x_base.h.

#define CAN0_AA1   0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */

Definition at line 1047 of file defBF54x_base.h.

#define CAN0_AA2   0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */

Definition at line 1063 of file defBF54x_base.h.

#define CAN0_AM00H   0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */

Definition at line 1094 of file defBF54x_base.h.

#define CAN0_AM00L   0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */

Definition at line 1093 of file defBF54x_base.h.

#define CAN0_AM01H   0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */

Definition at line 1096 of file defBF54x_base.h.

#define CAN0_AM01L   0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */

Definition at line 1095 of file defBF54x_base.h.

#define CAN0_AM02H   0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */

Definition at line 1098 of file defBF54x_base.h.

#define CAN0_AM02L   0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */

Definition at line 1097 of file defBF54x_base.h.

#define CAN0_AM03H   0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */

Definition at line 1100 of file defBF54x_base.h.

#define CAN0_AM03L   0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */

Definition at line 1099 of file defBF54x_base.h.

#define CAN0_AM04H   0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */

Definition at line 1102 of file defBF54x_base.h.

#define CAN0_AM04L   0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */

Definition at line 1101 of file defBF54x_base.h.

#define CAN0_AM05H   0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */

Definition at line 1104 of file defBF54x_base.h.

#define CAN0_AM05L   0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */

Definition at line 1103 of file defBF54x_base.h.

#define CAN0_AM06H   0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */

Definition at line 1106 of file defBF54x_base.h.

#define CAN0_AM06L   0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */

Definition at line 1105 of file defBF54x_base.h.

#define CAN0_AM07H   0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */

Definition at line 1108 of file defBF54x_base.h.

#define CAN0_AM07L   0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */

Definition at line 1107 of file defBF54x_base.h.

#define CAN0_AM08H   0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */

Definition at line 1110 of file defBF54x_base.h.

#define CAN0_AM08L   0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */

Definition at line 1109 of file defBF54x_base.h.

#define CAN0_AM09H   0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */

Definition at line 1112 of file defBF54x_base.h.

#define CAN0_AM09L   0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */

Definition at line 1111 of file defBF54x_base.h.

#define CAN0_AM10H   0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */

Definition at line 1114 of file defBF54x_base.h.

#define CAN0_AM10L   0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */

Definition at line 1113 of file defBF54x_base.h.

#define CAN0_AM11H   0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */

Definition at line 1116 of file defBF54x_base.h.

#define CAN0_AM11L   0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */

Definition at line 1115 of file defBF54x_base.h.

#define CAN0_AM12H   0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */

Definition at line 1118 of file defBF54x_base.h.

#define CAN0_AM12L   0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */

Definition at line 1117 of file defBF54x_base.h.

#define CAN0_AM13H   0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */

Definition at line 1120 of file defBF54x_base.h.

#define CAN0_AM13L   0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */

Definition at line 1119 of file defBF54x_base.h.

#define CAN0_AM14H   0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */

Definition at line 1122 of file defBF54x_base.h.

#define CAN0_AM14L   0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */

Definition at line 1121 of file defBF54x_base.h.

#define CAN0_AM15H   0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */

Definition at line 1124 of file defBF54x_base.h.

#define CAN0_AM15L   0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */

Definition at line 1123 of file defBF54x_base.h.

#define CAN0_AM16H   0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */

Definition at line 1129 of file defBF54x_base.h.

#define CAN0_AM16L   0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */

Definition at line 1128 of file defBF54x_base.h.

#define CAN0_AM17H   0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */

Definition at line 1131 of file defBF54x_base.h.

#define CAN0_AM17L   0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */

Definition at line 1130 of file defBF54x_base.h.

#define CAN0_AM18H   0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */

Definition at line 1133 of file defBF54x_base.h.

#define CAN0_AM18L   0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */

Definition at line 1132 of file defBF54x_base.h.

#define CAN0_AM19H   0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */

Definition at line 1135 of file defBF54x_base.h.

#define CAN0_AM19L   0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */

Definition at line 1134 of file defBF54x_base.h.

#define CAN0_AM20H   0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */

Definition at line 1137 of file defBF54x_base.h.

#define CAN0_AM20L   0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */

Definition at line 1136 of file defBF54x_base.h.

#define CAN0_AM21H   0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */

Definition at line 1139 of file defBF54x_base.h.

#define CAN0_AM21L   0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */

Definition at line 1138 of file defBF54x_base.h.

#define CAN0_AM22H   0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */

Definition at line 1141 of file defBF54x_base.h.

#define CAN0_AM22L   0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */

Definition at line 1140 of file defBF54x_base.h.

#define CAN0_AM23H   0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */

Definition at line 1143 of file defBF54x_base.h.

#define CAN0_AM23L   0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */

Definition at line 1142 of file defBF54x_base.h.

#define CAN0_AM24H   0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */

Definition at line 1145 of file defBF54x_base.h.

#define CAN0_AM24L   0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */

Definition at line 1144 of file defBF54x_base.h.

#define CAN0_AM25H   0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */

Definition at line 1147 of file defBF54x_base.h.

#define CAN0_AM25L   0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */

Definition at line 1146 of file defBF54x_base.h.

#define CAN0_AM26H   0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */

Definition at line 1149 of file defBF54x_base.h.

#define CAN0_AM26L   0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */

Definition at line 1148 of file defBF54x_base.h.

#define CAN0_AM27H   0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */

Definition at line 1151 of file defBF54x_base.h.

#define CAN0_AM27L   0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */

Definition at line 1150 of file defBF54x_base.h.

#define CAN0_AM28H   0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */

Definition at line 1153 of file defBF54x_base.h.

#define CAN0_AM28L   0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */

Definition at line 1152 of file defBF54x_base.h.

#define CAN0_AM29H   0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */

Definition at line 1155 of file defBF54x_base.h.

#define CAN0_AM29L   0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */

Definition at line 1154 of file defBF54x_base.h.

#define CAN0_AM30H   0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */

Definition at line 1157 of file defBF54x_base.h.

#define CAN0_AM30L   0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */

Definition at line 1156 of file defBF54x_base.h.

#define CAN0_AM31H   0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */

Definition at line 1159 of file defBF54x_base.h.

#define CAN0_AM31L   0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */

Definition at line 1158 of file defBF54x_base.h.

#define CAN0_CEC   0xffc02a90 /* CAN Controller 0 Error Counter Register */

Definition at line 1078 of file defBF54x_base.h.

#define CAN0_CLOCK   0xffc02a80 /* CAN Controller 0 Clock Register */

Definition at line 1074 of file defBF54x_base.h.

#define CAN0_CONTROL   0xffc02aa0 /* CAN Controller 0 Master Control Register */

Definition at line 1082 of file defBF54x_base.h.

#define CAN0_DEBUG   0xffc02a88 /* CAN Controller 0 Debug Register */

Definition at line 1076 of file defBF54x_base.h.

#define CAN0_ERR   0x1 /* CAN0 Error */

Definition at line 1548 of file defBF54x_base.h.

#define CAN0_ESR   0xffc02ab4 /* CAN Controller 0 Error Status Register */

Definition at line 1086 of file defBF54x_base.h.

#define CAN0_EWR   0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */

Definition at line 1085 of file defBF54x_base.h.

#define CAN0_GIF   0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */

Definition at line 1081 of file defBF54x_base.h.

#define CAN0_GIM   0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */

Definition at line 1080 of file defBF54x_base.h.

#define CAN0_GIS   0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */

Definition at line 1079 of file defBF54x_base.h.

#define CAN0_INTR   0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */

Definition at line 1083 of file defBF54x_base.h.

#define CAN0_MB00_DATA0   0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */

Definition at line 1163 of file defBF54x_base.h.

#define CAN0_MB00_DATA1   0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */

Definition at line 1164 of file defBF54x_base.h.

#define CAN0_MB00_DATA2   0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */

Definition at line 1165 of file defBF54x_base.h.

#define CAN0_MB00_DATA3   0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */

Definition at line 1166 of file defBF54x_base.h.

#define CAN0_MB00_ID0   0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */

Definition at line 1169 of file defBF54x_base.h.

#define CAN0_MB00_ID1   0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */

Definition at line 1170 of file defBF54x_base.h.

#define CAN0_MB00_LENGTH   0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */

Definition at line 1167 of file defBF54x_base.h.

#define CAN0_MB00_TIMESTAMP   0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */

Definition at line 1168 of file defBF54x_base.h.

#define CAN0_MB01_DATA0   0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */

Definition at line 1171 of file defBF54x_base.h.

#define CAN0_MB01_DATA1   0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */

Definition at line 1172 of file defBF54x_base.h.

#define CAN0_MB01_DATA2   0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */

Definition at line 1173 of file defBF54x_base.h.

#define CAN0_MB01_DATA3   0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */

Definition at line 1174 of file defBF54x_base.h.

#define CAN0_MB01_ID0   0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */

Definition at line 1177 of file defBF54x_base.h.

#define CAN0_MB01_ID1   0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */

Definition at line 1178 of file defBF54x_base.h.

#define CAN0_MB01_LENGTH   0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */

Definition at line 1175 of file defBF54x_base.h.

#define CAN0_MB01_TIMESTAMP   0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */

Definition at line 1176 of file defBF54x_base.h.

#define CAN0_MB02_DATA0   0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */

Definition at line 1179 of file defBF54x_base.h.

#define CAN0_MB02_DATA1   0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */

Definition at line 1180 of file defBF54x_base.h.

#define CAN0_MB02_DATA2   0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */

Definition at line 1181 of file defBF54x_base.h.

#define CAN0_MB02_DATA3   0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */

Definition at line 1182 of file defBF54x_base.h.

#define CAN0_MB02_ID0   0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */

Definition at line 1185 of file defBF54x_base.h.

#define CAN0_MB02_ID1   0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */

Definition at line 1186 of file defBF54x_base.h.

#define CAN0_MB02_LENGTH   0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */

Definition at line 1183 of file defBF54x_base.h.

#define CAN0_MB02_TIMESTAMP   0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */

Definition at line 1184 of file defBF54x_base.h.

#define CAN0_MB03_DATA0   0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */

Definition at line 1187 of file defBF54x_base.h.

#define CAN0_MB03_DATA1   0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */

Definition at line 1188 of file defBF54x_base.h.

#define CAN0_MB03_DATA2   0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */

Definition at line 1189 of file defBF54x_base.h.

#define CAN0_MB03_DATA3   0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */

Definition at line 1190 of file defBF54x_base.h.

#define CAN0_MB03_ID0   0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */

Definition at line 1193 of file defBF54x_base.h.

#define CAN0_MB03_ID1   0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */

Definition at line 1194 of file defBF54x_base.h.

#define CAN0_MB03_LENGTH   0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */

Definition at line 1191 of file defBF54x_base.h.

#define CAN0_MB03_TIMESTAMP   0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */

Definition at line 1192 of file defBF54x_base.h.

#define CAN0_MB04_DATA0   0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */

Definition at line 1195 of file defBF54x_base.h.

#define CAN0_MB04_DATA1   0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */

Definition at line 1196 of file defBF54x_base.h.

#define CAN0_MB04_DATA2   0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */

Definition at line 1197 of file defBF54x_base.h.

#define CAN0_MB04_DATA3   0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */

Definition at line 1198 of file defBF54x_base.h.

#define CAN0_MB04_ID0   0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */

Definition at line 1201 of file defBF54x_base.h.

#define CAN0_MB04_ID1   0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */

Definition at line 1202 of file defBF54x_base.h.

#define CAN0_MB04_LENGTH   0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */

Definition at line 1199 of file defBF54x_base.h.

#define CAN0_MB04_TIMESTAMP   0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */

Definition at line 1200 of file defBF54x_base.h.

#define CAN0_MB05_DATA0   0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */

Definition at line 1203 of file defBF54x_base.h.

#define CAN0_MB05_DATA1   0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */

Definition at line 1204 of file defBF54x_base.h.

#define CAN0_MB05_DATA2   0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */

Definition at line 1205 of file defBF54x_base.h.

#define CAN0_MB05_DATA3   0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */

Definition at line 1206 of file defBF54x_base.h.

#define CAN0_MB05_ID0   0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */

Definition at line 1209 of file defBF54x_base.h.

#define CAN0_MB05_ID1   0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */

Definition at line 1210 of file defBF54x_base.h.

#define CAN0_MB05_LENGTH   0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */

Definition at line 1207 of file defBF54x_base.h.

#define CAN0_MB05_TIMESTAMP   0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */

Definition at line 1208 of file defBF54x_base.h.

#define CAN0_MB06_DATA0   0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */

Definition at line 1211 of file defBF54x_base.h.

#define CAN0_MB06_DATA1   0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */

Definition at line 1212 of file defBF54x_base.h.

#define CAN0_MB06_DATA2   0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */

Definition at line 1213 of file defBF54x_base.h.

#define CAN0_MB06_DATA3   0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */

Definition at line 1214 of file defBF54x_base.h.

#define CAN0_MB06_ID0   0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */

Definition at line 1217 of file defBF54x_base.h.

#define CAN0_MB06_ID1   0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */

Definition at line 1218 of file defBF54x_base.h.

#define CAN0_MB06_LENGTH   0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */

Definition at line 1215 of file defBF54x_base.h.

#define CAN0_MB06_TIMESTAMP   0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */

Definition at line 1216 of file defBF54x_base.h.

#define CAN0_MB07_DATA0   0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */

Definition at line 1219 of file defBF54x_base.h.

#define CAN0_MB07_DATA1   0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */

Definition at line 1220 of file defBF54x_base.h.

#define CAN0_MB07_DATA2   0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */

Definition at line 1221 of file defBF54x_base.h.

#define CAN0_MB07_DATA3   0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */

Definition at line 1222 of file defBF54x_base.h.

#define CAN0_MB07_ID0   0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */

Definition at line 1225 of file defBF54x_base.h.

#define CAN0_MB07_ID1   0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */

Definition at line 1226 of file defBF54x_base.h.

#define CAN0_MB07_LENGTH   0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */

Definition at line 1223 of file defBF54x_base.h.

#define CAN0_MB07_TIMESTAMP   0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */

Definition at line 1224 of file defBF54x_base.h.

#define CAN0_MB08_DATA0   0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */

Definition at line 1227 of file defBF54x_base.h.

#define CAN0_MB08_DATA1   0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */

Definition at line 1228 of file defBF54x_base.h.

#define CAN0_MB08_DATA2   0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */

Definition at line 1229 of file defBF54x_base.h.

#define CAN0_MB08_DATA3   0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */

Definition at line 1230 of file defBF54x_base.h.

#define CAN0_MB08_ID0   0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */

Definition at line 1233 of file defBF54x_base.h.

#define CAN0_MB08_ID1   0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */

Definition at line 1234 of file defBF54x_base.h.

#define CAN0_MB08_LENGTH   0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */

Definition at line 1231 of file defBF54x_base.h.

#define CAN0_MB08_TIMESTAMP   0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */

Definition at line 1232 of file defBF54x_base.h.

#define CAN0_MB09_DATA0   0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */

Definition at line 1235 of file defBF54x_base.h.

#define CAN0_MB09_DATA1   0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */

Definition at line 1236 of file defBF54x_base.h.

#define CAN0_MB09_DATA2   0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */

Definition at line 1237 of file defBF54x_base.h.

#define CAN0_MB09_DATA3   0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */

Definition at line 1238 of file defBF54x_base.h.

#define CAN0_MB09_ID0   0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */

Definition at line 1241 of file defBF54x_base.h.

#define CAN0_MB09_ID1   0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */

Definition at line 1242 of file defBF54x_base.h.

#define CAN0_MB09_LENGTH   0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */

Definition at line 1239 of file defBF54x_base.h.

#define CAN0_MB09_TIMESTAMP   0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */

Definition at line 1240 of file defBF54x_base.h.

#define CAN0_MB10_DATA0   0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */

Definition at line 1243 of file defBF54x_base.h.

#define CAN0_MB10_DATA1   0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */

Definition at line 1244 of file defBF54x_base.h.

#define CAN0_MB10_DATA2   0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */

Definition at line 1245 of file defBF54x_base.h.

#define CAN0_MB10_DATA3   0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */

Definition at line 1246 of file defBF54x_base.h.

#define CAN0_MB10_ID0   0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */

Definition at line 1249 of file defBF54x_base.h.

#define CAN0_MB10_ID1   0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */

Definition at line 1250 of file defBF54x_base.h.

#define CAN0_MB10_LENGTH   0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */

Definition at line 1247 of file defBF54x_base.h.

#define CAN0_MB10_TIMESTAMP   0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */

Definition at line 1248 of file defBF54x_base.h.

#define CAN0_MB11_DATA0   0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */

Definition at line 1251 of file defBF54x_base.h.

#define CAN0_MB11_DATA1   0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */

Definition at line 1252 of file defBF54x_base.h.

#define CAN0_MB11_DATA2   0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */

Definition at line 1253 of file defBF54x_base.h.

#define CAN0_MB11_DATA3   0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */

Definition at line 1254 of file defBF54x_base.h.

#define CAN0_MB11_ID0   0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */

Definition at line 1257 of file defBF54x_base.h.

#define CAN0_MB11_ID1   0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */

Definition at line 1258 of file defBF54x_base.h.

#define CAN0_MB11_LENGTH   0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */

Definition at line 1255 of file defBF54x_base.h.

#define CAN0_MB11_TIMESTAMP   0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */

Definition at line 1256 of file defBF54x_base.h.

#define CAN0_MB12_DATA0   0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */

Definition at line 1259 of file defBF54x_base.h.

#define CAN0_MB12_DATA1   0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */

Definition at line 1260 of file defBF54x_base.h.

#define CAN0_MB12_DATA2   0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */

Definition at line 1261 of file defBF54x_base.h.

#define CAN0_MB12_DATA3   0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */

Definition at line 1262 of file defBF54x_base.h.

#define CAN0_MB12_ID0   0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */

Definition at line 1265 of file defBF54x_base.h.

#define CAN0_MB12_ID1   0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */

Definition at line 1266 of file defBF54x_base.h.

#define CAN0_MB12_LENGTH   0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */

Definition at line 1263 of file defBF54x_base.h.

#define CAN0_MB12_TIMESTAMP   0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */

Definition at line 1264 of file defBF54x_base.h.

#define CAN0_MB13_DATA0   0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */

Definition at line 1267 of file defBF54x_base.h.

#define CAN0_MB13_DATA1   0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */

Definition at line 1268 of file defBF54x_base.h.

#define CAN0_MB13_DATA2   0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */

Definition at line 1269 of file defBF54x_base.h.

#define CAN0_MB13_DATA3   0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */

Definition at line 1270 of file defBF54x_base.h.

#define CAN0_MB13_ID0   0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */

Definition at line 1273 of file defBF54x_base.h.

#define CAN0_MB13_ID1   0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */

Definition at line 1274 of file defBF54x_base.h.

#define CAN0_MB13_LENGTH   0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */

Definition at line 1271 of file defBF54x_base.h.

#define CAN0_MB13_TIMESTAMP   0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */

Definition at line 1272 of file defBF54x_base.h.

#define CAN0_MB14_DATA0   0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */

Definition at line 1275 of file defBF54x_base.h.

#define CAN0_MB14_DATA1   0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */

Definition at line 1276 of file defBF54x_base.h.

#define CAN0_MB14_DATA2   0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */

Definition at line 1277 of file defBF54x_base.h.

#define CAN0_MB14_DATA3   0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */

Definition at line 1278 of file defBF54x_base.h.

#define CAN0_MB14_ID0   0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */

Definition at line 1281 of file defBF54x_base.h.

#define CAN0_MB14_ID1   0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */

Definition at line 1282 of file defBF54x_base.h.

#define CAN0_MB14_LENGTH   0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */

Definition at line 1279 of file defBF54x_base.h.

#define CAN0_MB14_TIMESTAMP   0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */

Definition at line 1280 of file defBF54x_base.h.

#define CAN0_MB15_DATA0   0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */

Definition at line 1283 of file defBF54x_base.h.

#define CAN0_MB15_DATA1   0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */

Definition at line 1284 of file defBF54x_base.h.

#define CAN0_MB15_DATA2   0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */

Definition at line 1285 of file defBF54x_base.h.

#define CAN0_MB15_DATA3   0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */

Definition at line 1286 of file defBF54x_base.h.

#define CAN0_MB15_ID0   0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */

Definition at line 1289 of file defBF54x_base.h.

#define CAN0_MB15_ID1   0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */

Definition at line 1290 of file defBF54x_base.h.

#define CAN0_MB15_LENGTH   0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */

Definition at line 1287 of file defBF54x_base.h.

#define CAN0_MB15_TIMESTAMP   0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */

Definition at line 1288 of file defBF54x_base.h.

#define CAN0_MB16_DATA0   0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */

Definition at line 1294 of file defBF54x_base.h.

#define CAN0_MB16_DATA1   0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */

Definition at line 1295 of file defBF54x_base.h.

#define CAN0_MB16_DATA2   0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */

Definition at line 1296 of file defBF54x_base.h.

#define CAN0_MB16_DATA3   0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */

Definition at line 1297 of file defBF54x_base.h.

#define CAN0_MB16_ID0   0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */

Definition at line 1300 of file defBF54x_base.h.

#define CAN0_MB16_ID1   0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */

Definition at line 1301 of file defBF54x_base.h.

#define CAN0_MB16_LENGTH   0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */

Definition at line 1298 of file defBF54x_base.h.

#define CAN0_MB16_TIMESTAMP   0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */

Definition at line 1299 of file defBF54x_base.h.

#define CAN0_MB17_DATA0   0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */

Definition at line 1302 of file defBF54x_base.h.

#define CAN0_MB17_DATA1   0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */

Definition at line 1303 of file defBF54x_base.h.

#define CAN0_MB17_DATA2   0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */

Definition at line 1304 of file defBF54x_base.h.

#define CAN0_MB17_DATA3   0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */

Definition at line 1305 of file defBF54x_base.h.

#define CAN0_MB17_ID0   0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */

Definition at line 1308 of file defBF54x_base.h.

#define CAN0_MB17_ID1   0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */

Definition at line 1309 of file defBF54x_base.h.

#define CAN0_MB17_LENGTH   0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */

Definition at line 1306 of file defBF54x_base.h.

#define CAN0_MB17_TIMESTAMP   0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */

Definition at line 1307 of file defBF54x_base.h.

#define CAN0_MB18_DATA0   0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */

Definition at line 1310 of file defBF54x_base.h.

#define CAN0_MB18_DATA1   0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */

Definition at line 1311 of file defBF54x_base.h.

#define CAN0_MB18_DATA2   0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */

Definition at line 1312 of file defBF54x_base.h.

#define CAN0_MB18_DATA3   0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */

Definition at line 1313 of file defBF54x_base.h.

#define CAN0_MB18_ID0   0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */

Definition at line 1316 of file defBF54x_base.h.

#define CAN0_MB18_ID1   0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */

Definition at line 1317 of file defBF54x_base.h.

#define CAN0_MB18_LENGTH   0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */

Definition at line 1314 of file defBF54x_base.h.

#define CAN0_MB18_TIMESTAMP   0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */

Definition at line 1315 of file defBF54x_base.h.

#define CAN0_MB19_DATA0   0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */

Definition at line 1318 of file defBF54x_base.h.

#define CAN0_MB19_DATA1   0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */

Definition at line 1319 of file defBF54x_base.h.

#define CAN0_MB19_DATA2   0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */

Definition at line 1320 of file defBF54x_base.h.

#define CAN0_MB19_DATA3   0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */

Definition at line 1321 of file defBF54x_base.h.

#define CAN0_MB19_ID0   0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */

Definition at line 1324 of file defBF54x_base.h.

#define CAN0_MB19_ID1   0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */

Definition at line 1325 of file defBF54x_base.h.

#define CAN0_MB19_LENGTH   0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */

Definition at line 1322 of file defBF54x_base.h.

#define CAN0_MB19_TIMESTAMP   0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */

Definition at line 1323 of file defBF54x_base.h.

#define CAN0_MB20_DATA0   0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */

Definition at line 1326 of file defBF54x_base.h.

#define CAN0_MB20_DATA1   0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */

Definition at line 1327 of file defBF54x_base.h.

#define CAN0_MB20_DATA2   0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */

Definition at line 1328 of file defBF54x_base.h.

#define CAN0_MB20_DATA3   0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */

Definition at line 1329 of file defBF54x_base.h.

#define CAN0_MB20_ID0   0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */

Definition at line 1332 of file defBF54x_base.h.

#define CAN0_MB20_ID1   0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */

Definition at line 1333 of file defBF54x_base.h.

#define CAN0_MB20_LENGTH   0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */

Definition at line 1330 of file defBF54x_base.h.

#define CAN0_MB20_TIMESTAMP   0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */

Definition at line 1331 of file defBF54x_base.h.

#define CAN0_MB21_DATA0   0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */

Definition at line 1334 of file defBF54x_base.h.

#define CAN0_MB21_DATA1   0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */

Definition at line 1335 of file defBF54x_base.h.

#define CAN0_MB21_DATA2   0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */

Definition at line 1336 of file defBF54x_base.h.

#define CAN0_MB21_DATA3   0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */

Definition at line 1337 of file defBF54x_base.h.

#define CAN0_MB21_ID0   0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */

Definition at line 1340 of file defBF54x_base.h.

#define CAN0_MB21_ID1   0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */

Definition at line 1341 of file defBF54x_base.h.

#define CAN0_MB21_LENGTH   0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */

Definition at line 1338 of file defBF54x_base.h.

#define CAN0_MB21_TIMESTAMP   0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */

Definition at line 1339 of file defBF54x_base.h.

#define CAN0_MB22_DATA0   0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */

Definition at line 1342 of file defBF54x_base.h.

#define CAN0_MB22_DATA1   0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */

Definition at line 1343 of file defBF54x_base.h.

#define CAN0_MB22_DATA2   0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */

Definition at line 1344 of file defBF54x_base.h.

#define CAN0_MB22_DATA3   0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */

Definition at line 1345 of file defBF54x_base.h.

#define CAN0_MB22_ID0   0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */

Definition at line 1348 of file defBF54x_base.h.

#define CAN0_MB22_ID1   0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */

Definition at line 1349 of file defBF54x_base.h.

#define CAN0_MB22_LENGTH   0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */

Definition at line 1346 of file defBF54x_base.h.

#define CAN0_MB22_TIMESTAMP   0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */

Definition at line 1347 of file defBF54x_base.h.

#define CAN0_MB23_DATA0   0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */

Definition at line 1350 of file defBF54x_base.h.

#define CAN0_MB23_DATA1   0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */

Definition at line 1351 of file defBF54x_base.h.

#define CAN0_MB23_DATA2   0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */

Definition at line 1352 of file defBF54x_base.h.

#define CAN0_MB23_DATA3   0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */

Definition at line 1353 of file defBF54x_base.h.

#define CAN0_MB23_ID0   0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */

Definition at line 1356 of file defBF54x_base.h.

#define CAN0_MB23_ID1   0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */

Definition at line 1357 of file defBF54x_base.h.

#define CAN0_MB23_LENGTH   0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */

Definition at line 1354 of file defBF54x_base.h.

#define CAN0_MB23_TIMESTAMP   0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */

Definition at line 1355 of file defBF54x_base.h.

#define CAN0_MB24_DATA0   0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */

Definition at line 1358 of file defBF54x_base.h.

#define CAN0_MB24_DATA1   0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */

Definition at line 1359 of file defBF54x_base.h.

#define CAN0_MB24_DATA2   0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */

Definition at line 1360 of file defBF54x_base.h.

#define CAN0_MB24_DATA3   0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */

Definition at line 1361 of file defBF54x_base.h.

#define CAN0_MB24_ID0   0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */

Definition at line 1364 of file defBF54x_base.h.

#define CAN0_MB24_ID1   0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */

Definition at line 1365 of file defBF54x_base.h.

#define CAN0_MB24_LENGTH   0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */

Definition at line 1362 of file defBF54x_base.h.

#define CAN0_MB24_TIMESTAMP   0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */

Definition at line 1363 of file defBF54x_base.h.

#define CAN0_MB25_DATA0   0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */

Definition at line 1366 of file defBF54x_base.h.

#define CAN0_MB25_DATA1   0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */

Definition at line 1367 of file defBF54x_base.h.

#define CAN0_MB25_DATA2   0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */

Definition at line 1368 of file defBF54x_base.h.

#define CAN0_MB25_DATA3   0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */

Definition at line 1369 of file defBF54x_base.h.

#define CAN0_MB25_ID0   0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */

Definition at line 1372 of file defBF54x_base.h.

#define CAN0_MB25_ID1   0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */

Definition at line 1373 of file defBF54x_base.h.

#define CAN0_MB25_LENGTH   0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */

Definition at line 1370 of file defBF54x_base.h.

#define CAN0_MB25_TIMESTAMP   0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */

Definition at line 1371 of file defBF54x_base.h.

#define CAN0_MB26_DATA0   0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */

Definition at line 1374 of file defBF54x_base.h.

#define CAN0_MB26_DATA1   0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */

Definition at line 1375 of file defBF54x_base.h.

#define CAN0_MB26_DATA2   0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */

Definition at line 1376 of file defBF54x_base.h.

#define CAN0_MB26_DATA3   0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */

Definition at line 1377 of file defBF54x_base.h.

#define CAN0_MB26_ID0   0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */

Definition at line 1380 of file defBF54x_base.h.

#define CAN0_MB26_ID1   0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */

Definition at line 1381 of file defBF54x_base.h.

#define CAN0_MB26_LENGTH   0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */

Definition at line 1378 of file defBF54x_base.h.

#define CAN0_MB26_TIMESTAMP   0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */

Definition at line 1379 of file defBF54x_base.h.

#define CAN0_MB27_DATA0   0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */

Definition at line 1382 of file defBF54x_base.h.

#define CAN0_MB27_DATA1   0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */

Definition at line 1383 of file defBF54x_base.h.

#define CAN0_MB27_DATA2   0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */

Definition at line 1384 of file defBF54x_base.h.

#define CAN0_MB27_DATA3   0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */

Definition at line 1385 of file defBF54x_base.h.

#define CAN0_MB27_ID0   0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */

Definition at line 1388 of file defBF54x_base.h.

#define CAN0_MB27_ID1   0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */

Definition at line 1389 of file defBF54x_base.h.

#define CAN0_MB27_LENGTH   0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */

Definition at line 1386 of file defBF54x_base.h.

#define CAN0_MB27_TIMESTAMP   0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */

Definition at line 1387 of file defBF54x_base.h.

#define CAN0_MB28_DATA0   0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */

Definition at line 1390 of file defBF54x_base.h.

#define CAN0_MB28_DATA1   0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */

Definition at line 1391 of file defBF54x_base.h.

#define CAN0_MB28_DATA2   0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */

Definition at line 1392 of file defBF54x_base.h.

#define CAN0_MB28_DATA3   0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */

Definition at line 1393 of file defBF54x_base.h.

#define CAN0_MB28_ID0   0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */

Definition at line 1396 of file defBF54x_base.h.

#define CAN0_MB28_ID1   0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */

Definition at line 1397 of file defBF54x_base.h.

#define CAN0_MB28_LENGTH   0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */

Definition at line 1394 of file defBF54x_base.h.

#define CAN0_MB28_TIMESTAMP   0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */

Definition at line 1395 of file defBF54x_base.h.

#define CAN0_MB29_DATA0   0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */

Definition at line 1398 of file defBF54x_base.h.

#define CAN0_MB29_DATA1   0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */

Definition at line 1399 of file defBF54x_base.h.

#define CAN0_MB29_DATA2   0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */

Definition at line 1400 of file defBF54x_base.h.

#define CAN0_MB29_DATA3   0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */

Definition at line 1401 of file defBF54x_base.h.

#define CAN0_MB29_ID0   0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */

Definition at line 1404 of file defBF54x_base.h.

#define CAN0_MB29_ID1   0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */

Definition at line 1405 of file defBF54x_base.h.

#define CAN0_MB29_LENGTH   0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */

Definition at line 1402 of file defBF54x_base.h.

#define CAN0_MB29_TIMESTAMP   0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */

Definition at line 1403 of file defBF54x_base.h.

#define CAN0_MB30_DATA0   0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */

Definition at line 1406 of file defBF54x_base.h.

#define CAN0_MB30_DATA1   0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */

Definition at line 1407 of file defBF54x_base.h.

#define CAN0_MB30_DATA2   0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */

Definition at line 1408 of file defBF54x_base.h.

#define CAN0_MB30_DATA3   0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */

Definition at line 1409 of file defBF54x_base.h.

#define CAN0_MB30_ID0   0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */

Definition at line 1412 of file defBF54x_base.h.

#define CAN0_MB30_ID1   0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */

Definition at line 1413 of file defBF54x_base.h.

#define CAN0_MB30_LENGTH   0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */

Definition at line 1410 of file defBF54x_base.h.

#define CAN0_MB30_TIMESTAMP   0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */

Definition at line 1411 of file defBF54x_base.h.

#define CAN0_MB31_DATA0   0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */

Definition at line 1414 of file defBF54x_base.h.

#define CAN0_MB31_DATA1   0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */

Definition at line 1415 of file defBF54x_base.h.

#define CAN0_MB31_DATA2   0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */

Definition at line 1416 of file defBF54x_base.h.

#define CAN0_MB31_DATA3   0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */

Definition at line 1417 of file defBF54x_base.h.

#define CAN0_MB31_ID0   0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */

Definition at line 1420 of file defBF54x_base.h.

#define CAN0_MB31_ID1   0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */

Definition at line 1421 of file defBF54x_base.h.

#define CAN0_MB31_LENGTH   0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */

Definition at line 1418 of file defBF54x_base.h.

#define CAN0_MB31_TIMESTAMP   0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */

Definition at line 1419 of file defBF54x_base.h.

#define CAN0_MBIM1   0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */

Definition at line 1052 of file defBF54x_base.h.

#define CAN0_MBIM2   0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */

Definition at line 1068 of file defBF54x_base.h.

#define CAN0_MBRIF1   0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */

Definition at line 1051 of file defBF54x_base.h.

#define CAN0_MBRIF2   0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */

Definition at line 1067 of file defBF54x_base.h.

#define CAN0_MBTD   0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */

Definition at line 1084 of file defBF54x_base.h.

#define CAN0_MBTIF1   0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */

Definition at line 1050 of file defBF54x_base.h.

#define CAN0_MBTIF2   0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */

Definition at line 1066 of file defBF54x_base.h.

#define CAN0_MC1   0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */

Definition at line 1042 of file defBF54x_base.h.

#define CAN0_MC2   0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */

Definition at line 1058 of file defBF54x_base.h.

#define CAN0_MD1   0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */

Definition at line 1043 of file defBF54x_base.h.

#define CAN0_MD2   0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */

Definition at line 1059 of file defBF54x_base.h.

#define CAN0_OPSS1   0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */

Definition at line 1054 of file defBF54x_base.h.

#define CAN0_OPSS2   0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */

Definition at line 1070 of file defBF54x_base.h.

#define CAN0_RFH1   0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */

Definition at line 1053 of file defBF54x_base.h.

#define CAN0_RFH2   0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */

Definition at line 1069 of file defBF54x_base.h.

#define CAN0_RML1   0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */

Definition at line 1049 of file defBF54x_base.h.

#define CAN0_RML2   0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */

Definition at line 1065 of file defBF54x_base.h.

#define CAN0_RMP1   0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */

Definition at line 1048 of file defBF54x_base.h.

#define CAN0_RMP2   0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */

Definition at line 1064 of file defBF54x_base.h.

#define CAN0_RX   0x8000 /* CAN0 Receive */

Definition at line 1563 of file defBF54x_base.h.

#define CAN0_STATUS   0xffc02a8c /* CAN Controller 0 Global Status Register */

Definition at line 1077 of file defBF54x_base.h.

#define CAN0_TA1   0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */

Definition at line 1046 of file defBF54x_base.h.

#define CAN0_TA2   0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */

Definition at line 1062 of file defBF54x_base.h.

#define CAN0_TIMING   0xffc02a84 /* CAN Controller 0 Timing Register */

Definition at line 1075 of file defBF54x_base.h.

#define CAN0_TRR1   0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */

Definition at line 1045 of file defBF54x_base.h.

#define CAN0_TRR2   0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */

Definition at line 1061 of file defBF54x_base.h.

#define CAN0_TRS1   0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */

Definition at line 1044 of file defBF54x_base.h.

#define CAN0_TRS2   0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */

Definition at line 1060 of file defBF54x_base.h.

#define CAN0_TX   0x10000 /* CAN0 Transmit */

Definition at line 1564 of file defBF54x_base.h.

#define CAN0_UCCNF   0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */

Definition at line 1089 of file defBF54x_base.h.

#define CAN0_UCCNT   0xffc02ac4 /* CAN Controller 0 Universal Counter Register */

Definition at line 1087 of file defBF54x_base.h.

#define CAN0_UCRC   0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */

Definition at line 1088 of file defBF54x_base.h.

#define CAN1_ERR   0x40000000 /* CAN1 Error */

Definition at line 1578 of file defBF54x_base.h.

#define CAN1_RX   0x40 /* CAN1 Receive */

Definition at line 1592 of file defBF54x_base.h.

#define CAN1_TX   0x80 /* CAN1 Transmit */

Definition at line 1593 of file defBF54x_base.h.

#define CARCOUNT   0x40000 /* Clear auto-refresh count */

Definition at line 1836 of file defBF54x_base.h.

#define CASLATENCY   0x70 /* CAS latency */

Definition at line 1748 of file defBF54x_base.h.

#define CB0WCOUNT   0x1 /* Clear write count 0 */

Definition at line 1818 of file defBF54x_base.h.

#define CB1RCOUNT   0x200 /* Clear read count 1 */

Definition at line 1827 of file defBF54x_base.h.

#define CB1WCOUNT   0x2 /* Clear write count 1 */

Definition at line 1819 of file defBF54x_base.h.

#define CB2RCOUNT   0x400 /* Clear read count 2 */

Definition at line 1828 of file defBF54x_base.h.

#define CB2WCOUNT   0x4 /* Clear write count 2 */

Definition at line 1820 of file defBF54x_base.h.

#define CB3RCOUNT   0x800 /* Clear read count 3 */

Definition at line 1829 of file defBF54x_base.h.

#define CB3WCOUNT   0x8 /* Clear write count 3 */

Definition at line 1821 of file defBF54x_base.h.

#define CB4RCOUNT   0x1000 /* Clear read count 4 */

Definition at line 1830 of file defBF54x_base.h.

#define CB4WCOUNT   0x10 /* Clear write count 4 */

Definition at line 1822 of file defBF54x_base.h.

#define CB5RCOUNT   0x2000 /* Clear read count 5 */

Definition at line 1831 of file defBF54x_base.h.

#define CB5WCOUNT   0x20 /* Clear write count 5 */

Definition at line 1823 of file defBF54x_base.h.

#define CB6RCOUNT   0x4000 /* Clear read count 6 */

Definition at line 1832 of file defBF54x_base.h.

#define CB6WCOUNT   0x40 /* Clear write count 6 */

Definition at line 1824 of file defBF54x_base.h.

#define CB7RCOUNT   0x8000 /* Clear read count 7 */

Definition at line 1833 of file defBF54x_base.h.

#define CB7WCOUNT   0x80 /* Clear write count 7 */

Definition at line 1825 of file defBF54x_base.h.

#define CBRCOUNT   0x100 /* Clear read count 0 */

Definition at line 1826 of file defBF54x_base.h.

#define CFIFO_ERR   0x1 /* Chroma FIFO Error */

Definition at line 1999 of file defBF54x_base.h.

#define CG0COUNT   0x100000 /* Clear grant count 0 */

Definition at line 1837 of file defBF54x_base.h.

#define CG1COUNT   0x200000 /* Clear grant count 1 */

Definition at line 1838 of file defBF54x_base.h.

#define CG2COUNT   0x400000 /* Clear grant count 2 */

Definition at line 1839 of file defBF54x_base.h.

#define CG3COUNT   0x800000 /* Clear grant count 3 */

Definition at line 1840 of file defBF54x_base.h.

#define CHIPID   0xffc00014

Definition at line 25 of file defBF54x_base.h.

#define CHIPID_FAMILY   0x0FFFF000

Definition at line 28 of file defBF54x_base.h.

#define CHIPID_MANUFACTURE   0x00000FFE

Definition at line 29 of file defBF54x_base.h.

#define CHIPID_VERSION   0xF0000000

Definition at line 27 of file defBF54x_base.h.

#define CL_1_5   0x50 /* DDR CAS Latency = 1.5 cycles */

Definition at line 1751 of file defBF54x_base.h.

#define CL_2   0x20 /* DDR CAS Latency = 2 cycles */

Definition at line 1752 of file defBF54x_base.h.

#define CL_2_5   0x60 /* DDR CAS Latency = 2.5 cycles */

Definition at line 1753 of file defBF54x_base.h.

#define CL_3   0x30 /* DDR CAS Latency = 3 cycles */

Definition at line 1754 of file defBF54x_base.h.

#define CLK_SEL   0x80 /* Timer Clock Select */

Definition at line 1908 of file defBF54x_base.h.

#define CNT   0x10 /* Counter */

Definition at line 1590 of file defBF54x_base.h.

#define CNT_COMMAND   0xffc0420c /* Command Register */

Definition at line 1462 of file defBF54x_base.h.

#define CNT_CONFIG   0xffc04200 /* Configuration Register */

Definition at line 1459 of file defBF54x_base.h.

#define CNT_COUNTER   0xffc04214 /* Counter Register */

Definition at line 1464 of file defBF54x_base.h.

#define CNT_DEBOUNCE   0xffc04210 /* Debounce Register */

Definition at line 1463 of file defBF54x_base.h.

#define CNT_IMASK   0xffc04204 /* Interrupt Mask Register */

Definition at line 1460 of file defBF54x_base.h.

#define CNT_MAX   0xffc04218 /* Maximal Count Register */

Definition at line 1465 of file defBF54x_base.h.

#define CNT_MIN   0xffc0421c /* Minimal Count Register */

Definition at line 1466 of file defBF54x_base.h.

#define CNT_STATUS   0xffc04208 /* Status Register */

Definition at line 1461 of file defBF54x_base.h.

#define CORE_ERROR   0x8 /* Core error */

Definition at line 1775 of file defBF54x_base.h.

#define CORE_MERROR   0x80 /* Core Error (2nd) */

Definition at line 1779 of file defBF54x_base.h.

#define CRACOUNT   0x10000 /* Clear row activation count */

Definition at line 1834 of file defBF54x_base.h.

#define CRWTACOUNT   0x20000 /* Clear R/W turn-around count */

Definition at line 1835 of file defBF54x_base.h.

#define CTYPE   0x40 /* DMA Channel Type */

Definition at line 1615 of file defBF54x_base.h.

#define DAB_TRAFFIC_COUNT   0x700 /* DAB Traffic Control Count */

Definition at line 1629 of file defBF54x_base.h.

#define DAB_TRAFFIC_PERIOD   0x700 /* DAB Traffic Control Period */

Definition at line 1622 of file defBF54x_base.h.

#define DCB_TRAFFIC_COUNT   0xf /* DCB Traffic Control Count */

Definition at line 1627 of file defBF54x_base.h.

#define DCB_TRAFFIC_PERIOD   0xf /* DCB Traffic Control Period */

Definition at line 1620 of file defBF54x_base.h.

#define DDR_DATWIDTH   0x2000 /* DDR data width */

Definition at line 1734 of file defBF54x_base.h.

#define DDR_TMRD (   x)    ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */

Definition at line 1731 of file defBF54x_base.h.

#define DDR_TRAS (   x)    ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */

Definition at line 1714 of file defBF54x_base.h.

#define DDR_TRC (   x)    ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */

Definition at line 1716 of file defBF54x_base.h.

#define DDR_TRCD (   x)    (x&TRCD) /* DDR tRCD = (1~15) cycles */

Definition at line 1733 of file defBF54x_base.h.

#define DDR_TREFI (   x)    (x&TREFI) /* DDR tRFC = (1~15) cycles */

Definition at line 1718 of file defBF54x_base.h.

#define DDR_TRFC (   x)    ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */

Definition at line 1717 of file defBF54x_base.h.

#define DDR_TRP (   x)    ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */

Definition at line 1715 of file defBF54x_base.h.

#define DDR_TWR (   x)    ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */

Definition at line 1732 of file defBF54x_base.h.

#define DDR_TWTR (   x)    ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */

Definition at line 1730 of file defBF54x_base.h.

#define DDRDATWIDTH   0x3000 /* DDR data width */

Definition at line 1725 of file defBF54x_base.h.

#define DDRDEVSIZE   0xc0000 /* DDR device size */

Definition at line 1728 of file defBF54x_base.h.

#define DDRDEVWIDTH   0x30000 /* DDR device width */

Definition at line 1727 of file defBF54x_base.h.

#define DDRSRESET   0x1 /* DDR soft reset */

Definition at line 1783 of file defBF54x_base.h.

#define DEB1_ERROR   0x1 /* DEB1 Error */

Definition at line 1772 of file defBF54x_base.h.

#define DEB1_PFLEN   0x3 /* Pre fetch length for DEB1 accesses */

Definition at line 1762 of file defBF54x_base.h.

#define DEB1_URGENT   0x1000 /* DEB1 Urgent */

Definition at line 1766 of file defBF54x_base.h.

#define DEB2_ERROR   0x2 /* DEB2 Error */

Definition at line 1773 of file defBF54x_base.h.

#define DEB2_MERROR   0x20 /* DEB2 Error (2nd) */

Definition at line 1777 of file defBF54x_base.h.

#define DEB2_PFLEN   0xc /* Pre fetch length for DEB2 accesses */

Definition at line 1763 of file defBF54x_base.h.

#define DEB2_URGENT   0x2000 /* DEB2 Urgent */

Definition at line 1767 of file defBF54x_base.h.

#define DEB3_ERROR   0x4 /* DEB3 Error */

Definition at line 1774 of file defBF54x_base.h.

#define DEB3_MERROR   0x40 /* DEB3 Error (2nd) */

Definition at line 1778 of file defBF54x_base.h.

#define DEB3_PFLEN   0x30 /* Pre fetch length for DEB3 accesses */

Definition at line 1764 of file defBF54x_base.h.

#define DEB3_URGENT   0x4000 /* DEB3 Urgent */

Definition at line 1768 of file defBF54x_base.h.

#define DEB_ARB_PRIORITY   0x700 /* Arbitration between DEB busses */

Definition at line 1765 of file defBF54x_base.h.

#define DEB_MERROR   0x10 /* DEB1 Error (2nd) */

Definition at line 1776 of file defBF54x_base.h.

#define DEB_TRAFFIC_COUNT   0xf0 /* DEB Traffic Control Count */

Definition at line 1628 of file defBF54x_base.h.

#define DEB_TRAFFIC_PERIOD   0xf0 /* DEB Traffic Control Period */

Definition at line 1621 of file defBF54x_base.h.

#define DEVSZ_128   0x80000 /* DDR External Bank Size = 128MB */

Definition at line 1738 of file defBF54x_base.h.

#define DEVSZ_256   0xc0000 /* DDR External Bank Size = 256MB */

Definition at line 1739 of file defBF54x_base.h.

#define DEVSZ_512   0 /* DDR External Bank Size = 512MB */

Definition at line 1740 of file defBF54x_base.h.

#define DEVSZ_64   0x40000 /* DDR External Bank Size = 64MB */

Definition at line 1737 of file defBF54x_base.h.

#define DEVWD_16   0x20000 /* DDR Device Width = 16 Bits */

Definition at line 1743 of file defBF54x_base.h.

#define DEVWD_4   0 /* DDR Device Width = 4 Bits */

Definition at line 1741 of file defBF54x_base.h.

#define DEVWD_8   0x10000 /* DDR Device Width = 8 Bits */

Definition at line 1742 of file defBF54x_base.h.

#define DLEN_10   (1 << 15) /* 001 - 10 bits */

Definition at line 2038 of file defBF54x_base.h.

#define DLEN_12   (2 << 15) /* 010 - 12 bits */

Definition at line 2039 of file defBF54x_base.h.

#define DLEN_14   (3 << 15) /* 011 - 14 bits */

Definition at line 2040 of file defBF54x_base.h.

#define DLEN_16   (4 << 15) /* 100 - 16 bits */

Definition at line 2041 of file defBF54x_base.h.

#define DLEN_18   (5 << 15) /* 101 - 18 bits */

Definition at line 2042 of file defBF54x_base.h.

#define DLEN_24   (6 << 15) /* 110 - 24 bits */

Definition at line 2043 of file defBF54x_base.h.

#define DLEN_8   (0 << 15) /* 000 - 8 bits */

Definition at line 2037 of file defBF54x_base.h.

#define DLENGTH   0x38000 /* Data Length */

Definition at line 2024 of file defBF54x_base.h.

#define DLLRESET   0x100 /* DLL Reset */

Definition at line 1749 of file defBF54x_base.h.

#define DMA0   0x200 /* DMA Channel 0 */

Definition at line 1525 of file defBF54x_base.h.

#define DMA0_CONFIG   0xffc00c08 /* DMA Channel 0 Configuration Register */

Definition at line 209 of file defBF54x_base.h.

#define DMA0_CURR_ADDR   0xffc00c24 /* DMA Channel 0 Current Address Register */

Definition at line 215 of file defBF54x_base.h.

#define DMA0_CURR_DESC_PTR   0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */

Definition at line 214 of file defBF54x_base.h.

#define DMA0_CURR_X_COUNT   0xffc00c30 /* DMA Channel 0 Current X Count Register */

Definition at line 218 of file defBF54x_base.h.

#define DMA0_CURR_Y_COUNT   0xffc00c38 /* DMA Channel 0 Current Y Count Register */

Definition at line 219 of file defBF54x_base.h.

#define DMA0_ERR   0x2 /* DMA Controller 0 Error */

Definition at line 1517 of file defBF54x_base.h.

#define DMA0_IRQ_STATUS   0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */

Definition at line 216 of file defBF54x_base.h.

#define DMA0_NEXT_DESC_PTR   0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */

Definition at line 207 of file defBF54x_base.h.

#define DMA0_PERIPHERAL_MAP   0xffc00c2c /* DMA Channel 0 Peripheral Map Register */

Definition at line 217 of file defBF54x_base.h.

#define DMA0_START_ADDR   0xffc00c04 /* DMA Channel 0 Start Address Register */

Definition at line 208 of file defBF54x_base.h.

#define DMA0_X_COUNT   0xffc00c10 /* DMA Channel 0 X Count Register */

Definition at line 210 of file defBF54x_base.h.

#define DMA0_X_MODIFY   0xffc00c14 /* DMA Channel 0 X Modify Register */

Definition at line 211 of file defBF54x_base.h.

#define DMA0_Y_COUNT   0xffc00c18 /* DMA Channel 0 Y Count Register */

Definition at line 212 of file defBF54x_base.h.

#define DMA0_Y_MODIFY   0xffc00c1c /* DMA Channel 0 Y Modify Register */

Definition at line 213 of file defBF54x_base.h.

#define DMA0OVR   0x800 /* DMA0 Memory Access Override */

Definition at line 1969 of file defBF54x_base.h.

#define DMA0URQ   0x100 /* DMA0 Urgent Request */

Definition at line 2007 of file defBF54x_base.h.

#define DMA1   0x400 /* DMA Channel 1 */

Definition at line 1526 of file defBF54x_base.h.

#define DMA10   0x800 /* DMA Channel 10 */

Definition at line 1559 of file defBF54x_base.h.

#define DMA10_CONFIG   0xffc00e88 /* DMA Channel 10 Configuration Register */

Definition at line 369 of file defBF54x_base.h.

#define DMA10_CURR_ADDR   0xffc00ea4 /* DMA Channel 10 Current Address Register */

Definition at line 375 of file defBF54x_base.h.

#define DMA10_CURR_DESC_PTR   0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */

Definition at line 374 of file defBF54x_base.h.

#define DMA10_CURR_X_COUNT   0xffc00eb0 /* DMA Channel 10 Current X Count Register */

Definition at line 378 of file defBF54x_base.h.

#define DMA10_CURR_Y_COUNT   0xffc00eb8 /* DMA Channel 10 Current Y Count Register */

Definition at line 379 of file defBF54x_base.h.

#define DMA10_IRQ_STATUS   0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */

Definition at line 376 of file defBF54x_base.h.

#define DMA10_NEXT_DESC_PTR   0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */

Definition at line 367 of file defBF54x_base.h.

#define DMA10_PERIPHERAL_MAP   0xffc00eac /* DMA Channel 10 Peripheral Map Register */

Definition at line 377 of file defBF54x_base.h.

#define DMA10_START_ADDR   0xffc00e84 /* DMA Channel 10 Start Address Register */

Definition at line 368 of file defBF54x_base.h.

#define DMA10_X_COUNT   0xffc00e90 /* DMA Channel 10 X Count Register */

Definition at line 370 of file defBF54x_base.h.

#define DMA10_X_MODIFY   0xffc00e94 /* DMA Channel 10 X Modify Register */

Definition at line 371 of file defBF54x_base.h.

#define DMA10_Y_COUNT   0xffc00e98 /* DMA Channel 10 Y Count Register */

Definition at line 372 of file defBF54x_base.h.

#define DMA10_Y_MODIFY   0xffc00e9c /* DMA Channel 10 Y Modify Register */

Definition at line 373 of file defBF54x_base.h.

#define DMA11   0x1000 /* DMA Channel 11 */

Definition at line 1560 of file defBF54x_base.h.

#define DMA11_CONFIG   0xffc00ec8 /* DMA Channel 11 Configuration Register */

Definition at line 385 of file defBF54x_base.h.

#define DMA11_CURR_ADDR   0xffc00ee4 /* DMA Channel 11 Current Address Register */

Definition at line 391 of file defBF54x_base.h.

#define DMA11_CURR_DESC_PTR   0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */

Definition at line 390 of file defBF54x_base.h.

#define DMA11_CURR_X_COUNT   0xffc00ef0 /* DMA Channel 11 Current X Count Register */

Definition at line 394 of file defBF54x_base.h.

#define DMA11_CURR_Y_COUNT   0xffc00ef8 /* DMA Channel 11 Current Y Count Register */

Definition at line 395 of file defBF54x_base.h.

#define DMA11_IRQ_STATUS   0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */

Definition at line 392 of file defBF54x_base.h.

#define DMA11_NEXT_DESC_PTR   0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */

Definition at line 383 of file defBF54x_base.h.

#define DMA11_PERIPHERAL_MAP   0xffc00eec /* DMA Channel 11 Peripheral Map Register */

Definition at line 393 of file defBF54x_base.h.

#define DMA11_START_ADDR   0xffc00ec4 /* DMA Channel 11 Start Address Register */

Definition at line 384 of file defBF54x_base.h.

#define DMA11_X_COUNT   0xffc00ed0 /* DMA Channel 11 X Count Register */

Definition at line 386 of file defBF54x_base.h.

#define DMA11_X_MODIFY   0xffc00ed4 /* DMA Channel 11 X Modify Register */

Definition at line 387 of file defBF54x_base.h.

#define DMA11_Y_COUNT   0xffc00ed8 /* DMA Channel 11 Y Count Register */

Definition at line 388 of file defBF54x_base.h.

#define DMA11_Y_MODIFY   0xffc00edc /* DMA Channel 11 Y Modify Register */

Definition at line 389 of file defBF54x_base.h.

#define DMA12   0x100 /* DMA Channel 12 */

Definition at line 1524 of file defBF54x_base.h.

#define DMA12_CONFIG   0xffc01c08 /* DMA Channel 12 Configuration Register */

Definition at line 699 of file defBF54x_base.h.

#define DMA12_CURR_ADDR   0xffc01c24 /* DMA Channel 12 Current Address Register */

Definition at line 705 of file defBF54x_base.h.

#define DMA12_CURR_DESC_PTR   0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */

Definition at line 704 of file defBF54x_base.h.

#define DMA12_CURR_X_COUNT   0xffc01c30 /* DMA Channel 12 Current X Count Register */

Definition at line 708 of file defBF54x_base.h.

#define DMA12_CURR_Y_COUNT   0xffc01c38 /* DMA Channel 12 Current Y Count Register */

Definition at line 709 of file defBF54x_base.h.

#define DMA12_IRQ_STATUS   0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */

Definition at line 706 of file defBF54x_base.h.

#define DMA12_NEXT_DESC_PTR   0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */

Definition at line 697 of file defBF54x_base.h.

#define DMA12_PERIPHERAL_MAP   0xffc01c2c /* DMA Channel 12 Peripheral Map Register */

Definition at line 707 of file defBF54x_base.h.

#define DMA12_START_ADDR   0xffc01c04 /* DMA Channel 12 Start Address Register */

Definition at line 698 of file defBF54x_base.h.

#define DMA12_X_COUNT   0xffc01c10 /* DMA Channel 12 X Count Register */

Definition at line 700 of file defBF54x_base.h.

#define DMA12_X_MODIFY   0xffc01c14 /* DMA Channel 12 X Modify Register */

Definition at line 701 of file defBF54x_base.h.

#define DMA12_Y_COUNT   0xffc01c18 /* DMA Channel 12 Y Count Register */

Definition at line 702 of file defBF54x_base.h.

#define DMA12_Y_MODIFY   0xffc01c1c /* DMA Channel 12 Y Modify Register */

Definition at line 703 of file defBF54x_base.h.

#define DMA13   0x20 /* DMA Channel 13 */

Definition at line 1553 of file defBF54x_base.h.

#define DMA13_CONFIG   0xffc01c48 /* DMA Channel 13 Configuration Register */

Definition at line 715 of file defBF54x_base.h.

#define DMA13_CURR_ADDR   0xffc01c64 /* DMA Channel 13 Current Address Register */

Definition at line 721 of file defBF54x_base.h.

#define DMA13_CURR_DESC_PTR   0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */

Definition at line 720 of file defBF54x_base.h.

#define DMA13_CURR_X_COUNT   0xffc01c70 /* DMA Channel 13 Current X Count Register */

Definition at line 724 of file defBF54x_base.h.

#define DMA13_CURR_Y_COUNT   0xffc01c78 /* DMA Channel 13 Current Y Count Register */

Definition at line 725 of file defBF54x_base.h.

#define DMA13_IRQ_STATUS   0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */

Definition at line 722 of file defBF54x_base.h.

#define DMA13_NEXT_DESC_PTR   0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */

Definition at line 713 of file defBF54x_base.h.

#define DMA13_PERIPHERAL_MAP   0xffc01c6c /* DMA Channel 13 Peripheral Map Register */

Definition at line 723 of file defBF54x_base.h.

#define DMA13_START_ADDR   0xffc01c44 /* DMA Channel 13 Start Address Register */

Definition at line 714 of file defBF54x_base.h.

#define DMA13_X_COUNT   0xffc01c50 /* DMA Channel 13 X Count Register */

Definition at line 716 of file defBF54x_base.h.

#define DMA13_X_MODIFY   0xffc01c54 /* DMA Channel 13 X Modify Register */

Definition at line 717 of file defBF54x_base.h.

#define DMA13_Y_COUNT   0xffc01c58 /* DMA Channel 13 Y Count Register */

Definition at line 718 of file defBF54x_base.h.

#define DMA13_Y_MODIFY   0xffc01c5c /* DMA Channel 13 Y Modify Register */

Definition at line 719 of file defBF54x_base.h.

#define DMA14   0x40 /* DMA Channel 14 */

Definition at line 1554 of file defBF54x_base.h.

#define DMA14_CONFIG   0xffc01c88 /* DMA Channel 14 Configuration Register */

Definition at line 731 of file defBF54x_base.h.

#define DMA14_CURR_ADDR   0xffc01ca4 /* DMA Channel 14 Current Address Register */

Definition at line 737 of file defBF54x_base.h.

#define DMA14_CURR_DESC_PTR   0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */

Definition at line 736 of file defBF54x_base.h.

#define DMA14_CURR_X_COUNT   0xffc01cb0 /* DMA Channel 14 Current X Count Register */

Definition at line 740 of file defBF54x_base.h.

#define DMA14_CURR_Y_COUNT   0xffc01cb8 /* DMA Channel 14 Current Y Count Register */

Definition at line 741 of file defBF54x_base.h.

#define DMA14_IRQ_STATUS   0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */

Definition at line 738 of file defBF54x_base.h.

#define DMA14_NEXT_DESC_PTR   0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */

Definition at line 729 of file defBF54x_base.h.

#define DMA14_PERIPHERAL_MAP   0xffc01cac /* DMA Channel 14 Peripheral Map Register */

Definition at line 739 of file defBF54x_base.h.

#define DMA14_START_ADDR   0xffc01c84 /* DMA Channel 14 Start Address Register */

Definition at line 730 of file defBF54x_base.h.

#define DMA14_X_COUNT   0xffc01c90 /* DMA Channel 14 X Count Register */

Definition at line 732 of file defBF54x_base.h.

#define DMA14_X_MODIFY   0xffc01c94 /* DMA Channel 14 X Modify Register */

Definition at line 733 of file defBF54x_base.h.

#define DMA14_Y_COUNT   0xffc01c98 /* DMA Channel 14 Y Count Register */

Definition at line 734 of file defBF54x_base.h.

#define DMA14_Y_MODIFY   0xffc01c9c /* DMA Channel 14 Y Modify Register */

Definition at line 735 of file defBF54x_base.h.

#define DMA15   0x1 /* DMA Channel 15 */

Definition at line 1586 of file defBF54x_base.h.

#define DMA15_CONFIG   0xffc01cc8 /* DMA Channel 15 Configuration Register */

Definition at line 747 of file defBF54x_base.h.

#define DMA15_CURR_ADDR   0xffc01ce4 /* DMA Channel 15 Current Address Register */

Definition at line 753 of file defBF54x_base.h.

#define DMA15_CURR_DESC_PTR   0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */

Definition at line 752 of file defBF54x_base.h.

#define DMA15_CURR_X_COUNT   0xffc01cf0 /* DMA Channel 15 Current X Count Register */

Definition at line 756 of file defBF54x_base.h.

#define DMA15_CURR_Y_COUNT   0xffc01cf8 /* DMA Channel 15 Current Y Count Register */

Definition at line 757 of file defBF54x_base.h.

#define DMA15_IRQ_STATUS   0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */

Definition at line 754 of file defBF54x_base.h.

#define DMA15_NEXT_DESC_PTR   0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */

Definition at line 745 of file defBF54x_base.h.

#define DMA15_PERIPHERAL_MAP   0xffc01cec /* DMA Channel 15 Peripheral Map Register */

Definition at line 755 of file defBF54x_base.h.

#define DMA15_START_ADDR   0xffc01cc4 /* DMA Channel 15 Start Address Register */

Definition at line 746 of file defBF54x_base.h.

#define DMA15_X_COUNT   0xffc01cd0 /* DMA Channel 15 X Count Register */

Definition at line 748 of file defBF54x_base.h.

#define DMA15_X_MODIFY   0xffc01cd4 /* DMA Channel 15 X Modify Register */

Definition at line 749 of file defBF54x_base.h.

#define DMA15_Y_COUNT   0xffc01cd8 /* DMA Channel 15 Y Count Register */

Definition at line 750 of file defBF54x_base.h.

#define DMA15_Y_MODIFY   0xffc01cdc /* DMA Channel 15 Y Modify Register */

Definition at line 751 of file defBF54x_base.h.

#define DMA16   0x2 /* DMA Channel 16 */

Definition at line 1587 of file defBF54x_base.h.

#define DMA16_CONFIG   0xffc01d08 /* DMA Channel 16 Configuration Register */

Definition at line 763 of file defBF54x_base.h.

#define DMA16_CURR_ADDR   0xffc01d24 /* DMA Channel 16 Current Address Register */

Definition at line 769 of file defBF54x_base.h.

#define DMA16_CURR_DESC_PTR   0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */

Definition at line 768 of file defBF54x_base.h.

#define DMA16_CURR_X_COUNT   0xffc01d30 /* DMA Channel 16 Current X Count Register */

Definition at line 772 of file defBF54x_base.h.

#define DMA16_CURR_Y_COUNT   0xffc01d38 /* DMA Channel 16 Current Y Count Register */

Definition at line 773 of file defBF54x_base.h.

#define DMA16_IRQ_STATUS   0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */

Definition at line 770 of file defBF54x_base.h.

#define DMA16_NEXT_DESC_PTR   0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */

Definition at line 761 of file defBF54x_base.h.

#define DMA16_PERIPHERAL_MAP   0xffc01d2c /* DMA Channel 16 Peripheral Map Register */

Definition at line 771 of file defBF54x_base.h.

#define DMA16_START_ADDR   0xffc01d04 /* DMA Channel 16 Start Address Register */

Definition at line 762 of file defBF54x_base.h.

#define DMA16_X_COUNT   0xffc01d10 /* DMA Channel 16 X Count Register */

Definition at line 764 of file defBF54x_base.h.

#define DMA16_X_MODIFY   0xffc01d14 /* DMA Channel 16 X Modify Register */

Definition at line 765 of file defBF54x_base.h.

#define DMA16_Y_COUNT   0xffc01d18 /* DMA Channel 16 Y Count Register */

Definition at line 766 of file defBF54x_base.h.

#define DMA16_Y_MODIFY   0xffc01d1c /* DMA Channel 16 Y Modify Register */

Definition at line 767 of file defBF54x_base.h.

#define DMA17   0x4 /* DMA Channel 17 */

Definition at line 1588 of file defBF54x_base.h.

#define DMA17_CONFIG   0xffc01d48 /* DMA Channel 17 Configuration Register */

Definition at line 779 of file defBF54x_base.h.

#define DMA17_CURR_ADDR   0xffc01d64 /* DMA Channel 17 Current Address Register */

Definition at line 785 of file defBF54x_base.h.

#define DMA17_CURR_DESC_PTR   0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */

Definition at line 784 of file defBF54x_base.h.

#define DMA17_CURR_X_COUNT   0xffc01d70 /* DMA Channel 17 Current X Count Register */

Definition at line 788 of file defBF54x_base.h.

#define DMA17_CURR_Y_COUNT   0xffc01d78 /* DMA Channel 17 Current Y Count Register */

Definition at line 789 of file defBF54x_base.h.

#define DMA17_IRQ_STATUS   0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */

Definition at line 786 of file defBF54x_base.h.

#define DMA17_NEXT_DESC_PTR   0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */

Definition at line 777 of file defBF54x_base.h.

#define DMA17_PERIPHERAL_MAP   0xffc01d6c /* DMA Channel 17 Peripheral Map Register */

Definition at line 787 of file defBF54x_base.h.

#define DMA17_START_ADDR   0xffc01d44 /* DMA Channel 17 Start Address Register */

Definition at line 778 of file defBF54x_base.h.

#define DMA17_X_COUNT   0xffc01d50 /* DMA Channel 17 X Count Register */

Definition at line 780 of file defBF54x_base.h.

#define DMA17_X_MODIFY   0xffc01d54 /* DMA Channel 17 X Modify Register */

Definition at line 781 of file defBF54x_base.h.

#define DMA17_Y_COUNT   0xffc01d58 /* DMA Channel 17 Y Count Register */

Definition at line 782 of file defBF54x_base.h.

#define DMA17_Y_MODIFY   0xffc01d5c /* DMA Channel 17 Y Modify Register */

Definition at line 783 of file defBF54x_base.h.

#define DMA18   0x2 /* DMA Channel 18 */

Definition at line 1549 of file defBF54x_base.h.

#define DMA18_CONFIG   0xffc01d88 /* DMA Channel 18 Configuration Register */

Definition at line 795 of file defBF54x_base.h.

#define DMA18_CURR_ADDR   0xffc01da4 /* DMA Channel 18 Current Address Register */

Definition at line 801 of file defBF54x_base.h.

#define DMA18_CURR_DESC_PTR   0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */

Definition at line 800 of file defBF54x_base.h.

#define DMA18_CURR_X_COUNT   0xffc01db0 /* DMA Channel 18 Current X Count Register */

Definition at line 804 of file defBF54x_base.h.

#define DMA18_CURR_Y_COUNT   0xffc01db8 /* DMA Channel 18 Current Y Count Register */

Definition at line 805 of file defBF54x_base.h.

#define DMA18_IRQ_STATUS   0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */

Definition at line 802 of file defBF54x_base.h.

#define DMA18_NEXT_DESC_PTR   0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */

Definition at line 793 of file defBF54x_base.h.

#define DMA18_PERIPHERAL_MAP   0xffc01dac /* DMA Channel 18 Peripheral Map Register */

Definition at line 803 of file defBF54x_base.h.

#define DMA18_START_ADDR   0xffc01d84 /* DMA Channel 18 Start Address Register */

Definition at line 794 of file defBF54x_base.h.

#define DMA18_X_COUNT   0xffc01d90 /* DMA Channel 18 X Count Register */

Definition at line 796 of file defBF54x_base.h.

#define DMA18_X_MODIFY   0xffc01d94 /* DMA Channel 18 X Modify Register */

Definition at line 797 of file defBF54x_base.h.

#define DMA18_Y_COUNT   0xffc01d98 /* DMA Channel 18 Y Count Register */

Definition at line 798 of file defBF54x_base.h.

#define DMA18_Y_MODIFY   0xffc01d9c /* DMA Channel 18 Y Modify Register */

Definition at line 799 of file defBF54x_base.h.

#define DMA19   0x4 /* DMA Channel 19 */

Definition at line 1550 of file defBF54x_base.h.

#define DMA19_CONFIG   0xffc01dc8 /* DMA Channel 19 Configuration Register */

Definition at line 811 of file defBF54x_base.h.

#define DMA19_CURR_ADDR   0xffc01de4 /* DMA Channel 19 Current Address Register */

Definition at line 817 of file defBF54x_base.h.

#define DMA19_CURR_DESC_PTR   0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */

Definition at line 816 of file defBF54x_base.h.

#define DMA19_CURR_X_COUNT   0xffc01df0 /* DMA Channel 19 Current X Count Register */

Definition at line 820 of file defBF54x_base.h.

#define DMA19_CURR_Y_COUNT   0xffc01df8 /* DMA Channel 19 Current Y Count Register */

Definition at line 821 of file defBF54x_base.h.

#define DMA19_IRQ_STATUS   0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */

Definition at line 818 of file defBF54x_base.h.

#define DMA19_NEXT_DESC_PTR   0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */

Definition at line 809 of file defBF54x_base.h.

#define DMA19_PERIPHERAL_MAP   0xffc01dec /* DMA Channel 19 Peripheral Map Register */

Definition at line 819 of file defBF54x_base.h.

#define DMA19_START_ADDR   0xffc01dc4 /* DMA Channel 19 Start Address Register */

Definition at line 810 of file defBF54x_base.h.

#define DMA19_X_COUNT   0xffc01dd0 /* DMA Channel 19 X Count Register */

Definition at line 812 of file defBF54x_base.h.

#define DMA19_X_MODIFY   0xffc01dd4 /* DMA Channel 19 X Modify Register */

Definition at line 813 of file defBF54x_base.h.

#define DMA19_Y_COUNT   0xffc01dd8 /* DMA Channel 19 Y Count Register */

Definition at line 814 of file defBF54x_base.h.

#define DMA19_Y_MODIFY   0xffc01ddc /* DMA Channel 19 Y Modify Register */

Definition at line 815 of file defBF54x_base.h.

#define DMA1_CONFIG   0xffc00c48 /* DMA Channel 1 Configuration Register */

Definition at line 225 of file defBF54x_base.h.

#define DMA1_CURR_ADDR   0xffc00c64 /* DMA Channel 1 Current Address Register */

Definition at line 231 of file defBF54x_base.h.

#define DMA1_CURR_DESC_PTR   0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */

Definition at line 230 of file defBF54x_base.h.

#define DMA1_CURR_X_COUNT   0xffc00c70 /* DMA Channel 1 Current X Count Register */

Definition at line 234 of file defBF54x_base.h.

#define DMA1_CURR_Y_COUNT   0xffc00c78 /* DMA Channel 1 Current Y Count Register */

Definition at line 235 of file defBF54x_base.h.

#define DMA1_ERR   0x1000000 /* DMA Controller 1 Error */

Definition at line 1537 of file defBF54x_base.h.

#define DMA1_IRQ_STATUS   0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */

Definition at line 232 of file defBF54x_base.h.

#define DMA1_NEXT_DESC_PTR   0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */

Definition at line 223 of file defBF54x_base.h.

#define DMA1_PERIPHERAL_MAP   0xffc00c6c /* DMA Channel 1 Peripheral Map Register */

Definition at line 233 of file defBF54x_base.h.

#define DMA1_START_ADDR   0xffc00c44 /* DMA Channel 1 Start Address Register */

Definition at line 224 of file defBF54x_base.h.

#define DMA1_X_COUNT   0xffc00c50 /* DMA Channel 1 X Count Register */

Definition at line 226 of file defBF54x_base.h.

#define DMA1_X_MODIFY   0xffc00c54 /* DMA Channel 1 X Modify Register */

Definition at line 227 of file defBF54x_base.h.

#define DMA1_Y_COUNT   0xffc00c58 /* DMA Channel 1 Y Count Register */

Definition at line 228 of file defBF54x_base.h.

#define DMA1_Y_MODIFY   0xffc00c5c /* DMA Channel 1 Y Modify Register */

Definition at line 229 of file defBF54x_base.h.

#define DMA1OVR   0x1000 /* DMA1 Memory Access Override */

Definition at line 1970 of file defBF54x_base.h.

#define DMA1URQ   0x80 /* DMA1 Urgent Request */

Definition at line 2006 of file defBF54x_base.h.

#define DMA2   0x800 /* DMA Channel 2 */

Definition at line 1527 of file defBF54x_base.h.

#define DMA20   0x8 /* DMA Channel 20 */

Definition at line 1551 of file defBF54x_base.h.

#define DMA20_CONFIG   0xffc01e08 /* DMA Channel 20 Configuration Register */

Definition at line 827 of file defBF54x_base.h.

#define DMA20_CURR_ADDR   0xffc01e24 /* DMA Channel 20 Current Address Register */

Definition at line 833 of file defBF54x_base.h.

#define DMA20_CURR_DESC_PTR   0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */

Definition at line 832 of file defBF54x_base.h.

#define DMA20_CURR_X_COUNT   0xffc01e30 /* DMA Channel 20 Current X Count Register */

Definition at line 836 of file defBF54x_base.h.

#define DMA20_CURR_Y_COUNT   0xffc01e38 /* DMA Channel 20 Current Y Count Register */

Definition at line 837 of file defBF54x_base.h.

#define DMA20_IRQ_STATUS   0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */

Definition at line 834 of file defBF54x_base.h.

#define DMA20_NEXT_DESC_PTR   0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */

Definition at line 825 of file defBF54x_base.h.

#define DMA20_PERIPHERAL_MAP   0xffc01e2c /* DMA Channel 20 Peripheral Map Register */

Definition at line 835 of file defBF54x_base.h.

#define DMA20_START_ADDR   0xffc01e04 /* DMA Channel 20 Start Address Register */

Definition at line 826 of file defBF54x_base.h.

#define DMA20_X_COUNT   0xffc01e10 /* DMA Channel 20 X Count Register */

Definition at line 828 of file defBF54x_base.h.

#define DMA20_X_MODIFY   0xffc01e14 /* DMA Channel 20 X Modify Register */

Definition at line 829 of file defBF54x_base.h.

#define DMA20_Y_COUNT   0xffc01e18 /* DMA Channel 20 Y Count Register */

Definition at line 830 of file defBF54x_base.h.

#define DMA20_Y_MODIFY   0xffc01e1c /* DMA Channel 20 Y Modify Register */

Definition at line 831 of file defBF54x_base.h.

#define DMA21   0x10 /* DMA Channel 21 */

Definition at line 1552 of file defBF54x_base.h.

#define DMA21_CONFIG   0xffc01e48 /* DMA Channel 21 Configuration Register */

Definition at line 843 of file defBF54x_base.h.

#define DMA21_CURR_ADDR   0xffc01e64 /* DMA Channel 21 Current Address Register */

Definition at line 849 of file defBF54x_base.h.

#define DMA21_CURR_DESC_PTR   0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */

Definition at line 848 of file defBF54x_base.h.

#define DMA21_CURR_X_COUNT   0xffc01e70 /* DMA Channel 21 Current X Count Register */

Definition at line 852 of file defBF54x_base.h.

#define DMA21_CURR_Y_COUNT   0xffc01e78 /* DMA Channel 21 Current Y Count Register */

Definition at line 853 of file defBF54x_base.h.

#define DMA21_IRQ_STATUS   0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */

Definition at line 850 of file defBF54x_base.h.

#define DMA21_NEXT_DESC_PTR   0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */

Definition at line 841 of file defBF54x_base.h.

#define DMA21_PERIPHERAL_MAP   0xffc01e6c /* DMA Channel 21 Peripheral Map Register */

Definition at line 851 of file defBF54x_base.h.

#define DMA21_START_ADDR   0xffc01e44 /* DMA Channel 21 Start Address Register */

Definition at line 842 of file defBF54x_base.h.

#define DMA21_X_COUNT   0xffc01e50 /* DMA Channel 21 X Count Register */

Definition at line 844 of file defBF54x_base.h.

#define DMA21_X_MODIFY   0xffc01e54 /* DMA Channel 21 X Modify Register */

Definition at line 845 of file defBF54x_base.h.

#define DMA21_Y_COUNT   0xffc01e58 /* DMA Channel 21 Y Count Register */

Definition at line 846 of file defBF54x_base.h.

#define DMA21_Y_MODIFY   0xffc01e5c /* DMA Channel 21 Y Modify Register */

Definition at line 847 of file defBF54x_base.h.

#define DMA22   0x8 /* DMA Channel 22 */

Definition at line 1589 of file defBF54x_base.h.

#define DMA22_CONFIG   0xffc01e88 /* DMA Channel 22 Configuration Register */

Definition at line 859 of file defBF54x_base.h.

#define DMA22_CURR_ADDR   0xffc01ea4 /* DMA Channel 22 Current Address Register */

Definition at line 865 of file defBF54x_base.h.

#define DMA22_CURR_DESC_PTR   0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */

Definition at line 864 of file defBF54x_base.h.

#define DMA22_CURR_X_COUNT   0xffc01eb0 /* DMA Channel 22 Current X Count Register */

Definition at line 868 of file defBF54x_base.h.

#define DMA22_CURR_Y_COUNT   0xffc01eb8 /* DMA Channel 22 Current Y Count Register */

Definition at line 869 of file defBF54x_base.h.

#define DMA22_IRQ_STATUS   0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */

Definition at line 866 of file defBF54x_base.h.

#define DMA22_NEXT_DESC_PTR   0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */

Definition at line 857 of file defBF54x_base.h.

#define DMA22_PERIPHERAL_MAP   0xffc01eac /* DMA Channel 22 Peripheral Map Register */

Definition at line 867 of file defBF54x_base.h.

#define DMA22_START_ADDR   0xffc01e84 /* DMA Channel 22 Start Address Register */

Definition at line 858 of file defBF54x_base.h.

#define DMA22_X_COUNT   0xffc01e90 /* DMA Channel 22 X Count Register */

Definition at line 860 of file defBF54x_base.h.

#define DMA22_X_MODIFY   0xffc01e94 /* DMA Channel 22 X Modify Register */

Definition at line 861 of file defBF54x_base.h.

#define DMA22_Y_COUNT   0xffc01e98 /* DMA Channel 22 Y Count Register */

Definition at line 862 of file defBF54x_base.h.

#define DMA22_Y_MODIFY   0xffc01e9c /* DMA Channel 22 Y Modify Register */

Definition at line 863 of file defBF54x_base.h.

#define DMA23   0x100 /* DMA Channel 23 */

Definition at line 1556 of file defBF54x_base.h.

#define DMA23_CONFIG   0xffc01ec8 /* DMA Channel 23 Configuration Register */

Definition at line 875 of file defBF54x_base.h.

#define DMA23_CURR_ADDR   0xffc01ee4 /* DMA Channel 23 Current Address Register */

Definition at line 881 of file defBF54x_base.h.

#define DMA23_CURR_DESC_PTR   0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */

Definition at line 880 of file defBF54x_base.h.

#define DMA23_CURR_X_COUNT   0xffc01ef0 /* DMA Channel 23 Current X Count Register */

Definition at line 884 of file defBF54x_base.h.

#define DMA23_CURR_Y_COUNT   0xffc01ef8 /* DMA Channel 23 Current Y Count Register */

Definition at line 885 of file defBF54x_base.h.

#define DMA23_IRQ_STATUS   0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */

Definition at line 882 of file defBF54x_base.h.

#define DMA23_NEXT_DESC_PTR   0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */

Definition at line 873 of file defBF54x_base.h.

#define DMA23_PERIPHERAL_MAP   0xffc01eec /* DMA Channel 23 Peripheral Map Register */

Definition at line 883 of file defBF54x_base.h.

#define DMA23_START_ADDR   0xffc01ec4 /* DMA Channel 23 Start Address Register */

Definition at line 874 of file defBF54x_base.h.

#define DMA23_X_COUNT   0xffc01ed0 /* DMA Channel 23 X Count Register */

Definition at line 876 of file defBF54x_base.h.

#define DMA23_X_MODIFY   0xffc01ed4 /* DMA Channel 23 X Modify Register */

Definition at line 877 of file defBF54x_base.h.

#define DMA23_Y_COUNT   0xffc01ed8 /* DMA Channel 23 Y Count Register */

Definition at line 878 of file defBF54x_base.h.

#define DMA23_Y_MODIFY   0xffc01edc /* DMA Channel 23 Y Modify Register */

Definition at line 879 of file defBF54x_base.h.

#define DMA2_CONFIG   0xffc00c88 /* DMA Channel 2 Configuration Register */

Definition at line 241 of file defBF54x_base.h.

#define DMA2_CURR_ADDR   0xffc00ca4 /* DMA Channel 2 Current Address Register */

Definition at line 247 of file defBF54x_base.h.

#define DMA2_CURR_DESC_PTR   0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */

Definition at line 246 of file defBF54x_base.h.

#define DMA2_CURR_X_COUNT   0xffc00cb0 /* DMA Channel 2 Current X Count Register */

Definition at line 250 of file defBF54x_base.h.

#define DMA2_CURR_Y_COUNT   0xffc00cb8 /* DMA Channel 2 Current Y Count Register */

Definition at line 251 of file defBF54x_base.h.

#define DMA2_IRQ_STATUS   0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */

Definition at line 248 of file defBF54x_base.h.

#define DMA2_NEXT_DESC_PTR   0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */

Definition at line 239 of file defBF54x_base.h.

#define DMA2_PERIPHERAL_MAP   0xffc00cac /* DMA Channel 2 Peripheral Map Register */

Definition at line 249 of file defBF54x_base.h.

#define DMA2_START_ADDR   0xffc00c84 /* DMA Channel 2 Start Address Register */

Definition at line 240 of file defBF54x_base.h.

#define DMA2_X_COUNT   0xffc00c90 /* DMA Channel 2 X Count Register */

Definition at line 242 of file defBF54x_base.h.

#define DMA2_X_MODIFY   0xffc00c94 /* DMA Channel 2 X Modify Register */

Definition at line 243 of file defBF54x_base.h.

#define DMA2_Y_COUNT   0xffc00c98 /* DMA Channel 2 Y Count Register */

Definition at line 244 of file defBF54x_base.h.

#define DMA2_Y_MODIFY   0xffc00c9c /* DMA Channel 2 Y Modify Register */

Definition at line 245 of file defBF54x_base.h.

#define DMA3   0x1000 /* DMA Channel 3 */

Definition at line 1528 of file defBF54x_base.h.

#define DMA3_CONFIG   0xffc00cc8 /* DMA Channel 3 Configuration Register */

Definition at line 257 of file defBF54x_base.h.

#define DMA3_CURR_ADDR   0xffc00ce4 /* DMA Channel 3 Current Address Register */

Definition at line 263 of file defBF54x_base.h.

#define DMA3_CURR_DESC_PTR   0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */

Definition at line 262 of file defBF54x_base.h.

#define DMA3_CURR_X_COUNT   0xffc00cf0 /* DMA Channel 3 Current X Count Register */

Definition at line 266 of file defBF54x_base.h.

#define DMA3_CURR_Y_COUNT   0xffc00cf8 /* DMA Channel 3 Current Y Count Register */

Definition at line 267 of file defBF54x_base.h.

#define DMA3_IRQ_STATUS   0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */

Definition at line 264 of file defBF54x_base.h.

#define DMA3_NEXT_DESC_PTR   0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */

Definition at line 255 of file defBF54x_base.h.

#define DMA3_PERIPHERAL_MAP   0xffc00cec /* DMA Channel 3 Peripheral Map Register */

Definition at line 265 of file defBF54x_base.h.

#define DMA3_START_ADDR   0xffc00cc4 /* DMA Channel 3 Start Address Register */

Definition at line 256 of file defBF54x_base.h.

#define DMA3_X_COUNT   0xffc00cd0 /* DMA Channel 3 X Count Register */

Definition at line 258 of file defBF54x_base.h.

#define DMA3_X_MODIFY   0xffc00cd4 /* DMA Channel 3 X Modify Register */

Definition at line 259 of file defBF54x_base.h.

#define DMA3_Y_COUNT   0xffc00cd8 /* DMA Channel 3 Y Count Register */

Definition at line 260 of file defBF54x_base.h.

#define DMA3_Y_MODIFY   0xffc00cdc /* DMA Channel 3 Y Modify Register */

Definition at line 261 of file defBF54x_base.h.

#define DMA4   0x2000 /* DMA Channel 4 */

Definition at line 1529 of file defBF54x_base.h.

#define DMA4_CONFIG   0xffc00d08 /* DMA Channel 4 Configuration Register */

Definition at line 273 of file defBF54x_base.h.

#define DMA4_CURR_ADDR   0xffc00d24 /* DMA Channel 4 Current Address Register */

Definition at line 279 of file defBF54x_base.h.

#define DMA4_CURR_DESC_PTR   0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */

Definition at line 278 of file defBF54x_base.h.

#define DMA4_CURR_X_COUNT   0xffc00d30 /* DMA Channel 4 Current X Count Register */

Definition at line 282 of file defBF54x_base.h.

#define DMA4_CURR_Y_COUNT   0xffc00d38 /* DMA Channel 4 Current Y Count Register */

Definition at line 283 of file defBF54x_base.h.

#define DMA4_IRQ_STATUS   0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */

Definition at line 280 of file defBF54x_base.h.

#define DMA4_NEXT_DESC_PTR   0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */

Definition at line 271 of file defBF54x_base.h.

#define DMA4_PERIPHERAL_MAP   0xffc00d2c /* DMA Channel 4 Peripheral Map Register */

Definition at line 281 of file defBF54x_base.h.

#define DMA4_START_ADDR   0xffc00d04 /* DMA Channel 4 Start Address Register */

Definition at line 272 of file defBF54x_base.h.

#define DMA4_X_COUNT   0xffc00d10 /* DMA Channel 4 X Count Register */

Definition at line 274 of file defBF54x_base.h.

#define DMA4_X_MODIFY   0xffc00d14 /* DMA Channel 4 X Modify Register */

Definition at line 275 of file defBF54x_base.h.

#define DMA4_Y_COUNT   0xffc00d18 /* DMA Channel 4 Y Count Register */

Definition at line 276 of file defBF54x_base.h.

#define DMA4_Y_MODIFY   0xffc00d1c /* DMA Channel 4 Y Modify Register */

Definition at line 277 of file defBF54x_base.h.

#define DMA5   0x80 /* DMA Channel 5 */

Definition at line 1555 of file defBF54x_base.h.

#define DMA5_CONFIG   0xffc00d48 /* DMA Channel 5 Configuration Register */

Definition at line 289 of file defBF54x_base.h.

#define DMA5_CURR_ADDR   0xffc00d64 /* DMA Channel 5 Current Address Register */

Definition at line 295 of file defBF54x_base.h.

#define DMA5_CURR_DESC_PTR   0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */

Definition at line 294 of file defBF54x_base.h.

#define DMA5_CURR_X_COUNT   0xffc00d70 /* DMA Channel 5 Current X Count Register */

Definition at line 298 of file defBF54x_base.h.

#define DMA5_CURR_Y_COUNT   0xffc00d78 /* DMA Channel 5 Current Y Count Register */

Definition at line 299 of file defBF54x_base.h.

#define DMA5_IRQ_STATUS   0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */

Definition at line 296 of file defBF54x_base.h.

#define DMA5_NEXT_DESC_PTR   0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */

Definition at line 287 of file defBF54x_base.h.

#define DMA5_PERIPHERAL_MAP   0xffc00d6c /* DMA Channel 5 Peripheral Map Register */

Definition at line 297 of file defBF54x_base.h.

#define DMA5_START_ADDR   0xffc00d44 /* DMA Channel 5 Start Address Register */

Definition at line 288 of file defBF54x_base.h.

#define DMA5_X_COUNT   0xffc00d50 /* DMA Channel 5 X Count Register */

Definition at line 290 of file defBF54x_base.h.

#define DMA5_X_MODIFY   0xffc00d54 /* DMA Channel 5 X Modify Register */

Definition at line 291 of file defBF54x_base.h.

#define DMA5_Y_COUNT   0xffc00d58 /* DMA Channel 5 Y Count Register */

Definition at line 292 of file defBF54x_base.h.

#define DMA5_Y_MODIFY   0xffc00d5c /* DMA Channel 5 Y Modify Register */

Definition at line 293 of file defBF54x_base.h.

#define DMA6   0x4000 /* DMA Channel 6 */

Definition at line 1530 of file defBF54x_base.h.

#define DMA6_CONFIG   0xffc00d88 /* DMA Channel 6 Configuration Register */

Definition at line 305 of file defBF54x_base.h.

#define DMA6_CURR_ADDR   0xffc00da4 /* DMA Channel 6 Current Address Register */

Definition at line 311 of file defBF54x_base.h.

#define DMA6_CURR_DESC_PTR   0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */

Definition at line 310 of file defBF54x_base.h.

#define DMA6_CURR_X_COUNT   0xffc00db0 /* DMA Channel 6 Current X Count Register */

Definition at line 314 of file defBF54x_base.h.

#define DMA6_CURR_Y_COUNT   0xffc00db8 /* DMA Channel 6 Current Y Count Register */

Definition at line 315 of file defBF54x_base.h.

#define DMA6_IRQ_STATUS   0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */

Definition at line 312 of file defBF54x_base.h.

#define DMA6_NEXT_DESC_PTR   0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */

Definition at line 303 of file defBF54x_base.h.

#define DMA6_PERIPHERAL_MAP   0xffc00dac /* DMA Channel 6 Peripheral Map Register */

Definition at line 313 of file defBF54x_base.h.

#define DMA6_START_ADDR   0xffc00d84 /* DMA Channel 6 Start Address Register */

Definition at line 304 of file defBF54x_base.h.

#define DMA6_X_COUNT   0xffc00d90 /* DMA Channel 6 X Count Register */

Definition at line 306 of file defBF54x_base.h.

#define DMA6_X_MODIFY   0xffc00d94 /* DMA Channel 6 X Modify Register */

Definition at line 307 of file defBF54x_base.h.

#define DMA6_Y_COUNT   0xffc00d98 /* DMA Channel 6 Y Count Register */

Definition at line 308 of file defBF54x_base.h.

#define DMA6_Y_MODIFY   0xffc00d9c /* DMA Channel 6 Y Modify Register */

Definition at line 309 of file defBF54x_base.h.

#define DMA7   0x8000 /* DMA Channel 7 */

Definition at line 1531 of file defBF54x_base.h.

#define DMA7_CONFIG   0xffc00dc8 /* DMA Channel 7 Configuration Register */

Definition at line 321 of file defBF54x_base.h.

#define DMA7_CURR_ADDR   0xffc00de4 /* DMA Channel 7 Current Address Register */

Definition at line 327 of file defBF54x_base.h.

#define DMA7_CURR_DESC_PTR   0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */

Definition at line 326 of file defBF54x_base.h.

#define DMA7_CURR_X_COUNT   0xffc00df0 /* DMA Channel 7 Current X Count Register */

Definition at line 330 of file defBF54x_base.h.

#define DMA7_CURR_Y_COUNT   0xffc00df8 /* DMA Channel 7 Current Y Count Register */

Definition at line 331 of file defBF54x_base.h.

#define DMA7_IRQ_STATUS   0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */

Definition at line 328 of file defBF54x_base.h.

#define DMA7_NEXT_DESC_PTR   0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */

Definition at line 319 of file defBF54x_base.h.

#define DMA7_PERIPHERAL_MAP   0xffc00dec /* DMA Channel 7 Peripheral Map Register */

Definition at line 329 of file defBF54x_base.h.

#define DMA7_START_ADDR   0xffc00dc4 /* DMA Channel 7 Start Address Register */

Definition at line 320 of file defBF54x_base.h.

#define DMA7_X_COUNT   0xffc00dd0 /* DMA Channel 7 X Count Register */

Definition at line 322 of file defBF54x_base.h.

#define DMA7_X_MODIFY   0xffc00dd4 /* DMA Channel 7 X Modify Register */

Definition at line 323 of file defBF54x_base.h.

#define DMA7_Y_COUNT   0xffc00dd8 /* DMA Channel 7 Y Count Register */

Definition at line 324 of file defBF54x_base.h.

#define DMA7_Y_MODIFY   0xffc00ddc /* DMA Channel 7 Y Modify Register */

Definition at line 325 of file defBF54x_base.h.

#define DMA8   0x200 /* DMA Channel 8 */

Definition at line 1557 of file defBF54x_base.h.

#define DMA8_CONFIG   0xffc00e08 /* DMA Channel 8 Configuration Register */

Definition at line 337 of file defBF54x_base.h.

#define DMA8_CURR_ADDR   0xffc00e24 /* DMA Channel 8 Current Address Register */

Definition at line 343 of file defBF54x_base.h.

#define DMA8_CURR_DESC_PTR   0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */

Definition at line 342 of file defBF54x_base.h.

#define DMA8_CURR_X_COUNT   0xffc00e30 /* DMA Channel 8 Current X Count Register */

Definition at line 346 of file defBF54x_base.h.

#define DMA8_CURR_Y_COUNT   0xffc00e38 /* DMA Channel 8 Current Y Count Register */

Definition at line 347 of file defBF54x_base.h.

#define DMA8_IRQ_STATUS   0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */

Definition at line 344 of file defBF54x_base.h.

#define DMA8_NEXT_DESC_PTR   0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */

Definition at line 335 of file defBF54x_base.h.

#define DMA8_PERIPHERAL_MAP   0xffc00e2c /* DMA Channel 8 Peripheral Map Register */

Definition at line 345 of file defBF54x_base.h.

#define DMA8_START_ADDR   0xffc00e04 /* DMA Channel 8 Start Address Register */

Definition at line 336 of file defBF54x_base.h.

#define DMA8_X_COUNT   0xffc00e10 /* DMA Channel 8 X Count Register */

Definition at line 338 of file defBF54x_base.h.

#define DMA8_X_MODIFY   0xffc00e14 /* DMA Channel 8 X Modify Register */

Definition at line 339 of file defBF54x_base.h.

#define DMA8_Y_COUNT   0xffc00e18 /* DMA Channel 8 Y Count Register */

Definition at line 340 of file defBF54x_base.h.

#define DMA8_Y_MODIFY   0xffc00e1c /* DMA Channel 8 Y Modify Register */

Definition at line 341 of file defBF54x_base.h.

#define DMA9   0x400 /* DMA Channel 9 */

Definition at line 1558 of file defBF54x_base.h.

#define DMA9_CONFIG   0xffc00e48 /* DMA Channel 9 Configuration Register */

Definition at line 353 of file defBF54x_base.h.

#define DMA9_CURR_ADDR   0xffc00e64 /* DMA Channel 9 Current Address Register */

Definition at line 359 of file defBF54x_base.h.

#define DMA9_CURR_DESC_PTR   0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */

Definition at line 358 of file defBF54x_base.h.

#define DMA9_CURR_X_COUNT   0xffc00e70 /* DMA Channel 9 Current X Count Register */

Definition at line 362 of file defBF54x_base.h.

#define DMA9_CURR_Y_COUNT   0xffc00e78 /* DMA Channel 9 Current Y Count Register */

Definition at line 363 of file defBF54x_base.h.

#define DMA9_IRQ_STATUS   0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */

Definition at line 360 of file defBF54x_base.h.

#define DMA9_NEXT_DESC_PTR   0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */

Definition at line 351 of file defBF54x_base.h.

#define DMA9_PERIPHERAL_MAP   0xffc00e6c /* DMA Channel 9 Peripheral Map Register */

Definition at line 361 of file defBF54x_base.h.

#define DMA9_START_ADDR   0xffc00e44 /* DMA Channel 9 Start Address Register */

Definition at line 352 of file defBF54x_base.h.

#define DMA9_X_COUNT   0xffc00e50 /* DMA Channel 9 X Count Register */

Definition at line 354 of file defBF54x_base.h.

#define DMA9_X_MODIFY   0xffc00e54 /* DMA Channel 9 X Modify Register */

Definition at line 355 of file defBF54x_base.h.

#define DMA9_Y_COUNT   0xffc00e58 /* DMA Channel 9 Y Count Register */

Definition at line 356 of file defBF54x_base.h.

#define DMA9_Y_MODIFY   0xffc00e5c /* DMA Channel 9 Y Modify Register */

Definition at line 357 of file defBF54x_base.h.

#define DMAC0_TC_CNT   0xffc00b10 /* DMA Controller 0 Current Counts Register */

Definition at line 203 of file defBF54x_base.h.

#define DMAC0_TC_PER   0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */

Definition at line 202 of file defBF54x_base.h.

#define DMAC1_PERIMUX   0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */

Definition at line 1483 of file defBF54x_base.h.

#define DMAC1_TC_CNT   0xffc01b10 /* DMA Controller 1 Current Counts Register */

Definition at line 693 of file defBF54x_base.h.

#define DMAC1_TC_PER   0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */

Definition at line 692 of file defBF54x_base.h.

#define DMACFG   0x2000000 /* One or Two DMA Channels Mode */

Definition at line 2032 of file defBF54x_base.h.

#define DMAR0   0x80000000 /* DMAR0 Block */

Definition at line 1581 of file defBF54x_base.h.

#define DMAR0_ERR   0x80000000 /* DMAR0 Overflow Error */

Definition at line 1579 of file defBF54x_base.h.

#define DMAR1   0x80000000 /* DMAR1 Block */

Definition at line 1582 of file defBF54x_base.h.

#define DMAR1_ERR   0x80000000 /* DMAR1 Overflow Error */

Definition at line 1580 of file defBF54x_base.h.

#define DOUBLE_FAULT   0x0008 /* Core Double Fault Causes Reset */

Definition at line 1992 of file defBF54x_base.h.

#define EBIU_AMBCTL0   0xffc00a04 /* Asynchronous Memory Bank Control Register */

Definition at line 154 of file defBF54x_base.h.

#define EBIU_AMBCTL1   0xffc00a08 /* Asynchronous Memory Bank Control Register */

Definition at line 155 of file defBF54x_base.h.

#define EBIU_AMGCTL   0xffc00a00 /* Asynchronous Memory Global Control Register */

Definition at line 153 of file defBF54x_base.h.

#define EBIU_ARBSTAT   0xffc00a10 /* Asynchronous Memory Arbiter Status Register */

Definition at line 157 of file defBF54x_base.h.

#define EBIU_DDRACCT   0xffc00aa0 /* DDR Activation Count Register */

Definition at line 190 of file defBF54x_base.h.

#define EBIU_DDRARCT   0xffc00aac /* DDR Auto-refresh Count Register */

Definition at line 192 of file defBF54x_base.h.

#define EBIU_DDRBRC0   0xffc00a60 /* DDR Bank0 Read Count Register */

Definition at line 174 of file defBF54x_base.h.

#define EBIU_DDRBRC1   0xffc00a64 /* DDR Bank1 Read Count Register */

Definition at line 175 of file defBF54x_base.h.

#define EBIU_DDRBRC2   0xffc00a68 /* DDR Bank2 Read Count Register */

Definition at line 176 of file defBF54x_base.h.

#define EBIU_DDRBRC3   0xffc00a6c /* DDR Bank3 Read Count Register */

Definition at line 177 of file defBF54x_base.h.

#define EBIU_DDRBRC4   0xffc00a70 /* DDR Bank4 Read Count Register */

Definition at line 178 of file defBF54x_base.h.

#define EBIU_DDRBRC5   0xffc00a74 /* DDR Bank5 Read Count Register */

Definition at line 179 of file defBF54x_base.h.

#define EBIU_DDRBRC6   0xffc00a78 /* DDR Bank6 Read Count Register */

Definition at line 180 of file defBF54x_base.h.

#define EBIU_DDRBRC7   0xffc00a7c /* DDR Bank7 Read Count Register */

Definition at line 181 of file defBF54x_base.h.

#define EBIU_DDRBWC0   0xffc00a80 /* DDR Bank0 Write Count Register */

Definition at line 182 of file defBF54x_base.h.

#define EBIU_DDRBWC1   0xffc00a84 /* DDR Bank1 Write Count Register */

Definition at line 183 of file defBF54x_base.h.

#define EBIU_DDRBWC2   0xffc00a88 /* DDR Bank2 Write Count Register */

Definition at line 184 of file defBF54x_base.h.

#define EBIU_DDRBWC3   0xffc00a8c /* DDR Bank3 Write Count Register */

Definition at line 185 of file defBF54x_base.h.

#define EBIU_DDRBWC4   0xffc00a90 /* DDR Bank4 Write Count Register */

Definition at line 186 of file defBF54x_base.h.

#define EBIU_DDRBWC5   0xffc00a94 /* DDR Bank5 Write Count Register */

Definition at line 187 of file defBF54x_base.h.

#define EBIU_DDRBWC6   0xffc00a98 /* DDR Bank6 Write Count Register */

Definition at line 188 of file defBF54x_base.h.

#define EBIU_DDRBWC7   0xffc00a9c /* DDR Bank7 Write Count Register */

Definition at line 189 of file defBF54x_base.h.

#define EBIU_DDRCTL0   0xffc00a20 /* DDR Memory Control 0 Register */

Definition at line 163 of file defBF54x_base.h.

#define EBIU_DDRCTL1   0xffc00a24 /* DDR Memory Control 1 Register */

Definition at line 164 of file defBF54x_base.h.

#define EBIU_DDRCTL2   0xffc00a28 /* DDR Memory Control 2 Register */

Definition at line 165 of file defBF54x_base.h.

#define EBIU_DDRCTL3   0xffc00a2c /* DDR Memory Control 3 Register */

Definition at line 166 of file defBF54x_base.h.

#define EBIU_DDRGC0   0xffc00ab0 /* DDR Grant Count 0 Register */

Definition at line 193 of file defBF54x_base.h.

#define EBIU_DDRGC1   0xffc00ab4 /* DDR Grant Count 1 Register */

Definition at line 194 of file defBF54x_base.h.

#define EBIU_DDRGC2   0xffc00ab8 /* DDR Grant Count 2 Register */

Definition at line 195 of file defBF54x_base.h.

#define EBIU_DDRGC3   0xffc00abc /* DDR Grant Count 3 Register */

Definition at line 196 of file defBF54x_base.h.

#define EBIU_DDRMCCL   0xffc00ac4 /* DDR Metrics Counter Clear Register */

Definition at line 198 of file defBF54x_base.h.

#define EBIU_DDRMCEN   0xffc00ac0 /* DDR Metrics Counter Enable Register */

Definition at line 197 of file defBF54x_base.h.

#define EBIU_DDRQUE   0xffc00a30 /* DDR Queue Configuration Register */

Definition at line 167 of file defBF54x_base.h.

#define EBIU_DDRTACT   0xffc00aa8 /* DDR Turn Around Count Register */

Definition at line 191 of file defBF54x_base.h.

#define EBIU_ERRADD   0xffc00a34 /* DDR Error Address Register */

Definition at line 168 of file defBF54x_base.h.

#define EBIU_ERRMST   0xffc00a38 /* DDR Error Master Register */

Definition at line 169 of file defBF54x_base.h.

#define EBIU_FCTL   0xffc00a18 /* Asynchronous Memory Flash Control Register */

Definition at line 159 of file defBF54x_base.h.

#define EBIU_MBSCTL   0xffc00a0c /* Asynchronous Memory Bank Select Control Register */

Definition at line 156 of file defBF54x_base.h.

#define EBIU_MODE   0xffc00a14 /* Asynchronous Mode Control Register */

Definition at line 158 of file defBF54x_base.h.

#define EBIU_RSTCTL   0xffc00a3c /* DDR Reset Control Register */

Definition at line 170 of file defBF54x_base.h.

#define EMU_RUN   0x200 /* Emulation Behavior Select */

Definition at line 1910 of file defBF54x_base.h.

#define EMUDABL   0x1 /* Emulation Disable. */

Definition at line 1964 of file defBF54x_base.h.

#define EMUOVR   0x4000 /* Emulation Override */

Definition at line 1971 of file defBF54x_base.h.

#define EPPI0_ERR   0x4 /* EPPI0 Error */

Definition at line 1518 of file defBF54x_base.h.

#define EPPI1_CLIP   0xffc01334 /* EPPI1 Clipping Register */

Definition at line 485 of file defBF54x_base.h.

#define EPPI1_CLKDIV   0xffc0131c /* EPPI1 Clock Divide Register */

Definition at line 479 of file defBF54x_base.h.

#define EPPI1_CONTROL   0xffc01320 /* EPPI1 Control Register */

Definition at line 480 of file defBF54x_base.h.

#define EPPI1_ERR   0x400000 /* EPPI1 Error */

Definition at line 1570 of file defBF54x_base.h.

#define EPPI1_FRAME   0xffc01314 /* EPPI1 Lines per Frame Register */

Definition at line 477 of file defBF54x_base.h.

#define EPPI1_FS1P_AVPL   0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */

Definition at line 482 of file defBF54x_base.h.

#define EPPI1_FS1W_HBL   0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */

Definition at line 481 of file defBF54x_base.h.

#define EPPI1_FS2P_LAVF   0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */

Definition at line 484 of file defBF54x_base.h.

#define EPPI1_FS2W_LVB   0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */

Definition at line 483 of file defBF54x_base.h.

#define EPPI1_HCOUNT   0xffc01304 /* EPPI1 Horizontal Transfer Count Register */

Definition at line 473 of file defBF54x_base.h.

#define EPPI1_HDELAY   0xffc01308 /* EPPI1 Horizontal Delay Count Register */

Definition at line 474 of file defBF54x_base.h.

#define EPPI1_LINE   0xffc01318 /* EPPI1 Samples per Line Register */

Definition at line 478 of file defBF54x_base.h.

#define EPPI1_STATUS   0xffc01300 /* EPPI1 Status Register */

Definition at line 472 of file defBF54x_base.h.

#define EPPI1_VCOUNT   0xffc0130c /* EPPI1 Vertical Transfer Count Register */

Definition at line 475 of file defBF54x_base.h.

#define EPPI1_VDELAY   0xffc01310 /* EPPI1 Vertical Delay Count Register */

Definition at line 476 of file defBF54x_base.h.

#define EPPI2_CLIP   0xffc02934 /* EPPI2 Clipping Register */

Definition at line 1038 of file defBF54x_base.h.

#define EPPI2_CLKDIV   0xffc0291c /* EPPI2 Clock Divide Register */

Definition at line 1032 of file defBF54x_base.h.

#define EPPI2_CONTROL   0xffc02920 /* EPPI2 Control Register */

Definition at line 1033 of file defBF54x_base.h.

#define EPPI2_ERR   0x800000 /* EPPI2 Error */

Definition at line 1571 of file defBF54x_base.h.

#define EPPI2_FRAME   0xffc02914 /* EPPI2 Lines per Frame Register */

Definition at line 1030 of file defBF54x_base.h.

#define EPPI2_FS1P_AVPL   0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */

Definition at line 1035 of file defBF54x_base.h.

#define EPPI2_FS1W_HBL   0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */

Definition at line 1034 of file defBF54x_base.h.

#define EPPI2_FS2P_LAVF   0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */

Definition at line 1037 of file defBF54x_base.h.

#define EPPI2_FS2W_LVB   0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */

Definition at line 1036 of file defBF54x_base.h.

#define EPPI2_HCOUNT   0xffc02904 /* EPPI2 Horizontal Transfer Count Register */

Definition at line 1026 of file defBF54x_base.h.

#define EPPI2_HDELAY   0xffc02908 /* EPPI2 Horizontal Delay Count Register */

Definition at line 1027 of file defBF54x_base.h.

#define EPPI2_LINE   0xffc02918 /* EPPI2 Samples per Line Register */

Definition at line 1031 of file defBF54x_base.h.

#define EPPI2_STATUS   0xffc02900 /* EPPI2 Status Register */

Definition at line 1025 of file defBF54x_base.h.

#define EPPI2_VCOUNT   0xffc0290c /* EPPI2 Vertical Transfer Count Register */

Definition at line 1028 of file defBF54x_base.h.

#define EPPI2_VDELAY   0xffc02910 /* EPPI2 Vertical Delay Count Register */

Definition at line 1029 of file defBF54x_base.h.

#define EPPI_DIR   0x2 /* Direction */

Definition at line 2014 of file defBF54x_base.h.

#define EPPI_EN   0x1 /* Enable */

Definition at line 2013 of file defBF54x_base.h.

#define ERR_DET   0x4000 /* Preamble Error Detected */

Definition at line 2008 of file defBF54x_base.h.

#define ERR_NCOR   0x40 /* Preamble Error Not Corrected */

Definition at line 2005 of file defBF54x_base.h.

#define ERR_TYP   0xc000 /* Error Type */

Definition at line 1911 of file defBF54x_base.h.

#define EXT_CLK   0x0003

Definition at line 2081 of file defBF54x_base.h.

#define EXTBANK_1   0 /* 1 external bank */

Definition at line 1735 of file defBF54x_base.h.

#define EXTBANK_2   0x4000 /* 2 external banks */

Definition at line 1736 of file defBF54x_base.h.

#define EXTBANKS   0xc000 /* External banks */

Definition at line 1726 of file defBF54x_base.h.

#define F1_ACT   0xffff /* Number of Lines of Active Data in Field 1 */

Definition at line 2055 of file defBF54x_base.h.

#define F1VB_AD   0xff00 /* Vertical Blanking after Field 1 Active Data */

Definition at line 2049 of file defBF54x_base.h.

#define F1VB_BD   0xff /* Vertical Blanking before Field 1 Active Data */

Definition at line 2048 of file defBF54x_base.h.

#define F2_ACT   0xffff0000 /* Number of Lines of Active Data in Field 2 */

Definition at line 2056 of file defBF54x_base.h.

#define F2VB_AD   0xff000000 /* Vertical Blanking after Field 2 Active Data */

Definition at line 2051 of file defBF54x_base.h.

#define F2VB_BD   0xff0000 /* Vertical Blanking before Field 2 Active Data */

Definition at line 2050 of file defBF54x_base.h.

#define FIFO_RWM   0x18000000 /* FIFO Regular Watermarks */

Definition at line 2034 of file defBF54x_base.h.

#define FIFO_UWM   0x60000000 /* FIFO Urgent Watermarks */

Definition at line 2035 of file defBF54x_base.h.

#define FLD   0x8000 /* Field */

Definition at line 2009 of file defBF54x_base.h.

#define FLD_SEL   0x40 /* Field Select/Trigger */

Definition at line 2017 of file defBF54x_base.h.

#define FS_CFG   0x30 /* Frame Sync Configuration */

Definition at line 2016 of file defBF54x_base.h.

#define FTERR_OVR   0x10 /* Frame Track Overflow */

Definition at line 2003 of file defBF54x_base.h.

#define FTERR_UNDR   0x20 /* Frame Track Underflow */

Definition at line 2004 of file defBF54x_base.h.

#define GC0ENABLE   0x100000 /* DDR Grant count 0 enable */

Definition at line 1810 of file defBF54x_base.h.

#define GC1ENABLE   0x200000 /* DDR Grant count 1 enable */

Definition at line 1811 of file defBF54x_base.h.

#define GC2ENABLE   0x400000 /* DDR Grant count 2 enable */

Definition at line 1812 of file defBF54x_base.h.

#define GC3ENABLE   0x800000 /* DDR Grant count 3 enable */

Definition at line 1813 of file defBF54x_base.h.

#define GCCONTROL   0x3000000 /* DDR Grant Count Control */

Definition at line 1814 of file defBF54x_base.h.

#define HIGH_EVEN   0xff000000 /* Upper Limit for Even Bytes (Luma) */

Definition at line 2063 of file defBF54x_base.h.

#define HIGH_ODD   0xff00 /* Upper Limit for Odd Bytes (Chroma) */

Definition at line 2061 of file defBF54x_base.h.

#define HOST_ERR   0x2000000 /* Host DMA Port Error */

Definition at line 1573 of file defBF54x_base.h.

#define IB0   0x1 /* Interrupt Bit 0 */

Definition at line 1883 of file defBF54x_base.h.

#define IB1   0x2 /* Interrupt Bit 1 */

Definition at line 1884 of file defBF54x_base.h.

#define IB10   0x400 /* Interrupt Bit 10 */

Definition at line 1893 of file defBF54x_base.h.

#define IB11   0x800 /* Interrupt Bit 11 */

Definition at line 1894 of file defBF54x_base.h.

#define IB12   0x1000 /* Interrupt Bit 12 */

Definition at line 1895 of file defBF54x_base.h.

#define IB13   0x2000 /* Interrupt Bit 13 */

Definition at line 1896 of file defBF54x_base.h.

#define IB14   0x4000 /* Interrupt Bit 14 */

Definition at line 1897 of file defBF54x_base.h.

#define IB15   0x8000 /* Interrupt Bit 15 */

Definition at line 1898 of file defBF54x_base.h.

#define IB2   0x4 /* Interrupt Bit 2 */

Definition at line 1885 of file defBF54x_base.h.

#define IB3   0x8 /* Interrupt Bit 3 */

Definition at line 1886 of file defBF54x_base.h.

#define IB4   0x10 /* Interrupt Bit 4 */

Definition at line 1887 of file defBF54x_base.h.

#define IB5   0x20 /* Interrupt Bit 5 */

Definition at line 1888 of file defBF54x_base.h.

#define IB6   0x40 /* Interrupt Bit 6 */

Definition at line 1889 of file defBF54x_base.h.

#define IB7   0x80 /* Interrupt Bit 7 */

Definition at line 1890 of file defBF54x_base.h.

#define IB8   0x100 /* Interrupt Bit 8 */

Definition at line 1891 of file defBF54x_base.h.

#define IB9   0x200 /* Interrupt Bit 9 */

Definition at line 1892 of file defBF54x_base.h.

#define ICLKGEN   0x200 /* Internal Clock Generation */

Definition at line 2020 of file defBF54x_base.h.

#define IFSGEN   0x400 /* Internal Frame Sync Generation */

Definition at line 2021 of file defBF54x_base.h.

#define IRQ_ENA   0x10 /* Interrupt Request Enable */

Definition at line 1905 of file defBF54x_base.h.

#define ITU_TYPE   0x80 /* ITU Interlaced or Progressive */

Definition at line 2018 of file defBF54x_base.h.

#define IWR_DISABLE (   x)    (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */

Definition at line 1509 of file defBF54x_base.h.

#define IWR_DISABLE_ALL   0x00000000 /* Wakeup Disable all peripherals */

Definition at line 1506 of file defBF54x_base.h.

#define IWR_ENABLE (   x)    (1 << (x)) /* Wakeup Enable Peripheral #x */

Definition at line 1508 of file defBF54x_base.h.

#define IWR_ENABLE_ALL   0xFFFFFFFF /* Wakeup Enable all peripherals */

Definition at line 1507 of file defBF54x_base.h.

#define KEY   0x20 /* Keypad */

Definition at line 1591 of file defBF54x_base.h.

#define L1DADABL   0xe0 /* L1 Data Bank A Memory Disable. */

Definition at line 1967 of file defBF54x_base.h.

#define L1DBDABL   0x700 /* L1 Data Bank B Memory Disable. */

Definition at line 1968 of file defBF54x_base.h.

#define L1IDABL   0x1c /* L1 Instruction Memory Disable. */

Definition at line 1966 of file defBF54x_base.h.

#define L2DABL   0x70000 /* L2 Memory Disable. */

Definition at line 1973 of file defBF54x_base.h.

#define LOW_EVEN   0xff0000 /* Lower Limit for Even Bytes (Luma) */

Definition at line 2062 of file defBF54x_base.h.

#define LOW_ODD   0xff /* Lower Limit for Odd Bytes (Chroma) */

Definition at line 2060 of file defBF54x_base.h.

#define LTERR_OVR   0x4 /* Line Track Overflow */

Definition at line 2001 of file defBF54x_base.h.

#define LTERR_UNDR   0x8 /* Line Track Underflow */

Definition at line 2002 of file defBF54x_base.h.

#define MDDRENABLE   0x20 /* Mobile DDR enable */

Definition at line 1787 of file defBF54x_base.h.

#define MDMA0   0x200000 /* Memory DMA Stream 0 */

Definition at line 1534 of file defBF54x_base.h.

#define MDMA1   0x400000 /* Memory DMA Stream 1 */

Definition at line 1535 of file defBF54x_base.h.

#define MDMA2   0x20000 /* Memory DMA Stream 0 */

Definition at line 1565 of file defBF54x_base.h.

#define MDMA3   0x40000 /* Memory DMA Stream 1 */

Definition at line 1566 of file defBF54x_base.h.

#define MDMA_D0_CONFIG   0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */

Definition at line 401 of file defBF54x_base.h.

#define MDMA_D0_CURR_ADDR   0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */

Definition at line 407 of file defBF54x_base.h.

#define MDMA_D0_CURR_DESC_PTR   0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */

Definition at line 406 of file defBF54x_base.h.

#define MDMA_D0_CURR_X_COUNT   0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */

Definition at line 410 of file defBF54x_base.h.

#define MDMA_D0_CURR_Y_COUNT   0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */

Definition at line 411 of file defBF54x_base.h.

#define MDMA_D0_IRQ_STATUS   0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */

Definition at line 408 of file defBF54x_base.h.

#define MDMA_D0_NEXT_DESC_PTR   0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */

Definition at line 399 of file defBF54x_base.h.

#define MDMA_D0_PERIPHERAL_MAP   0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */

Definition at line 409 of file defBF54x_base.h.

#define MDMA_D0_START_ADDR   0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */

Definition at line 400 of file defBF54x_base.h.

#define MDMA_D0_X_COUNT   0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */

Definition at line 402 of file defBF54x_base.h.

#define MDMA_D0_X_MODIFY   0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */

Definition at line 403 of file defBF54x_base.h.

#define MDMA_D0_Y_COUNT   0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */

Definition at line 404 of file defBF54x_base.h.

#define MDMA_D0_Y_MODIFY   0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */

Definition at line 405 of file defBF54x_base.h.

#define MDMA_D1_CONFIG   0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */

Definition at line 430 of file defBF54x_base.h.

#define MDMA_D1_CURR_ADDR   0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */

Definition at line 436 of file defBF54x_base.h.

#define MDMA_D1_CURR_DESC_PTR   0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */

Definition at line 435 of file defBF54x_base.h.

#define MDMA_D1_CURR_X_COUNT   0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */

Definition at line 439 of file defBF54x_base.h.

#define MDMA_D1_CURR_Y_COUNT   0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */

Definition at line 440 of file defBF54x_base.h.

#define MDMA_D1_IRQ_STATUS   0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */

Definition at line 437 of file defBF54x_base.h.

#define MDMA_D1_NEXT_DESC_PTR   0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */

Definition at line 428 of file defBF54x_base.h.

#define MDMA_D1_PERIPHERAL_MAP   0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */

Definition at line 438 of file defBF54x_base.h.

#define MDMA_D1_START_ADDR   0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */

Definition at line 429 of file defBF54x_base.h.

#define MDMA_D1_X_COUNT   0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */

Definition at line 431 of file defBF54x_base.h.

#define MDMA_D1_X_MODIFY   0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */

Definition at line 432 of file defBF54x_base.h.

#define MDMA_D1_Y_COUNT   0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */

Definition at line 433 of file defBF54x_base.h.

#define MDMA_D1_Y_MODIFY   0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */

Definition at line 434 of file defBF54x_base.h.

#define MDMA_D2_CONFIG   0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */

Definition at line 891 of file defBF54x_base.h.

#define MDMA_D2_CURR_ADDR   0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */

Definition at line 897 of file defBF54x_base.h.

#define MDMA_D2_CURR_DESC_PTR   0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */

Definition at line 896 of file defBF54x_base.h.

#define MDMA_D2_CURR_X_COUNT   0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */

Definition at line 900 of file defBF54x_base.h.

#define MDMA_D2_CURR_Y_COUNT   0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */

Definition at line 901 of file defBF54x_base.h.

#define MDMA_D2_IRQ_STATUS   0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */

Definition at line 898 of file defBF54x_base.h.

#define MDMA_D2_NEXT_DESC_PTR   0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */

Definition at line 889 of file defBF54x_base.h.

#define MDMA_D2_PERIPHERAL_MAP   0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */

Definition at line 899 of file defBF54x_base.h.

#define MDMA_D2_START_ADDR   0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */

Definition at line 890 of file defBF54x_base.h.

#define MDMA_D2_X_COUNT   0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */

Definition at line 892 of file defBF54x_base.h.

#define MDMA_D2_X_MODIFY   0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */

Definition at line 893 of file defBF54x_base.h.

#define MDMA_D2_Y_COUNT   0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */

Definition at line 894 of file defBF54x_base.h.

#define MDMA_D2_Y_MODIFY   0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */

Definition at line 895 of file defBF54x_base.h.

#define MDMA_D3_CONFIG   0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */

Definition at line 920 of file defBF54x_base.h.

#define MDMA_D3_CURR_ADDR   0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */

Definition at line 926 of file defBF54x_base.h.

#define MDMA_D3_CURR_DESC_PTR   0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */

Definition at line 925 of file defBF54x_base.h.

#define MDMA_D3_CURR_X_COUNT   0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */

Definition at line 929 of file defBF54x_base.h.

#define MDMA_D3_CURR_Y_COUNT   0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */

Definition at line 930 of file defBF54x_base.h.

#define MDMA_D3_IRQ_STATUS   0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */

Definition at line 927 of file defBF54x_base.h.

#define MDMA_D3_NEXT_DESC_PTR   0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */

Definition at line 918 of file defBF54x_base.h.

#define MDMA_D3_PERIPHERAL_MAP   0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */

Definition at line 928 of file defBF54x_base.h.

#define MDMA_D3_START_ADDR   0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */

Definition at line 919 of file defBF54x_base.h.

#define MDMA_D3_X_COUNT   0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */

Definition at line 921 of file defBF54x_base.h.

#define MDMA_D3_X_MODIFY   0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */

Definition at line 922 of file defBF54x_base.h.

#define MDMA_D3_Y_COUNT   0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */

Definition at line 923 of file defBF54x_base.h.

#define MDMA_D3_Y_MODIFY   0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */

Definition at line 924 of file defBF54x_base.h.

#define MDMA_ROUND_ROBIN_COUNT   0xf800 /* MDMA Round Robin Count */

Definition at line 1630 of file defBF54x_base.h.

#define MDMA_ROUND_ROBIN_PERIOD   0xf800 /* MDMA Round Robin Period */

Definition at line 1623 of file defBF54x_base.h.

#define MDMA_S0_CONFIG   0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */

Definition at line 414 of file defBF54x_base.h.

#define MDMA_S0_CURR_ADDR   0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */

Definition at line 420 of file defBF54x_base.h.

#define MDMA_S0_CURR_DESC_PTR   0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */

Definition at line 419 of file defBF54x_base.h.

#define MDMA_S0_CURR_X_COUNT   0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */

Definition at line 423 of file defBF54x_base.h.

#define MDMA_S0_CURR_Y_COUNT   0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */

Definition at line 424 of file defBF54x_base.h.

#define MDMA_S0_IRQ_STATUS   0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */

Definition at line 421 of file defBF54x_base.h.

#define MDMA_S0_NEXT_DESC_PTR   0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */

Definition at line 412 of file defBF54x_base.h.

#define MDMA_S0_PERIPHERAL_MAP   0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */

Definition at line 422 of file defBF54x_base.h.

#define MDMA_S0_START_ADDR   0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */

Definition at line 413 of file defBF54x_base.h.

#define MDMA_S0_X_COUNT   0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */

Definition at line 415 of file defBF54x_base.h.

#define MDMA_S0_X_MODIFY   0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */

Definition at line 416 of file defBF54x_base.h.

#define MDMA_S0_Y_COUNT   0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */

Definition at line 417 of file defBF54x_base.h.

#define MDMA_S0_Y_MODIFY   0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */

Definition at line 418 of file defBF54x_base.h.

#define MDMA_S1_CONFIG   0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */

Definition at line 443 of file defBF54x_base.h.

#define MDMA_S1_CURR_ADDR   0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */

Definition at line 449 of file defBF54x_base.h.

#define MDMA_S1_CURR_DESC_PTR   0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */

Definition at line 448 of file defBF54x_base.h.

#define MDMA_S1_CURR_X_COUNT   0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */

Definition at line 452 of file defBF54x_base.h.

#define MDMA_S1_CURR_Y_COUNT   0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */

Definition at line 453 of file defBF54x_base.h.

#define MDMA_S1_IRQ_STATUS   0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */

Definition at line 450 of file defBF54x_base.h.

#define MDMA_S1_NEXT_DESC_PTR   0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */

Definition at line 441 of file defBF54x_base.h.

#define MDMA_S1_PERIPHERAL_MAP   0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */

Definition at line 451 of file defBF54x_base.h.

#define MDMA_S1_START_ADDR   0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */

Definition at line 442 of file defBF54x_base.h.

#define MDMA_S1_X_COUNT   0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */

Definition at line 444 of file defBF54x_base.h.

#define MDMA_S1_X_MODIFY   0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */

Definition at line 445 of file defBF54x_base.h.

#define MDMA_S1_Y_COUNT   0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */

Definition at line 446 of file defBF54x_base.h.

#define MDMA_S1_Y_MODIFY   0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */

Definition at line 447 of file defBF54x_base.h.

#define MDMA_S2_CONFIG   0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */

Definition at line 904 of file defBF54x_base.h.

#define MDMA_S2_CURR_ADDR   0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */

Definition at line 910 of file defBF54x_base.h.

#define MDMA_S2_CURR_DESC_PTR   0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */

Definition at line 909 of file defBF54x_base.h.

#define MDMA_S2_CURR_X_COUNT   0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */

Definition at line 913 of file defBF54x_base.h.

#define MDMA_S2_CURR_Y_COUNT   0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */

Definition at line 914 of file defBF54x_base.h.

#define MDMA_S2_IRQ_STATUS   0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */

Definition at line 911 of file defBF54x_base.h.

#define MDMA_S2_NEXT_DESC_PTR   0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */

Definition at line 902 of file defBF54x_base.h.

#define MDMA_S2_PERIPHERAL_MAP   0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */

Definition at line 912 of file defBF54x_base.h.

#define MDMA_S2_START_ADDR   0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */

Definition at line 903 of file defBF54x_base.h.

#define MDMA_S2_X_COUNT   0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */

Definition at line 905 of file defBF54x_base.h.

#define MDMA_S2_X_MODIFY   0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */

Definition at line 906 of file defBF54x_base.h.

#define MDMA_S2_Y_COUNT   0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */

Definition at line 907 of file defBF54x_base.h.

#define MDMA_S2_Y_MODIFY   0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */

Definition at line 908 of file defBF54x_base.h.

#define MDMA_S3_CONFIG   0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */

Definition at line 933 of file defBF54x_base.h.

#define MDMA_S3_CURR_ADDR   0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */

Definition at line 939 of file defBF54x_base.h.

#define MDMA_S3_CURR_DESC_PTR   0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */

Definition at line 938 of file defBF54x_base.h.

#define MDMA_S3_CURR_X_COUNT   0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */

Definition at line 942 of file defBF54x_base.h.

#define MDMA_S3_CURR_Y_COUNT   0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */

Definition at line 943 of file defBF54x_base.h.

#define MDMA_S3_IRQ_STATUS   0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */

Definition at line 940 of file defBF54x_base.h.

#define MDMA_S3_NEXT_DESC_PTR   0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */

Definition at line 931 of file defBF54x_base.h.

#define MDMA_S3_PERIPHERAL_MAP   0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */

Definition at line 941 of file defBF54x_base.h.

#define MDMA_S3_START_ADDR   0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */

Definition at line 932 of file defBF54x_base.h.

#define MDMA_S3_X_COUNT   0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */

Definition at line 934 of file defBF54x_base.h.

#define MDMA_S3_X_MODIFY   0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */

Definition at line 935 of file defBF54x_base.h.

#define MDMA_S3_Y_COUNT   0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */

Definition at line 936 of file defBF54x_base.h.

#define MDMA_S3_Y_MODIFY   0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */

Definition at line 937 of file defBF54x_base.h.

#define MUX (   b15,
  b14,
  b13,
  b12,
  b11,
  b10,
  b9,
  b8,
  b7,
  b6,
  b5,
  b4,
  b3,
  b2,
  b1,
  b0 
)
Value:
((((b15)&3) << 30) | \
(((b14)&3) << 28) | \
(((b13)&3) << 26) | \
(((b12)&3) << 24) | \
(((b11)&3) << 22) | \
(((b10)&3) << 20) | \
(((b9) &3) << 18) | \
(((b8) &3) << 16) | \
(((b7) &3) << 14) | \
(((b6) &3) << 12) | \
(((b5) &3) << 10) | \
(((b4) &3) << 8) | \
(((b3) &3) << 6) | \
(((b2) &3) << 4) | \
(((b1) &3) << 2) | \
(((b0) &3)))

Definition at line 2223 of file defBF54x_base.h.

#define MUX0   0x00000003

Definition at line 2127 of file defBF54x_base.h.

#define MUX0_0   0x00000000

Definition at line 2128 of file defBF54x_base.h.

#define MUX0_1   0x00000001

Definition at line 2129 of file defBF54x_base.h.

#define MUX0_2   0x00000002

Definition at line 2130 of file defBF54x_base.h.

#define MUX0_3   0x00000003

Definition at line 2131 of file defBF54x_base.h.

#define MUX1   0x0000000C

Definition at line 2133 of file defBF54x_base.h.

#define MUX10   0x00300000

Definition at line 2187 of file defBF54x_base.h.

#define MUX10_0   0x00000000

Definition at line 2188 of file defBF54x_base.h.

#define MUX10_1   0x00100000

Definition at line 2189 of file defBF54x_base.h.

#define MUX10_2   0x00200000

Definition at line 2190 of file defBF54x_base.h.

#define MUX10_3   0x00300000

Definition at line 2191 of file defBF54x_base.h.

#define MUX11   0x00C00000

Definition at line 2193 of file defBF54x_base.h.

#define MUX11_0   0x00000000

Definition at line 2194 of file defBF54x_base.h.

#define MUX11_1   0x00400000

Definition at line 2195 of file defBF54x_base.h.

#define MUX11_2   0x00800000

Definition at line 2196 of file defBF54x_base.h.

#define MUX11_3   0x00C00000

Definition at line 2197 of file defBF54x_base.h.

#define MUX12   0x03000000

Definition at line 2199 of file defBF54x_base.h.

#define MUX12_0   0x00000000

Definition at line 2200 of file defBF54x_base.h.

#define MUX12_1   0x01000000

Definition at line 2201 of file defBF54x_base.h.

#define MUX12_2   0x02000000

Definition at line 2202 of file defBF54x_base.h.

#define MUX12_3   0x03000000

Definition at line 2203 of file defBF54x_base.h.

#define MUX13   0x0C000000

Definition at line 2205 of file defBF54x_base.h.

#define MUX13_0   0x00000000

Definition at line 2206 of file defBF54x_base.h.

#define MUX13_1   0x04000000

Definition at line 2207 of file defBF54x_base.h.

#define MUX13_2   0x08000000

Definition at line 2208 of file defBF54x_base.h.

#define MUX13_3   0x0C000000

Definition at line 2209 of file defBF54x_base.h.

#define MUX14   0x30000000

Definition at line 2211 of file defBF54x_base.h.

#define MUX14_0   0x00000000

Definition at line 2212 of file defBF54x_base.h.

#define MUX14_1   0x10000000

Definition at line 2213 of file defBF54x_base.h.

#define MUX14_2   0x20000000

Definition at line 2214 of file defBF54x_base.h.

#define MUX14_3   0x30000000

Definition at line 2215 of file defBF54x_base.h.

#define MUX15   0xC0000000

Definition at line 2217 of file defBF54x_base.h.

#define MUX15_0   0x00000000

Definition at line 2218 of file defBF54x_base.h.

#define MUX15_1   0x40000000

Definition at line 2219 of file defBF54x_base.h.

#define MUX15_2   0x80000000

Definition at line 2220 of file defBF54x_base.h.

#define MUX15_3   0xC0000000

Definition at line 2221 of file defBF54x_base.h.

#define MUX1_0   0x00000000

Definition at line 2134 of file defBF54x_base.h.

#define MUX1_1   0x00000004

Definition at line 2135 of file defBF54x_base.h.

#define MUX1_2   0x00000008

Definition at line 2136 of file defBF54x_base.h.

#define MUX1_3   0x0000000C

Definition at line 2137 of file defBF54x_base.h.

#define MUX2   0x00000030

Definition at line 2139 of file defBF54x_base.h.

#define MUX2_0   0x00000000

Definition at line 2140 of file defBF54x_base.h.

#define MUX2_1   0x00000010

Definition at line 2141 of file defBF54x_base.h.

#define MUX2_2   0x00000020

Definition at line 2142 of file defBF54x_base.h.

#define MUX2_3   0x00000030

Definition at line 2143 of file defBF54x_base.h.

#define MUX3   0x000000C0

Definition at line 2145 of file defBF54x_base.h.

#define MUX3_0   0x00000000

Definition at line 2146 of file defBF54x_base.h.

#define MUX3_1   0x00000040

Definition at line 2147 of file defBF54x_base.h.

#define MUX3_2   0x00000080

Definition at line 2148 of file defBF54x_base.h.

#define MUX3_3   0x000000C0

Definition at line 2149 of file defBF54x_base.h.

#define MUX4   0x00000300

Definition at line 2151 of file defBF54x_base.h.

#define MUX4_0   0x00000000

Definition at line 2152 of file defBF54x_base.h.

#define MUX4_1   0x00000100

Definition at line 2153 of file defBF54x_base.h.

#define MUX4_2   0x00000200

Definition at line 2154 of file defBF54x_base.h.

#define MUX4_3   0x00000300

Definition at line 2155 of file defBF54x_base.h.

#define MUX5   0x00000C00

Definition at line 2157 of file defBF54x_base.h.

#define MUX5_0   0x00000000

Definition at line 2158 of file defBF54x_base.h.

#define MUX5_1   0x00000400

Definition at line 2159 of file defBF54x_base.h.

#define MUX5_2   0x00000800

Definition at line 2160 of file defBF54x_base.h.

#define MUX5_3   0x00000C00

Definition at line 2161 of file defBF54x_base.h.

#define MUX6   0x00003000

Definition at line 2163 of file defBF54x_base.h.

#define MUX6_0   0x00000000

Definition at line 2164 of file defBF54x_base.h.

#define MUX6_1   0x00001000

Definition at line 2165 of file defBF54x_base.h.

#define MUX6_2   0x00002000

Definition at line 2166 of file defBF54x_base.h.

#define MUX6_3   0x00003000

Definition at line 2167 of file defBF54x_base.h.

#define MUX7   0x0000C000

Definition at line 2169 of file defBF54x_base.h.

#define MUX7_0   0x00000000

Definition at line 2170 of file defBF54x_base.h.

#define MUX7_1   0x00004000

Definition at line 2171 of file defBF54x_base.h.

#define MUX7_2   0x00008000

Definition at line 2172 of file defBF54x_base.h.

#define MUX7_3   0x0000C000

Definition at line 2173 of file defBF54x_base.h.

#define MUX8   0x00030000

Definition at line 2175 of file defBF54x_base.h.

#define MUX8_0   0x00000000

Definition at line 2176 of file defBF54x_base.h.

#define MUX8_1   0x00010000

Definition at line 2177 of file defBF54x_base.h.

#define MUX8_2   0x00020000

Definition at line 2178 of file defBF54x_base.h.

#define MUX8_3   0x00030000

Definition at line 2179 of file defBF54x_base.h.

#define MUX9   0x000C0000

Definition at line 2181 of file defBF54x_base.h.

#define MUX9_0   0x00000000

Definition at line 2182 of file defBF54x_base.h.

#define MUX9_1   0x00040000

Definition at line 2183 of file defBF54x_base.h.

#define MUX9_2   0x00080000

Definition at line 2184 of file defBF54x_base.h.

#define MUX9_3   0x000C0000

Definition at line 2185 of file defBF54x_base.h.

#define MXVR_AP   0x200000 /* MXVR Asynchronous Packet */

Definition at line 1569 of file defBF54x_base.h.

#define MXVR_CM   0x100000 /* MXVR Control Message */

Definition at line 1568 of file defBF54x_base.h.

#define MXVR_SD   0x8000000 /* MXVR Synchronous Data */

Definition at line 1540 of file defBF54x_base.h.

#define MXVR_STAT   0x80000 /* MXVR Status */

Definition at line 1567 of file defBF54x_base.h.

#define NFC_ADDR   0xffc03b40 /* NAND Address Register */

Definition at line 1452 of file defBF54x_base.h.

#define NFC_CMD   0xffc03b44 /* NAND Command Register */

Definition at line 1453 of file defBF54x_base.h.

#define NFC_COUNT   0xffc03b20 /* NAND ECC Count Register */

Definition at line 1448 of file defBF54x_base.h.

#define NFC_CTL   0xffc03b00 /* NAND Control Register */

Definition at line 1440 of file defBF54x_base.h.

#define NFC_DATA_RD   0xffc03b4c /* NAND Data Read Register */

Definition at line 1455 of file defBF54x_base.h.

#define NFC_DATA_WR   0xffc03b48 /* NAND Data Write Register */

Definition at line 1454 of file defBF54x_base.h.

#define NFC_ECC0   0xffc03b10 /* NAND ECC Register 0 */

Definition at line 1444 of file defBF54x_base.h.

#define NFC_ECC1   0xffc03b14 /* NAND ECC Register 1 */

Definition at line 1445 of file defBF54x_base.h.

#define NFC_ECC2   0xffc03b18 /* NAND ECC Register 2 */

Definition at line 1446 of file defBF54x_base.h.

#define NFC_ECC3   0xffc03b1c /* NAND ECC Register 3 */

Definition at line 1447 of file defBF54x_base.h.

#define NFC_ERR   0x10000000 /* Nand Flash Controller Error */

Definition at line 1576 of file defBF54x_base.h.

#define NFC_IRQMASK   0xffc03b0c /* NAND Interrupt Mask Register */

Definition at line 1443 of file defBF54x_base.h.

#define NFC_IRQSTAT   0xffc03b08 /* NAND Interrupt Status Register */

Definition at line 1442 of file defBF54x_base.h.

#define NFC_PGCTL   0xffc03b28 /* NAND Page Control Register */

Definition at line 1450 of file defBF54x_base.h.

#define NFC_READ   0xffc03b2c /* NAND Read Data Register */

Definition at line 1451 of file defBF54x_base.h.

#define NFC_RST   0xffc03b24 /* NAND ECC Reset Register */

Definition at line 1449 of file defBF54x_base.h.

#define NFC_STAT   0xffc03b04 /* NAND Status Register */

Definition at line 1441 of file defBF54x_base.h.

#define NMI   0x4 /* Non Maskable Interrupt */

Definition at line 1985 of file defBF54x_base.h.

#define OTP_BEN   0xffc04304 /* OTP/Fuse Byte Enable */

Definition at line 1471 of file defBF54x_base.h.

#define OTP_CONTROL   0xffc04300 /* OTP/Fuse Control Register */

Definition at line 1470 of file defBF54x_base.h.

#define OTP_DATA0   0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */

Definition at line 1487 of file defBF54x_base.h.

#define OTP_DATA1   0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */

Definition at line 1488 of file defBF54x_base.h.

#define OTP_DATA2   0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */

Definition at line 1489 of file defBF54x_base.h.

#define OTP_DATA3   0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */

Definition at line 1490 of file defBF54x_base.h.

#define OTP_STATUS   0xffc04308 /* OTP/Fuse Status */

Definition at line 1472 of file defBF54x_base.h.

#define OTP_TIMING   0xffc0430c /* OTP/Fuse Access Timing */

Definition at line 1473 of file defBF54x_base.h.

#define OTPSEC   0x8000 /* OTP Access Complete */

Definition at line 1601 of file defBF54x_base.h.

#define OTPSEN   0x8000 /* OTP Secrets Enable. */

Definition at line 1972 of file defBF54x_base.h.

#define OUT_DIS   0x40 /* Output Pad Disable */

Definition at line 1907 of file defBF54x_base.h.

#define PACKEN   0x100000 /* Packing/Unpacking Enable */

Definition at line 2027 of file defBF54x_base.h.

#define PASR   0x7 /* Partial array self-refresh */

Definition at line 1758 of file defBF54x_base.h.

#define PERIOD_CNT   0x8 /* Period Count */

Definition at line 1904 of file defBF54x_base.h.

#define PFTCHSRESET   0x4 /* DDR prefetch reset */

Definition at line 1784 of file defBF54x_base.h.

#define PGSZ   0x40 /* Page size */

Definition at line 1699 of file defBF54x_base.h.

#define PGWS   0x38 /* Page wait states */

Definition at line 1698 of file defBF54x_base.h.

#define PINT0   0x80000 /* Pin Interrupt 0 */

Definition at line 1532 of file defBF54x_base.h.

#define PINT0_ASSIGN   0xffc0140c /* Pin Interrupt 0 Port Assign Register */

Definition at line 492 of file defBF54x_base.h.

#define PINT0_EDGE_CLEAR   0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */

Definition at line 494 of file defBF54x_base.h.

#define PINT0_EDGE_SET   0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */

Definition at line 493 of file defBF54x_base.h.

#define PINT0_INVERT_CLEAR   0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */

Definition at line 496 of file defBF54x_base.h.

#define PINT0_INVERT_SET   0xffc01418 /* Pin Interrupt 0 Inversion Set Register */

Definition at line 495 of file defBF54x_base.h.

#define PINT0_LATCH   0xffc01424 /* Pin Interrupt 0 Latch Register */

Definition at line 498 of file defBF54x_base.h.

#define PINT0_MASK_CLEAR   0xffc01404 /* Pin Interrupt 0 Mask Clear Register */

Definition at line 490 of file defBF54x_base.h.

#define PINT0_MASK_SET   0xffc01400 /* Pin Interrupt 0 Mask Set Register */

Definition at line 489 of file defBF54x_base.h.

#define PINT0_PINSTATE   0xffc01420 /* Pin Interrupt 0 Pin Status Register */

Definition at line 497 of file defBF54x_base.h.

#define PINT0_REQUEST   0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */

Definition at line 491 of file defBF54x_base.h.

#define PINT1   0x100000 /* Pin Interrupt 1 */

Definition at line 1533 of file defBF54x_base.h.

#define PINT1_ASSIGN   0xffc0143c /* Pin Interrupt 1 Port Assign Register */

Definition at line 505 of file defBF54x_base.h.

#define PINT1_EDGE_CLEAR   0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */

Definition at line 507 of file defBF54x_base.h.

#define PINT1_EDGE_SET   0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */

Definition at line 506 of file defBF54x_base.h.

#define PINT1_INVERT_CLEAR   0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */

Definition at line 509 of file defBF54x_base.h.

#define PINT1_INVERT_SET   0xffc01448 /* Pin Interrupt 1 Inversion Set Register */

Definition at line 508 of file defBF54x_base.h.

#define PINT1_LATCH   0xffc01454 /* Pin Interrupt 1 Latch Register */

Definition at line 511 of file defBF54x_base.h.

#define PINT1_MASK_CLEAR   0xffc01434 /* Pin Interrupt 1 Mask Clear Register */

Definition at line 503 of file defBF54x_base.h.

#define PINT1_MASK_SET   0xffc01430 /* Pin Interrupt 1 Mask Set Register */

Definition at line 502 of file defBF54x_base.h.

#define PINT1_PINSTATE   0xffc01450 /* Pin Interrupt 1 Pin Status Register */

Definition at line 510 of file defBF54x_base.h.

#define PINT1_REQUEST   0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */

Definition at line 504 of file defBF54x_base.h.

#define PINT2   0x40000000 /* Pin Interrupt 2 */

Definition at line 1610 of file defBF54x_base.h.

#define PINT2_ASSIGN   0xffc0146c /* Pin Interrupt 2 Port Assign Register */

Definition at line 518 of file defBF54x_base.h.

#define PINT2_EDGE_CLEAR   0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */

Definition at line 520 of file defBF54x_base.h.

#define PINT2_EDGE_SET   0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */

Definition at line 519 of file defBF54x_base.h.

#define PINT2_INVERT_CLEAR   0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */

Definition at line 522 of file defBF54x_base.h.

#define PINT2_INVERT_SET   0xffc01478 /* Pin Interrupt 2 Inversion Set Register */

Definition at line 521 of file defBF54x_base.h.

#define PINT2_LATCH   0xffc01484 /* Pin Interrupt 2 Latch Register */

Definition at line 524 of file defBF54x_base.h.

#define PINT2_MASK_CLEAR   0xffc01464 /* Pin Interrupt 2 Mask Clear Register */

Definition at line 516 of file defBF54x_base.h.

#define PINT2_MASK_SET   0xffc01460 /* Pin Interrupt 2 Mask Set Register */

Definition at line 515 of file defBF54x_base.h.

#define PINT2_PINSTATE   0xffc01480 /* Pin Interrupt 2 Pin Status Register */

Definition at line 523 of file defBF54x_base.h.

#define PINT2_REQUEST   0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */

Definition at line 517 of file defBF54x_base.h.

#define PINT3   0x80000000 /* Pin Interrupt 3 */

Definition at line 1611 of file defBF54x_base.h.

#define PINT3_ASSIGN   0xffc0149c /* Pin Interrupt 3 Port Assign Register */

Definition at line 531 of file defBF54x_base.h.

#define PINT3_EDGE_CLEAR   0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */

Definition at line 533 of file defBF54x_base.h.

#define PINT3_EDGE_SET   0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */

Definition at line 532 of file defBF54x_base.h.

#define PINT3_INVERT_CLEAR   0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */

Definition at line 535 of file defBF54x_base.h.

#define PINT3_INVERT_SET   0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */

Definition at line 534 of file defBF54x_base.h.

#define PINT3_LATCH   0xffc014b4 /* Pin Interrupt 3 Latch Register */

Definition at line 537 of file defBF54x_base.h.

#define PINT3_MASK_CLEAR   0xffc01494 /* Pin Interrupt 3 Mask Clear Register */

Definition at line 529 of file defBF54x_base.h.

#define PINT3_MASK_SET   0xffc01490 /* Pin Interrupt 3 Mask Set Register */

Definition at line 528 of file defBF54x_base.h.

#define PINT3_PINSTATE   0xffc014b0 /* Pin Interrupt 3 Pin Status Register */

Definition at line 536 of file defBF54x_base.h.

#define PINT3_REQUEST   0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */

Definition at line 530 of file defBF54x_base.h.

#define PIQ0   0x00000001

Definition at line 2085 of file defBF54x_base.h.

#define PIQ1   0x00000002

Definition at line 2086 of file defBF54x_base.h.

#define PIQ10   0x00000400

Definition at line 2097 of file defBF54x_base.h.

#define PIQ11   0x00000800

Definition at line 2098 of file defBF54x_base.h.

#define PIQ12   0x00001000

Definition at line 2100 of file defBF54x_base.h.

#define PIQ13   0x00002000

Definition at line 2101 of file defBF54x_base.h.

#define PIQ14   0x00004000

Definition at line 2102 of file defBF54x_base.h.

#define PIQ15   0x00008000

Definition at line 2103 of file defBF54x_base.h.

#define PIQ16   0x00010000

Definition at line 2105 of file defBF54x_base.h.

#define PIQ17   0x00020000

Definition at line 2106 of file defBF54x_base.h.

#define PIQ18   0x00040000

Definition at line 2107 of file defBF54x_base.h.

#define PIQ19   0x00080000

Definition at line 2108 of file defBF54x_base.h.

#define PIQ2   0x00000004

Definition at line 2087 of file defBF54x_base.h.

#define PIQ20   0x00100000

Definition at line 2110 of file defBF54x_base.h.

#define PIQ21   0x00200000

Definition at line 2111 of file defBF54x_base.h.

#define PIQ22   0x00400000

Definition at line 2112 of file defBF54x_base.h.

#define PIQ23   0x00800000

Definition at line 2113 of file defBF54x_base.h.

#define PIQ24   0x01000000

Definition at line 2115 of file defBF54x_base.h.

#define PIQ25   0x02000000

Definition at line 2116 of file defBF54x_base.h.

#define PIQ26   0x04000000

Definition at line 2117 of file defBF54x_base.h.

#define PIQ27   0x08000000

Definition at line 2118 of file defBF54x_base.h.

#define PIQ28   0x10000000

Definition at line 2120 of file defBF54x_base.h.

#define PIQ29   0x20000000

Definition at line 2121 of file defBF54x_base.h.

#define PIQ3   0x00000008

Definition at line 2088 of file defBF54x_base.h.

#define PIQ30   0x40000000

Definition at line 2122 of file defBF54x_base.h.

#define PIQ31   0x80000000

Definition at line 2123 of file defBF54x_base.h.

#define PIQ4   0x00000010

Definition at line 2090 of file defBF54x_base.h.

#define PIQ5   0x00000020

Definition at line 2091 of file defBF54x_base.h.

#define PIQ6   0x00000040

Definition at line 2092 of file defBF54x_base.h.

#define PIQ7   0x00000080

Definition at line 2093 of file defBF54x_base.h.

#define PIQ8   0x00000100

Definition at line 2095 of file defBF54x_base.h.

#define PIQ9   0x00000200

Definition at line 2096 of file defBF54x_base.h.

#define PIXC_ERR   0x8000000 /* Pixel Compositor Error */

Definition at line 1575 of file defBF54x_base.h.

#define PLL_CTL   0xffc00000 /* PLL Control Register */

Definition at line 17 of file defBF54x_base.h.

#define PLL_DIV   0xffc00004 /* PLL Divisor Register */

Definition at line 18 of file defBF54x_base.h.

#define PLL_LOCKCNT   0xffc00010 /* PLL Lock Count Register */

Definition at line 21 of file defBF54x_base.h.

#define PLL_STAT   0xffc0000c /* PLL Status Register */

Definition at line 20 of file defBF54x_base.h.

#define PLL_WAKEUP   0x1 /* PLL Wakeup */

Definition at line 1513 of file defBF54x_base.h.

#define PMAP   0xf000 /* Peripheral Mapped To This Channel */

Definition at line 1616 of file defBF54x_base.h.

#define PMUXSDH   0x1 /* Peripheral Select for DMA22 channel */

Definition at line 1634 of file defBF54x_base.h.

#define POLC   0x1800 /* Frame Sync and Data Driving/Sampling Edges */

Definition at line 2022 of file defBF54x_base.h.

#define POLS   0x6000 /* Frame Sync Polarity */

Definition at line 2023 of file defBF54x_base.h.

#define PORTA   0xffc014c4 /* GPIO Data Register */

Definition at line 542 of file defBF54x_base.h.

#define PORTA_CLEAR   0xffc014cc /* GPIO Data Clear Register */

Definition at line 544 of file defBF54x_base.h.

#define PORTA_DIR_CLEAR   0xffc014d4 /* GPIO Direction Clear Register */

Definition at line 546 of file defBF54x_base.h.

#define PORTA_DIR_SET   0xffc014d0 /* GPIO Direction Set Register */

Definition at line 545 of file defBF54x_base.h.

#define PORTA_FER   0xffc014c0 /* Function Enable Register */

Definition at line 541 of file defBF54x_base.h.

#define PORTA_INEN   0xffc014d8 /* GPIO Input Enable Register */

Definition at line 547 of file defBF54x_base.h.

#define PORTA_MUX   0xffc014dc /* Multiplexer Control Register */

Definition at line 548 of file defBF54x_base.h.

#define PORTA_SET   0xffc014c8 /* GPIO Data Set Register */

Definition at line 543 of file defBF54x_base.h.

#define PORTB   0xffc014e4 /* GPIO Data Register */

Definition at line 553 of file defBF54x_base.h.

#define PORTB_CLEAR   0xffc014ec /* GPIO Data Clear Register */

Definition at line 555 of file defBF54x_base.h.

#define PORTB_DIR_CLEAR   0xffc014f4 /* GPIO Direction Clear Register */

Definition at line 557 of file defBF54x_base.h.

#define PORTB_DIR_SET   0xffc014f0 /* GPIO Direction Set Register */

Definition at line 556 of file defBF54x_base.h.

#define PORTB_FER   0xffc014e0 /* Function Enable Register */

Definition at line 552 of file defBF54x_base.h.

#define PORTB_INEN   0xffc014f8 /* GPIO Input Enable Register */

Definition at line 558 of file defBF54x_base.h.

#define PORTB_MUX   0xffc014fc /* Multiplexer Control Register */

Definition at line 559 of file defBF54x_base.h.

#define PORTB_SET   0xffc014e8 /* GPIO Data Set Register */

Definition at line 554 of file defBF54x_base.h.

#define PORTC   0xffc01504 /* GPIO Data Register */

Definition at line 564 of file defBF54x_base.h.

#define PORTC_CLEAR   0xffc0150c /* GPIO Data Clear Register */

Definition at line 566 of file defBF54x_base.h.

#define PORTC_DIR_CLEAR   0xffc01514 /* GPIO Direction Clear Register */

Definition at line 568 of file defBF54x_base.h.

#define PORTC_DIR_SET   0xffc01510 /* GPIO Direction Set Register */

Definition at line 567 of file defBF54x_base.h.

#define PORTC_FER   0xffc01500 /* Function Enable Register */

Definition at line 563 of file defBF54x_base.h.

#define PORTC_INEN   0xffc01518 /* GPIO Input Enable Register */

Definition at line 569 of file defBF54x_base.h.

#define PORTC_MUX   0xffc0151c /* Multiplexer Control Register */

Definition at line 570 of file defBF54x_base.h.

#define PORTC_SET   0xffc01508 /* GPIO Data Set Register */

Definition at line 565 of file defBF54x_base.h.

#define PORTD   0xffc01524 /* GPIO Data Register */

Definition at line 575 of file defBF54x_base.h.

#define PORTD_CLEAR   0xffc0152c /* GPIO Data Clear Register */

Definition at line 577 of file defBF54x_base.h.

#define PORTD_DIR_CLEAR   0xffc01534 /* GPIO Direction Clear Register */

Definition at line 579 of file defBF54x_base.h.

#define PORTD_DIR_SET   0xffc01530 /* GPIO Direction Set Register */

Definition at line 578 of file defBF54x_base.h.

#define PORTD_FER   0xffc01520 /* Function Enable Register */

Definition at line 574 of file defBF54x_base.h.

#define PORTD_INEN   0xffc01538 /* GPIO Input Enable Register */

Definition at line 580 of file defBF54x_base.h.

#define PORTD_MUX   0xffc0153c /* Multiplexer Control Register */

Definition at line 581 of file defBF54x_base.h.

#define PORTD_SET   0xffc01528 /* GPIO Data Set Register */

Definition at line 576 of file defBF54x_base.h.

#define PORTE   0xffc01544 /* GPIO Data Register */

Definition at line 586 of file defBF54x_base.h.

#define PORTE_CLEAR   0xffc0154c /* GPIO Data Clear Register */

Definition at line 588 of file defBF54x_base.h.

#define PORTE_DIR_CLEAR   0xffc01554 /* GPIO Direction Clear Register */

Definition at line 590 of file defBF54x_base.h.

#define PORTE_DIR_SET   0xffc01550 /* GPIO Direction Set Register */

Definition at line 589 of file defBF54x_base.h.

#define PORTE_FER   0xffc01540 /* Function Enable Register */

Definition at line 585 of file defBF54x_base.h.

#define PORTE_INEN   0xffc01558 /* GPIO Input Enable Register */

Definition at line 591 of file defBF54x_base.h.

#define PORTE_MUX   0xffc0155c /* Multiplexer Control Register */

Definition at line 592 of file defBF54x_base.h.

#define PORTE_SET   0xffc01548 /* GPIO Data Set Register */

Definition at line 587 of file defBF54x_base.h.

#define PORTF   0xffc01564 /* GPIO Data Register */

Definition at line 597 of file defBF54x_base.h.

#define PORTF_CLEAR   0xffc0156c /* GPIO Data Clear Register */

Definition at line 599 of file defBF54x_base.h.

#define PORTF_DIR_CLEAR   0xffc01574 /* GPIO Direction Clear Register */

Definition at line 601 of file defBF54x_base.h.

#define PORTF_DIR_SET   0xffc01570 /* GPIO Direction Set Register */

Definition at line 600 of file defBF54x_base.h.

#define PORTF_FER   0xffc01560 /* Function Enable Register */

Definition at line 596 of file defBF54x_base.h.

#define PORTF_INEN   0xffc01578 /* GPIO Input Enable Register */

Definition at line 602 of file defBF54x_base.h.

#define PORTF_MUX   0xffc0157c /* Multiplexer Control Register */

Definition at line 603 of file defBF54x_base.h.

#define PORTF_SET   0xffc01568 /* GPIO Data Set Register */

Definition at line 598 of file defBF54x_base.h.

#define PORTG   0xffc01584 /* GPIO Data Register */

Definition at line 608 of file defBF54x_base.h.

#define PORTG_CLEAR   0xffc0158c /* GPIO Data Clear Register */

Definition at line 610 of file defBF54x_base.h.

#define PORTG_DIR_CLEAR   0xffc01594 /* GPIO Direction Clear Register */

Definition at line 612 of file defBF54x_base.h.

#define PORTG_DIR_SET   0xffc01590 /* GPIO Direction Set Register */

Definition at line 611 of file defBF54x_base.h.

#define PORTG_FER   0xffc01580 /* Function Enable Register */

Definition at line 607 of file defBF54x_base.h.

#define PORTG_INEN   0xffc01598 /* GPIO Input Enable Register */

Definition at line 613 of file defBF54x_base.h.

#define PORTG_MUX   0xffc0159c /* Multiplexer Control Register */

Definition at line 614 of file defBF54x_base.h.

#define PORTG_SET   0xffc01588 /* GPIO Data Set Register */

Definition at line 609 of file defBF54x_base.h.

#define PORTH   0xffc015a4 /* GPIO Data Register */

Definition at line 619 of file defBF54x_base.h.

#define PORTH_CLEAR   0xffc015ac /* GPIO Data Clear Register */

Definition at line 621 of file defBF54x_base.h.

#define PORTH_DIR_CLEAR   0xffc015b4 /* GPIO Direction Clear Register */

Definition at line 623 of file defBF54x_base.h.

#define PORTH_DIR_SET   0xffc015b0 /* GPIO Direction Set Register */

Definition at line 622 of file defBF54x_base.h.

#define PORTH_FER   0xffc015a0 /* Function Enable Register */

Definition at line 618 of file defBF54x_base.h.

#define PORTH_INEN   0xffc015b8 /* GPIO Input Enable Register */

Definition at line 624 of file defBF54x_base.h.

#define PORTH_MUX   0xffc015bc /* Multiplexer Control Register */

Definition at line 625 of file defBF54x_base.h.

#define PORTH_SET   0xffc015a8 /* GPIO Data Set Register */

Definition at line 620 of file defBF54x_base.h.

#define PORTI   0xffc015c4 /* GPIO Data Register */

Definition at line 630 of file defBF54x_base.h.

#define PORTI_CLEAR   0xffc015cc /* GPIO Data Clear Register */

Definition at line 632 of file defBF54x_base.h.

#define PORTI_DIR_CLEAR   0xffc015d4 /* GPIO Direction Clear Register */

Definition at line 634 of file defBF54x_base.h.

#define PORTI_DIR_SET   0xffc015d0 /* GPIO Direction Set Register */

Definition at line 633 of file defBF54x_base.h.

#define PORTI_FER   0xffc015c0 /* Function Enable Register */

Definition at line 629 of file defBF54x_base.h.

#define PORTI_INEN   0xffc015d8 /* GPIO Input Enable Register */

Definition at line 635 of file defBF54x_base.h.

#define PORTI_MUX   0xffc015dc /* Multiplexer Control Register */

Definition at line 636 of file defBF54x_base.h.

#define PORTI_SET   0xffc015c8 /* GPIO Data Set Register */

Definition at line 631 of file defBF54x_base.h.

#define PORTJ   0xffc015e4 /* GPIO Data Register */

Definition at line 641 of file defBF54x_base.h.

#define PORTJ_CLEAR   0xffc015ec /* GPIO Data Clear Register */

Definition at line 643 of file defBF54x_base.h.

#define PORTJ_DIR_CLEAR   0xffc015f4 /* GPIO Direction Clear Register */

Definition at line 645 of file defBF54x_base.h.

#define PORTJ_DIR_SET   0xffc015f0 /* GPIO Direction Set Register */

Definition at line 644 of file defBF54x_base.h.

#define PORTJ_FER   0xffc015e0 /* Function Enable Register */

Definition at line 640 of file defBF54x_base.h.

#define PORTJ_INEN   0xffc015f8 /* GPIO Input Enable Register */

Definition at line 646 of file defBF54x_base.h.

#define PORTJ_MUX   0xffc015fc /* Multiplexer Control Register */

Definition at line 647 of file defBF54x_base.h.

#define PORTJ_SET   0xffc015e8 /* GPIO Data Set Register */

Definition at line 642 of file defBF54x_base.h.

#define PULSE_HI   0x4 /* Pulse Polarity */

Definition at line 1903 of file defBF54x_base.h.

#define PWM_OUT   0x0001

Definition at line 2079 of file defBF54x_base.h.

#define Px0   0x1 /* GPIO 0 */

Definition at line 1844 of file defBF54x_base.h.

#define Px1   0x2 /* GPIO 1 */

Definition at line 1845 of file defBF54x_base.h.

#define Px10   0x400 /* GPIO 10 */

Definition at line 1854 of file defBF54x_base.h.

#define Px11   0x800 /* GPIO 11 */

Definition at line 1855 of file defBF54x_base.h.

#define Px12   0x1000 /* GPIO 12 */

Definition at line 1856 of file defBF54x_base.h.

#define Px13   0x2000 /* GPIO 13 */

Definition at line 1857 of file defBF54x_base.h.

#define Px14   0x4000 /* GPIO 14 */

Definition at line 1858 of file defBF54x_base.h.

#define Px15   0x8000 /* GPIO 15 */

Definition at line 1859 of file defBF54x_base.h.

#define Px2   0x4 /* GPIO 2 */

Definition at line 1846 of file defBF54x_base.h.

#define Px3   0x8 /* GPIO 3 */

Definition at line 1847 of file defBF54x_base.h.

#define Px4   0x10 /* GPIO 4 */

Definition at line 1848 of file defBF54x_base.h.

#define Px5   0x20 /* GPIO 5 */

Definition at line 1849 of file defBF54x_base.h.

#define Px6   0x40 /* GPIO 6 */

Definition at line 1850 of file defBF54x_base.h.

#define Px7   0x80 /* GPIO 7 */

Definition at line 1851 of file defBF54x_base.h.

#define Px8   0x100 /* GPIO 8 */

Definition at line 1852 of file defBF54x_base.h.

#define Px9   0x200 /* GPIO 9 */

Definition at line 1853 of file defBF54x_base.h.

#define PxM0   0x3 /* GPIO Mux 0 */

Definition at line 1863 of file defBF54x_base.h.

#define PxM1   0xc /* GPIO Mux 1 */

Definition at line 1864 of file defBF54x_base.h.

#define PxM10   0x300000 /* GPIO Mux 10 */

Definition at line 1873 of file defBF54x_base.h.

#define PxM11   0xc00000 /* GPIO Mux 11 */

Definition at line 1874 of file defBF54x_base.h.

#define PxM12   0x3000000 /* GPIO Mux 12 */

Definition at line 1875 of file defBF54x_base.h.

#define PxM13   0xc000000 /* GPIO Mux 13 */

Definition at line 1876 of file defBF54x_base.h.

#define PxM14   0x30000000 /* GPIO Mux 14 */

Definition at line 1877 of file defBF54x_base.h.

#define PxM15   0xc0000000 /* GPIO Mux 15 */

Definition at line 1878 of file defBF54x_base.h.

#define PxM2   0x30 /* GPIO Mux 2 */

Definition at line 1865 of file defBF54x_base.h.

#define PxM3   0xc0 /* GPIO Mux 3 */

Definition at line 1866 of file defBF54x_base.h.

#define PxM4   0x300 /* GPIO Mux 4 */

Definition at line 1867 of file defBF54x_base.h.

#define PxM5   0xc00 /* GPIO Mux 5 */

Definition at line 1868 of file defBF54x_base.h.

#define PxM6   0x3000 /* GPIO Mux 6 */

Definition at line 1869 of file defBF54x_base.h.

#define PxM7   0xc000 /* GPIO Mux 7 */

Definition at line 1870 of file defBF54x_base.h.

#define PxM8   0x30000 /* GPIO Mux 8 */

Definition at line 1871 of file defBF54x_base.h.

#define PxM9   0xc0000 /* GPIO Mux 9 */

Definition at line 1872 of file defBF54x_base.h.

#define RDDL   0x380 /* Read data delay */

Definition at line 1700 of file defBF54x_base.h.

#define REGE   0x1000 /* Register mode enable */

Definition at line 1750 of file defBF54x_base.h.

#define RESET_DOUBLE   0x2000 /* SW Reset Generated By Core Double-Fault */

Definition at line 1993 of file defBF54x_base.h.

#define RESET_SOFTWARE   0x8000 /* SW Reset Occurred Since Last Read Of SWRST */

Definition at line 1995 of file defBF54x_base.h.

#define RESET_WDOG   0x4000 /* SW Reset Generated By Watchdog Timer */

Definition at line 1994 of file defBF54x_base.h.

#define RGB_FMT_EN   0x4000000 /* RGB Formatting Enable */

Definition at line 2033 of file defBF54x_base.h.

#define ROWACTCENABLE   0x10000 /* DDR Row activate count enable */

Definition at line 1807 of file defBF54x_base.h.

#define RSTDABL   0x2 /* Reset Disable */

Definition at line 1965 of file defBF54x_base.h.

#define RTC   0x80 /* Real-Time Clock */

Definition at line 1523 of file defBF54x_base.h.

#define RTC_ALARM   0xffc00310 /* RTC Alarm Register */

Definition at line 73 of file defBF54x_base.h.

#define RTC_ICTL   0xffc00304 /* RTC Interrupt Control Register */

Definition at line 70 of file defBF54x_base.h.

#define RTC_ISTAT   0xffc00308 /* RTC Interrupt Status Register */

Definition at line 71 of file defBF54x_base.h.

#define RTC_PREN   0xffc00314 /* RTC Prescaler Enable Register */

Definition at line 74 of file defBF54x_base.h.

#define RTC_STAT   0xffc00300 /* RTC Status Register */

Definition at line 69 of file defBF54x_base.h.

#define RTC_SWCNT   0xffc0030c /* RTC Stopwatch Count Register */

Definition at line 72 of file defBF54x_base.h.

#define RWTCENABLE   0x20000 /* DDR R/W Turn around count enable */

Definition at line 1808 of file defBF54x_base.h.

#define SDH_INT_MASK0   0x100 /* SDH Mask 0 */

Definition at line 1594 of file defBF54x_base.h.

#define SDH_INT_MASK1   0x200 /* SDH Mask 1 */

Definition at line 1595 of file defBF54x_base.h.

#define SECMODE   0x3 /* Secured Mode Control State */

Definition at line 1984 of file defBF54x_base.h.

#define SECSTAT   0xe0 /* Secure Status */

Definition at line 1988 of file defBF54x_base.h.

#define SECURE0   0x1 /* SECURE 0 */

Definition at line 1977 of file defBF54x_base.h.

#define SECURE1   0x2 /* SECURE 1 */

Definition at line 1978 of file defBF54x_base.h.

#define SECURE2   0x4 /* SECURE 2 */

Definition at line 1979 of file defBF54x_base.h.

#define SECURE3   0x8 /* SECURE 3 */

Definition at line 1980 of file defBF54x_base.h.

#define SECURE_CONTROL   0xffc04324 /* Secure Control */

Definition at line 1478 of file defBF54x_base.h.

#define SECURE_STATUS   0xffc04328 /* Secure Status */

Definition at line 1479 of file defBF54x_base.h.

#define SECURE_SYSSWT   0xffc04320 /* Secure System Switches */

Definition at line 1477 of file defBF54x_base.h.

#define SIC_IAR0   0xffc00130 /* System Interrupt Assignment Register 0 */

Definition at line 48 of file defBF54x_base.h.

#define SIC_IAR1   0xffc00134 /* System Interrupt Assignment Register 1 */

Definition at line 49 of file defBF54x_base.h.

#define SIC_IAR10   0xffc00158 /* System Interrupt Assignment Register 10 */

Definition at line 58 of file defBF54x_base.h.

#define SIC_IAR11   0xffc0015c /* System Interrupt Assignment Register 11 */

Definition at line 59 of file defBF54x_base.h.

#define SIC_IAR2   0xffc00138 /* System Interrupt Assignment Register 2 */

Definition at line 50 of file defBF54x_base.h.

#define SIC_IAR3   0xffc0013c /* System Interrupt Assignment Register 3 */

Definition at line 51 of file defBF54x_base.h.

#define SIC_IAR4   0xffc00140 /* System Interrupt Assignment Register 4 */

Definition at line 52 of file defBF54x_base.h.

#define SIC_IAR5   0xffc00144 /* System Interrupt Assignment Register 5 */

Definition at line 53 of file defBF54x_base.h.

#define SIC_IAR6   0xffc00148 /* System Interrupt Assignment Register 6 */

Definition at line 54 of file defBF54x_base.h.

#define SIC_IAR7   0xffc0014c /* System Interrupt Assignment Register 7 */

Definition at line 55 of file defBF54x_base.h.

#define SIC_IAR8   0xffc00150 /* System Interrupt Assignment Register 8 */

Definition at line 56 of file defBF54x_base.h.

#define SIC_IAR9   0xffc00154 /* System Interrupt Assignment Register 9 */

Definition at line 57 of file defBF54x_base.h.

#define SIC_IMASK0   0xffc0010c /* System Interrupt Mask Register 0 */

Definition at line 39 of file defBF54x_base.h.

#define SIC_IMASK1   0xffc00110 /* System Interrupt Mask Register 1 */

Definition at line 40 of file defBF54x_base.h.

#define SIC_IMASK2   0xffc00114 /* System Interrupt Mask Register 2 */

Definition at line 41 of file defBF54x_base.h.

#define SIC_ISR0   0xffc00118 /* System Interrupt Status Register 0 */

Definition at line 42 of file defBF54x_base.h.

#define SIC_ISR1   0xffc0011c /* System Interrupt Status Register 1 */

Definition at line 43 of file defBF54x_base.h.

#define SIC_ISR2   0xffc00120 /* System Interrupt Status Register 2 */

Definition at line 44 of file defBF54x_base.h.

#define SIC_IWR0   0xffc00124 /* System Interrupt Wakeup Register 0 */

Definition at line 45 of file defBF54x_base.h.

#define SIC_IWR1   0xffc00128 /* System Interrupt Wakeup Register 1 */

Definition at line 46 of file defBF54x_base.h.

#define SIC_IWR2   0xffc0012c /* System Interrupt Wakeup Register 2 */

Definition at line 47 of file defBF54x_base.h.

#define SIC_MASK (   x)    (1 << (x)) /* Mask Peripheral #x interrupt */

Definition at line 1502 of file defBF54x_base.h.

#define SIC_MASK_ALL   0xFFFFFFFF /* Mask all peripheral interrupts */

Definition at line 1501 of file defBF54x_base.h.

#define SIC_RVECT   0xffc00108

Definition at line 38 of file defBF54x_base.h.

#define SIC_UNMASK (   x)    (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */

Definition at line 1503 of file defBF54x_base.h.

#define SIC_UNMASK_ALL   0x00000000 /* Unmask all peripheral interrupts */

Definition at line 1500 of file defBF54x_base.h.

#define SIGN_EXT   0x400000 /* Sign Extension or Zero-filled / Data Split Format */

Definition at line 2029 of file defBF54x_base.h.

#define SKIP_EN   0x40000 /* Skip Enable */

Definition at line 2025 of file defBF54x_base.h.

#define SKIP_EO   0x80000 /* Skip Even or Odd */

Definition at line 2026 of file defBF54x_base.h.

#define SPI0_BAUD   0xffc00514 /* SPI0 Baud Rate Register */

Definition at line 99 of file defBF54x_base.h.

#define SPI0_CTL   0xffc00500 /* SPI0 Control Register */

Definition at line 94 of file defBF54x_base.h.

#define SPI0_ERR   0x20 /* SPI0 Error */

Definition at line 1521 of file defBF54x_base.h.

#define SPI0_FLG   0xffc00504 /* SPI0 Flag Register */

Definition at line 95 of file defBF54x_base.h.

#define SPI0_RDBR   0xffc00510 /* SPI0 Receive Data Buffer Register */

Definition at line 98 of file defBF54x_base.h.

#define SPI0_REGBASE   0xffc00500

Definition at line 93 of file defBF54x_base.h.

#define SPI0_SHADOW   0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */

Definition at line 100 of file defBF54x_base.h.

#define SPI0_STAT   0xffc00508 /* SPI0 Status Register */

Definition at line 96 of file defBF54x_base.h.

#define SPI0_TDBR   0xffc0050c /* SPI0 Transmit Data Buffer Register */

Definition at line 97 of file defBF54x_base.h.

#define SPI1_BAUD   0xffc02314 /* SPI1 Baud Rate Register */

Definition at line 970 of file defBF54x_base.h.

#define SPI1_CTL   0xffc02300 /* SPI1 Control Register */

Definition at line 965 of file defBF54x_base.h.

#define SPI1_ERR   0x10000000 /* SPI1 Error */

Definition at line 1541 of file defBF54x_base.h.

#define SPI1_FLG   0xffc02304 /* SPI1 Flag Register */

Definition at line 966 of file defBF54x_base.h.

#define SPI1_RDBR   0xffc02310 /* SPI1 Receive Data Buffer Register */

Definition at line 969 of file defBF54x_base.h.

#define SPI1_REGBASE   0xffc02300

Definition at line 964 of file defBF54x_base.h.

#define SPI1_SHADOW   0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */

Definition at line 971 of file defBF54x_base.h.

#define SPI1_STAT   0xffc02308 /* SPI1 Status Register */

Definition at line 967 of file defBF54x_base.h.

#define SPI1_TDBR   0xffc0230c /* SPI1 Transmit Data Buffer Register */

Definition at line 968 of file defBF54x_base.h.

#define SPI2_ERR   0x20000000 /* SPI2 Error */

Definition at line 1542 of file defBF54x_base.h.

#define SPLT_EVEN_ODD   0x800000 /* Split Even and Odd Data Samples */

Definition at line 2030 of file defBF54x_base.h.

#define SPORT0_ERR   0x8 /* SPORT0 Error */

Definition at line 1519 of file defBF54x_base.h.

#define SPORT1_CHNL   0xffc00934 /* SPORT1 Current Channel Register */

Definition at line 139 of file defBF54x_base.h.

#define SPORT1_ERR   0x10 /* SPORT1 Error */

Definition at line 1520 of file defBF54x_base.h.

#define SPORT1_MCMC1   0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */

Definition at line 140 of file defBF54x_base.h.

#define SPORT1_MCMC2   0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */

Definition at line 141 of file defBF54x_base.h.

#define SPORT1_MRCS0   0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */

Definition at line 146 of file defBF54x_base.h.

#define SPORT1_MRCS1   0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */

Definition at line 147 of file defBF54x_base.h.

#define SPORT1_MRCS2   0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */

Definition at line 148 of file defBF54x_base.h.

#define SPORT1_MRCS3   0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */

Definition at line 149 of file defBF54x_base.h.

#define SPORT1_MTCS0   0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */

Definition at line 142 of file defBF54x_base.h.

#define SPORT1_MTCS1   0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */

Definition at line 143 of file defBF54x_base.h.

#define SPORT1_MTCS2   0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */

Definition at line 144 of file defBF54x_base.h.

#define SPORT1_MTCS3   0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */

Definition at line 145 of file defBF54x_base.h.

#define SPORT1_RCLKDIV   0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */

Definition at line 136 of file defBF54x_base.h.

#define SPORT1_RCR1   0xffc00920 /* SPORT1 Receive Configuration 1 Register */

Definition at line 134 of file defBF54x_base.h.

#define SPORT1_RCR2   0xffc00924 /* SPORT1 Receive Configuration 2 Register */

Definition at line 135 of file defBF54x_base.h.

#define SPORT1_RFSDIV   0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */

Definition at line 137 of file defBF54x_base.h.

#define SPORT1_RX   0xffc00918 /* SPORT1 Receive Data Register */

Definition at line 133 of file defBF54x_base.h.

#define SPORT1_STAT   0xffc00930 /* SPORT1 Status Register */

Definition at line 138 of file defBF54x_base.h.

#define SPORT1_TCLKDIV   0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */

Definition at line 130 of file defBF54x_base.h.

#define SPORT1_TCR1   0xffc00900 /* SPORT1 Transmit Configuration 1 Register */

Definition at line 128 of file defBF54x_base.h.

#define SPORT1_TCR2   0xffc00904 /* SPORT1 Transmit Configuration 2 Register */

Definition at line 129 of file defBF54x_base.h.

#define SPORT1_TFSDIV   0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */

Definition at line 131 of file defBF54x_base.h.

#define SPORT1_TX   0xffc00910 /* SPORT1 Transmit Data Register */

Definition at line 132 of file defBF54x_base.h.

#define SPORT2_CHNL   0xffc02534 /* SPORT2 Current Channel Register */

Definition at line 986 of file defBF54x_base.h.

#define SPORT2_ERR   0x2000000 /* SPORT2 Error */

Definition at line 1538 of file defBF54x_base.h.

#define SPORT2_MCMC1   0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */

Definition at line 987 of file defBF54x_base.h.

#define SPORT2_MCMC2   0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */

Definition at line 988 of file defBF54x_base.h.

#define SPORT2_MRCS0   0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */

Definition at line 993 of file defBF54x_base.h.

#define SPORT2_MRCS1   0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */

Definition at line 994 of file defBF54x_base.h.

#define SPORT2_MRCS2   0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */

Definition at line 995 of file defBF54x_base.h.

#define SPORT2_MRCS3   0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */

Definition at line 996 of file defBF54x_base.h.

#define SPORT2_MTCS0   0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */

Definition at line 989 of file defBF54x_base.h.

#define SPORT2_MTCS1   0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */

Definition at line 990 of file defBF54x_base.h.

#define SPORT2_MTCS2   0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */

Definition at line 991 of file defBF54x_base.h.

#define SPORT2_MTCS3   0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */

Definition at line 992 of file defBF54x_base.h.

#define SPORT2_RCLKDIV   0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */

Definition at line 983 of file defBF54x_base.h.

#define SPORT2_RCR1   0xffc02520 /* SPORT2 Receive Configuration 1 Register */

Definition at line 981 of file defBF54x_base.h.

#define SPORT2_RCR2   0xffc02524 /* SPORT2 Receive Configuration 2 Register */

Definition at line 982 of file defBF54x_base.h.

#define SPORT2_RFSDIV   0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */

Definition at line 984 of file defBF54x_base.h.

#define SPORT2_RX   0xffc02518 /* SPORT2 Receive Data Register */

Definition at line 980 of file defBF54x_base.h.

#define SPORT2_STAT   0xffc02530 /* SPORT2 Status Register */

Definition at line 985 of file defBF54x_base.h.

#define SPORT2_TCLKDIV   0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */

Definition at line 977 of file defBF54x_base.h.

#define SPORT2_TCR1   0xffc02500 /* SPORT2 Transmit Configuration 1 Register */

Definition at line 975 of file defBF54x_base.h.

#define SPORT2_TCR2   0xffc02504 /* SPORT2 Transmit Configuration 2 Register */

Definition at line 976 of file defBF54x_base.h.

#define SPORT2_TFSDIV   0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */

Definition at line 978 of file defBF54x_base.h.

#define SPORT2_TX   0xffc02510 /* SPORT2 Transmit Data Register */

Definition at line 979 of file defBF54x_base.h.

#define SPORT3_CHNL   0xffc02634 /* SPORT3 Current Channel Register */

Definition at line 1011 of file defBF54x_base.h.

#define SPORT3_ERR   0x4000000 /* SPORT3 Error */

Definition at line 1539 of file defBF54x_base.h.

#define SPORT3_MCMC1   0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */

Definition at line 1012 of file defBF54x_base.h.

#define SPORT3_MCMC2   0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */

Definition at line 1013 of file defBF54x_base.h.

#define SPORT3_MRCS0   0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */

Definition at line 1018 of file defBF54x_base.h.

#define SPORT3_MRCS1   0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */

Definition at line 1019 of file defBF54x_base.h.

#define SPORT3_MRCS2   0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */

Definition at line 1020 of file defBF54x_base.h.

#define SPORT3_MRCS3   0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */

Definition at line 1021 of file defBF54x_base.h.

#define SPORT3_MTCS0   0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */

Definition at line 1014 of file defBF54x_base.h.

#define SPORT3_MTCS1   0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */

Definition at line 1015 of file defBF54x_base.h.

#define SPORT3_MTCS2   0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */

Definition at line 1016 of file defBF54x_base.h.

#define SPORT3_MTCS3   0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */

Definition at line 1017 of file defBF54x_base.h.

#define SPORT3_RCLKDIV   0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */

Definition at line 1008 of file defBF54x_base.h.

#define SPORT3_RCR1   0xffc02620 /* SPORT3 Receive Configuration 1 Register */

Definition at line 1006 of file defBF54x_base.h.

#define SPORT3_RCR2   0xffc02624 /* SPORT3 Receive Configuration 2 Register */

Definition at line 1007 of file defBF54x_base.h.

#define SPORT3_RFSDIV   0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */

Definition at line 1009 of file defBF54x_base.h.

#define SPORT3_RX   0xffc02618 /* SPORT3 Receive Data Register */

Definition at line 1005 of file defBF54x_base.h.

#define SPORT3_STAT   0xffc02630 /* SPORT3 Status Register */

Definition at line 1010 of file defBF54x_base.h.

#define SPORT3_TCLKDIV   0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */

Definition at line 1002 of file defBF54x_base.h.

#define SPORT3_TCR1   0xffc02600 /* SPORT3 Transmit Configuration 1 Register */

Definition at line 1000 of file defBF54x_base.h.

#define SPORT3_TCR2   0xffc02604 /* SPORT3 Transmit Configuration 2 Register */

Definition at line 1001 of file defBF54x_base.h.

#define SPORT3_TFSDIV   0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */

Definition at line 1003 of file defBF54x_base.h.

#define SPORT3_TX   0xffc02610 /* SPORT3 Transmit Data Register */

Definition at line 1004 of file defBF54x_base.h.

#define SRACK   0x10 /* Self-refresh acknowledge */

Definition at line 1786 of file defBF54x_base.h.

#define SRREQ   0x8 /* Self-refresh request */

Definition at line 1785 of file defBF54x_base.h.

#define SUBSPLT_ODD   0x1000000 /* Sub-split Odd Samples */

Definition at line 2031 of file defBF54x_base.h.

#define SWAPEN   0x200000 /* Swap Enable */

Definition at line 2028 of file defBF54x_base.h.

#define SWRST   0xffc00100 /* Software Reset Register */

Definition at line 33 of file defBF54x_base.h.

#define SYSCR   0xffc00104 /* System Configuration register */

Definition at line 34 of file defBF54x_base.h.

#define SYSTEM_RESET   0x0007 /* Initiates A System Software Reset */

Definition at line 1991 of file defBF54x_base.h.

#define TESTSETLOCK   0x1 /* Test set lock */

Definition at line 1696 of file defBF54x_base.h.

#define TIMDIS0   0x1 /* Timer 0 Disable */

Definition at line 1926 of file defBF54x_base.h.

#define TIMDIS1   0x2 /* Timer 1 Disable */

Definition at line 1927 of file defBF54x_base.h.

#define TIMDIS2   0x4 /* Timer 2 Disable */

Definition at line 1928 of file defBF54x_base.h.

#define TIMDIS3   0x8 /* Timer 3 Disable */

Definition at line 1929 of file defBF54x_base.h.

#define TIMDIS4   0x10 /* Timer 4 Disable */

Definition at line 1930 of file defBF54x_base.h.

#define TIMDIS5   0x20 /* Timer 5 Disable */

Definition at line 1931 of file defBF54x_base.h.

#define TIMDIS6   0x40 /* Timer 6 Disable */

Definition at line 1932 of file defBF54x_base.h.

#define TIMDIS7   0x80 /* Timer 7 Disable */

Definition at line 1933 of file defBF54x_base.h.

#define TIMEN0   0x1 /* Timer 0 Enable */

Definition at line 1915 of file defBF54x_base.h.

#define TIMEN1   0x2 /* Timer 1 Enable */

Definition at line 1916 of file defBF54x_base.h.

#define TIMEN2   0x4 /* Timer 2 Enable */

Definition at line 1917 of file defBF54x_base.h.

#define TIMEN3   0x8 /* Timer 3 Enable */

Definition at line 1918 of file defBF54x_base.h.

#define TIMEN4   0x10 /* Timer 4 Enable */

Definition at line 1919 of file defBF54x_base.h.

#define TIMEN5   0x20 /* Timer 5 Enable */

Definition at line 1920 of file defBF54x_base.h.

#define TIMEN6   0x40 /* Timer 6 Enable */

Definition at line 1921 of file defBF54x_base.h.

#define TIMEN7   0x80 /* Timer 7 Enable */

Definition at line 1922 of file defBF54x_base.h.

#define TIMER0   0x400000 /* Timer 0 */

Definition at line 1602 of file defBF54x_base.h.

#define TIMER0_CONFIG   0xffc01600 /* Timer 0 Configuration Register */

Definition at line 651 of file defBF54x_base.h.

#define TIMER0_COUNTER   0xffc01604 /* Timer 0 Counter Register */

Definition at line 652 of file defBF54x_base.h.

#define TIMER0_PERIOD   0xffc01608 /* Timer 0 Period Register */

Definition at line 653 of file defBF54x_base.h.

#define TIMER0_WIDTH   0xffc0160c /* Timer 0 Width Register */

Definition at line 654 of file defBF54x_base.h.

#define TIMER1   0x800000 /* Timer 1 */

Definition at line 1603 of file defBF54x_base.h.

#define TIMER1_CONFIG   0xffc01610 /* Timer 1 Configuration Register */

Definition at line 655 of file defBF54x_base.h.

#define TIMER1_COUNTER   0xffc01614 /* Timer 1 Counter Register */

Definition at line 656 of file defBF54x_base.h.

#define TIMER1_PERIOD   0xffc01618 /* Timer 1 Period Register */

Definition at line 657 of file defBF54x_base.h.

#define TIMER1_WIDTH   0xffc0161c /* Timer 1 Width Register */

Definition at line 658 of file defBF54x_base.h.

#define TIMER2   0x1000000 /* Timer 2 */

Definition at line 1604 of file defBF54x_base.h.

#define TIMER2_CONFIG   0xffc01620 /* Timer 2 Configuration Register */

Definition at line 659 of file defBF54x_base.h.

#define TIMER2_COUNTER   0xffc01624 /* Timer 2 Counter Register */

Definition at line 660 of file defBF54x_base.h.

#define TIMER2_PERIOD   0xffc01628 /* Timer 2 Period Register */

Definition at line 661 of file defBF54x_base.h.

#define TIMER2_WIDTH   0xffc0162c /* Timer 2 Width Register */

Definition at line 662 of file defBF54x_base.h.

#define TIMER3   0x2000000 /* Timer 3 */

Definition at line 1605 of file defBF54x_base.h.

#define TIMER3_CONFIG   0xffc01630 /* Timer 3 Configuration Register */

Definition at line 663 of file defBF54x_base.h.

#define TIMER3_COUNTER   0xffc01634 /* Timer 3 Counter Register */

Definition at line 664 of file defBF54x_base.h.

#define TIMER3_PERIOD   0xffc01638 /* Timer 3 Period Register */

Definition at line 665 of file defBF54x_base.h.

#define TIMER3_WIDTH   0xffc0163c /* Timer 3 Width Register */

Definition at line 666 of file defBF54x_base.h.

#define TIMER4   0x4000000 /* Timer 4 */

Definition at line 1606 of file defBF54x_base.h.

#define TIMER4_CONFIG   0xffc01640 /* Timer 4 Configuration Register */

Definition at line 667 of file defBF54x_base.h.

#define TIMER4_COUNTER   0xffc01644 /* Timer 4 Counter Register */

Definition at line 668 of file defBF54x_base.h.

#define TIMER4_PERIOD   0xffc01648 /* Timer 4 Period Register */

Definition at line 669 of file defBF54x_base.h.

#define TIMER4_WIDTH   0xffc0164c /* Timer 4 Width Register */

Definition at line 670 of file defBF54x_base.h.

#define TIMER5   0x8000000 /* Timer 5 */

Definition at line 1607 of file defBF54x_base.h.

#define TIMER5_CONFIG   0xffc01650 /* Timer 5 Configuration Register */

Definition at line 671 of file defBF54x_base.h.

#define TIMER5_COUNTER   0xffc01654 /* Timer 5 Counter Register */

Definition at line 672 of file defBF54x_base.h.

#define TIMER5_PERIOD   0xffc01658 /* Timer 5 Period Register */

Definition at line 673 of file defBF54x_base.h.

#define TIMER5_WIDTH   0xffc0165c /* Timer 5 Width Register */

Definition at line 674 of file defBF54x_base.h.

#define TIMER6   0x10000000 /* Timer 6 */

Definition at line 1608 of file defBF54x_base.h.

#define TIMER6_CONFIG   0xffc01660 /* Timer 6 Configuration Register */

Definition at line 675 of file defBF54x_base.h.

#define TIMER6_COUNTER   0xffc01664 /* Timer 6 Counter Register */

Definition at line 676 of file defBF54x_base.h.

#define TIMER6_PERIOD   0xffc01668 /* Timer 6 Period Register */

Definition at line 677 of file defBF54x_base.h.

#define TIMER6_WIDTH   0xffc0166c /* Timer 6 Width Register */

Definition at line 678 of file defBF54x_base.h.

#define TIMER7   0x20000000 /* Timer 7 */

Definition at line 1609 of file defBF54x_base.h.

#define TIMER7_CONFIG   0xffc01670 /* Timer 7 Configuration Register */

Definition at line 679 of file defBF54x_base.h.

#define TIMER7_COUNTER   0xffc01674 /* Timer 7 Counter Register */

Definition at line 680 of file defBF54x_base.h.

#define TIMER7_PERIOD   0xffc01678 /* Timer 7 Period Register */

Definition at line 681 of file defBF54x_base.h.

#define TIMER7_WIDTH   0xffc0167c /* Timer 7 Width Register */

Definition at line 682 of file defBF54x_base.h.

#define TIMER_DISABLE0   0xffc01684 /* Timer Group of 8 Disable Register */

Definition at line 687 of file defBF54x_base.h.

#define TIMER_ENABLE0   0xffc01680 /* Timer Group of 8 Enable Register */

Definition at line 686 of file defBF54x_base.h.

#define TIMER_STATUS0   0xffc01688 /* Timer Group of 8 Status Register */

Definition at line 688 of file defBF54x_base.h.

#define TIMIL0   0x1 /* Timer 0 Interrupt */

Definition at line 1937 of file defBF54x_base.h.

#define TIMIL1   0x2 /* Timer 1 Interrupt */

Definition at line 1938 of file defBF54x_base.h.

#define TIMIL2   0x4 /* Timer 2 Interrupt */

Definition at line 1939 of file defBF54x_base.h.

#define TIMIL3   0x8 /* Timer 3 Interrupt */

Definition at line 1940 of file defBF54x_base.h.

#define TIMIL4   0x10000 /* Timer 4 Interrupt */

Definition at line 1949 of file defBF54x_base.h.

#define TIMIL5   0x20000 /* Timer 5 Interrupt */

Definition at line 1950 of file defBF54x_base.h.

#define TIMIL6   0x40000 /* Timer 6 Interrupt */

Definition at line 1951 of file defBF54x_base.h.

#define TIMIL7   0x80000 /* Timer 7 Interrupt */

Definition at line 1952 of file defBF54x_base.h.

#define TIN_SEL   0x20 /* Timer Input Select */

Definition at line 1906 of file defBF54x_base.h.

#define TMODE   0x3 /* Timer Mode */

Definition at line 1902 of file defBF54x_base.h.

#define TMRD   0xf0 /* Mode register set to active */

Definition at line 1723 of file defBF54x_base.h.

#define TOGGLE_HI   0x100 /* Toggle Mode */

Definition at line 1909 of file defBF54x_base.h.

#define TOVF_ERR0   0x10 /* Timer 0 Counter Overflow */

Definition at line 1941 of file defBF54x_base.h.

#define TOVF_ERR1   0x20 /* Timer 1 Counter Overflow */

Definition at line 1942 of file defBF54x_base.h.

#define TOVF_ERR2   0x40 /* Timer 2 Counter Overflow */

Definition at line 1943 of file defBF54x_base.h.

#define TOVF_ERR3   0x80 /* Timer 3 Counter Overflow */

Definition at line 1944 of file defBF54x_base.h.

#define TOVF_ERR4   0x100000 /* Timer 4 Counter Overflow */

Definition at line 1953 of file defBF54x_base.h.

#define TOVF_ERR5   0x200000 /* Timer 5 Counter Overflow */

Definition at line 1954 of file defBF54x_base.h.

#define TOVF_ERR6   0x400000 /* Timer 6 Counter Overflow */

Definition at line 1955 of file defBF54x_base.h.

#define TOVF_ERR7   0x800000 /* Timer 7 Counter Overflow */

Definition at line 1956 of file defBF54x_base.h.

#define TRAS   0x3c00000 /* Min Active-to-pre charge time */

Definition at line 1712 of file defBF54x_base.h.

#define TRC   0x3c000000 /* Active-to-active time */

Definition at line 1713 of file defBF54x_base.h.

#define TRCD   0xf /* Active-to-Read/write delay */

Definition at line 1722 of file defBF54x_base.h.

#define TREFI   0x3fff /* Refresh Interval */

Definition at line 1709 of file defBF54x_base.h.

#define TRFC   0x3c000 /* Auto-refresh command period */

Definition at line 1710 of file defBF54x_base.h.

#define TRP   0x3c0000 /* Pre charge-to-active command period */

Definition at line 1711 of file defBF54x_base.h.

#define TRUN0   0x1000 /* Timer 0 Slave Enable Status */

Definition at line 1945 of file defBF54x_base.h.

#define TRUN1   0x2000 /* Timer 1 Slave Enable Status */

Definition at line 1946 of file defBF54x_base.h.

#define TRUN2   0x4000 /* Timer 2 Slave Enable Status */

Definition at line 1947 of file defBF54x_base.h.

#define TRUN3   0x8000 /* Timer 3 Slave Enable Status */

Definition at line 1948 of file defBF54x_base.h.

#define TRUN4   0x10000000 /* Timer 4 Slave Enable Status */

Definition at line 1957 of file defBF54x_base.h.

#define TRUN5   0x20000000 /* Timer 5 Slave Enable Status */

Definition at line 1958 of file defBF54x_base.h.

#define TRUN6   0x40000000 /* Timer 6 Slave Enable Status */

Definition at line 1959 of file defBF54x_base.h.

#define TRUN7   0x80000000 /* Timer 7 Slave Enable Status */

Definition at line 1960 of file defBF54x_base.h.

#define TWI0   0x2000 /* TWI0 */

Definition at line 1561 of file defBF54x_base.h.

#define TWI0_CLKDIV   0xffc00700 /* Clock Divider Register */

Definition at line 107 of file defBF54x_base.h.

#define TWI0_CONTROL   0xffc00704 /* TWI Control Register */

Definition at line 108 of file defBF54x_base.h.

#define TWI0_FIFO_CTL   0xffc00728 /* TWI FIFO Control Register */

Definition at line 117 of file defBF54x_base.h.

#define TWI0_FIFO_STAT   0xffc0072c /* TWI FIFO Status Register */

Definition at line 118 of file defBF54x_base.h.

#define TWI0_INT_MASK   0xffc00724 /* TWI Interrupt Mask Register */

Definition at line 116 of file defBF54x_base.h.

#define TWI0_INT_STAT   0xffc00720 /* TWI Interrupt Status Register */

Definition at line 115 of file defBF54x_base.h.

#define TWI0_MASTER_ADDR   0xffc0071c /* TWI Master Mode Address Register */

Definition at line 114 of file defBF54x_base.h.

#define TWI0_MASTER_CTL   0xffc00714 /* TWI Master Mode Control Register */

Definition at line 112 of file defBF54x_base.h.

#define TWI0_MASTER_STAT   0xffc00718 /* TWI Master Mode Status Register */

Definition at line 113 of file defBF54x_base.h.

#define TWI0_RCV_DATA16   0xffc0078c /* TWI FIFO Receive Data Double Byte Register */

Definition at line 122 of file defBF54x_base.h.

#define TWI0_RCV_DATA8   0xffc00788 /* TWI FIFO Receive Data Single Byte Register */

Definition at line 121 of file defBF54x_base.h.

#define TWI0_REGBASE   0xffc00700

Definition at line 106 of file defBF54x_base.h.

#define TWI0_SLAVE_ADDR   0xffc00710 /* TWI Slave Mode Address Register */

Definition at line 111 of file defBF54x_base.h.

#define TWI0_SLAVE_CTL   0xffc00708 /* TWI Slave Mode Control Register */

Definition at line 109 of file defBF54x_base.h.

#define TWI0_SLAVE_STAT   0xffc0070c /* TWI Slave Mode Status Register */

Definition at line 110 of file defBF54x_base.h.

#define TWI0_XMT_DATA16   0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */

Definition at line 120 of file defBF54x_base.h.

#define TWI0_XMT_DATA8   0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */

Definition at line 119 of file defBF54x_base.h.

#define TWI1   0x4000 /* TWI1 */

Definition at line 1562 of file defBF54x_base.h.

#define TWR   0x300 /* Write Recovery time */

Definition at line 1724 of file defBF54x_base.h.

#define TWTR   0xf0000000 /* Write-to-read delay */

Definition at line 1729 of file defBF54x_base.h.

#define UART0_DLH   0xffc00404 /* Divisor Latch High Byte */

Definition at line 79 of file defBF54x_base.h.

#define UART0_DLL   0xffc00400 /* Divisor Latch Low Byte */

Definition at line 78 of file defBF54x_base.h.

#define UART0_ERR   0x40 /* UART0 Error */

Definition at line 1522 of file defBF54x_base.h.

#define UART0_GCTL   0xffc00408 /* Global Control Register */

Definition at line 80 of file defBF54x_base.h.

#define UART0_IER_CLEAR   0xffc00424 /* Interrupt Enable Register Clear */

Definition at line 87 of file defBF54x_base.h.

#define UART0_IER_SET   0xffc00420 /* Interrupt Enable Register Set */

Definition at line 86 of file defBF54x_base.h.

#define UART0_LCR   0xffc0040c /* Line Control Register */

Definition at line 81 of file defBF54x_base.h.

#define UART0_LSR   0xffc00414 /* Line Status Register */

Definition at line 83 of file defBF54x_base.h.

#define UART0_MCR   0xffc00410 /* Modem Control Register */

Definition at line 82 of file defBF54x_base.h.

#define UART0_MSR   0xffc00418 /* Modem Status Register */

Definition at line 84 of file defBF54x_base.h.

#define UART0_RBR   0xffc0042c /* Receive Buffer Register */

Definition at line 89 of file defBF54x_base.h.

#define UART0_SCR   0xffc0041c /* Scratch Register */

Definition at line 85 of file defBF54x_base.h.

#define UART0_THR   0xffc00428 /* Transmit Hold Register */

Definition at line 88 of file defBF54x_base.h.

#define UART1_DLH   0xffc02004 /* Divisor Latch High Byte */

Definition at line 948 of file defBF54x_base.h.

#define UART1_DLL   0xffc02000 /* Divisor Latch Low Byte */

Definition at line 947 of file defBF54x_base.h.

#define UART1_ERR   0x40000000 /* UART1 Error */

Definition at line 1543 of file defBF54x_base.h.

#define UART1_GCTL   0xffc02008 /* Global Control Register */

Definition at line 949 of file defBF54x_base.h.

#define UART1_IER_CLEAR   0xffc02024 /* Interrupt Enable Register Clear */

Definition at line 956 of file defBF54x_base.h.

#define UART1_IER_SET   0xffc02020 /* Interrupt Enable Register Set */

Definition at line 955 of file defBF54x_base.h.

#define UART1_LCR   0xffc0200c /* Line Control Register */

Definition at line 950 of file defBF54x_base.h.

#define UART1_LSR   0xffc02014 /* Line Status Register */

Definition at line 952 of file defBF54x_base.h.

#define UART1_MCR   0xffc02010 /* Modem Control Register */

Definition at line 951 of file defBF54x_base.h.

#define UART1_MSR   0xffc02018 /* Modem Status Register */

Definition at line 953 of file defBF54x_base.h.

#define UART1_RBR   0xffc0202c /* Receive Buffer Register */

Definition at line 958 of file defBF54x_base.h.

#define UART1_SCR   0xffc0201c /* Scratch Register */

Definition at line 954 of file defBF54x_base.h.

#define UART1_THR   0xffc02028 /* Transmit Hold Register */

Definition at line 957 of file defBF54x_base.h.

#define UART2_ERR   0x80000000 /* UART2 Error */

Definition at line 1544 of file defBF54x_base.h.

#define UART3_DLH   0xffc03104 /* Divisor Latch High Byte */

Definition at line 1426 of file defBF54x_base.h.

#define UART3_DLH   0xffc03104 /* Divisor Latch High Byte */

Definition at line 1426 of file defBF54x_base.h.

#define UART3_DLL   0xffc03100 /* Divisor Latch Low Byte */

Definition at line 1425 of file defBF54x_base.h.

#define UART3_DLL   0xffc03100 /* Divisor Latch Low Byte */

Definition at line 1425 of file defBF54x_base.h.

#define UART3_ERR   0x1000000 /* UART3 Error */

Definition at line 1572 of file defBF54x_base.h.

#define UART3_GCTL   0xffc03108 /* Global Control Register */

Definition at line 1427 of file defBF54x_base.h.

#define UART3_GCTL   0xffc03108 /* Global Control Register */

Definition at line 1427 of file defBF54x_base.h.

#define UART3_IER_CLEAR   0xffc03124 /* Interrupt Enable Register Clear */

Definition at line 1434 of file defBF54x_base.h.

#define UART3_IER_CLEAR   0xffc03124 /* Interrupt Enable Register Clear */

Definition at line 1434 of file defBF54x_base.h.

#define UART3_IER_SET   0xffc03120 /* Interrupt Enable Register Set */

Definition at line 1433 of file defBF54x_base.h.

#define UART3_IER_SET   0xffc03120 /* Interrupt Enable Register Set */

Definition at line 1433 of file defBF54x_base.h.

#define UART3_LCR   0xffc0310c /* Line Control Register */

Definition at line 1428 of file defBF54x_base.h.

#define UART3_LCR   0xffc0310c /* Line Control Register */

Definition at line 1428 of file defBF54x_base.h.

#define UART3_LSR   0xffc03114 /* Line Status Register */

Definition at line 1430 of file defBF54x_base.h.

#define UART3_LSR   0xffc03114 /* Line Status Register */

Definition at line 1430 of file defBF54x_base.h.

#define UART3_MCR   0xffc03110 /* Modem Control Register */

Definition at line 1429 of file defBF54x_base.h.

#define UART3_MCR   0xffc03110 /* Modem Control Register */

Definition at line 1429 of file defBF54x_base.h.

#define UART3_MSR   0xffc03118 /* Modem Status Register */

Definition at line 1431 of file defBF54x_base.h.

#define UART3_MSR   0xffc03118 /* Modem Status Register */

Definition at line 1431 of file defBF54x_base.h.

#define UART3_RBR   0xffc0312c /* Receive Buffer Register */

Definition at line 1436 of file defBF54x_base.h.

#define UART3_RBR   0xffc0312c /* Receive Buffer Register */

Definition at line 1436 of file defBF54x_base.h.

#define UART3_SCR   0xffc0311c /* Scratch Register */

Definition at line 1432 of file defBF54x_base.h.

#define UART3_SCR   0xffc0311c /* Scratch Register */

Definition at line 1432 of file defBF54x_base.h.

#define UART3_THR   0xffc03128 /* Transmit Hold Register */

Definition at line 1435 of file defBF54x_base.h.

#define UART3_THR   0xffc03128 /* Transmit Hold Register */

Definition at line 1435 of file defBF54x_base.h.

#define USB_DMAINT   0x4000 /* USB DMA */

Definition at line 1600 of file defBF54x_base.h.

#define USB_EINT   0x400 /* USB Exception */

Definition at line 1596 of file defBF54x_base.h.

#define USB_ERR   0x4000000 /* USB Error */

Definition at line 1574 of file defBF54x_base.h.

#define USB_INT0   0x800 /* USB Interrupt 0 */

Definition at line 1597 of file defBF54x_base.h.

#define USB_INT1   0x1000 /* USB Interrupt 1 */

Definition at line 1598 of file defBF54x_base.h.

#define USB_INT2   0x2000 /* USB Interrupt 2 */

Definition at line 1599 of file defBF54x_base.h.

#define VR_CTL   0xffc00008 /* Voltage Regulator Control Register */

Definition at line 19 of file defBF54x_base.h.

#define WDOG   0x800000 /* Watchdog Timer */

Definition at line 1536 of file defBF54x_base.h.

#define WDOG_CNT   0xffc00204 /* Watchdog Count Register */

Definition at line 64 of file defBF54x_base.h.

#define WDOG_CTL   0xffc00200 /* Watchdog Control Register */

Definition at line 63 of file defBF54x_base.h.

#define WDOG_STAT   0xffc00208 /* Watchdog Status Register */

Definition at line 65 of file defBF54x_base.h.

#define WDTH_CAP   0x0002

Definition at line 2080 of file defBF54x_base.h.

#define XFR_TYPE   0xc /* Operating Mode */

Definition at line 2015 of file defBF54x_base.h.

#define YFIFO_ERR   0x2 /* Luma FIFO Error */

Definition at line 2000 of file defBF54x_base.h.