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devices-qsd8x50.c
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1 /*
2  * Copyright (C) 2008 Google, Inc.
3  * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4  *
5  * This software is licensed under the terms of the GNU General Public
6  * License version 2, as published by the Free Software Foundation, and
7  * may be copied, distributed, and modified under those terms.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12  * GNU General Public License for more details.
13  *
14  */
15 
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clkdev.h>
19 #include <linux/dma-mapping.h>
20 
21 #include <mach/irqs.h>
22 #include <mach/msm_iomap.h>
23 #include <mach/dma.h>
24 #include <mach/board.h>
25 
26 #include "devices.h"
27 
28 #include <asm/mach/flash.h>
29 
30 #include <linux/platform_data/mmc-msm_sdcc.h>
31 #include "clock-pcom.h"
32 
33 static struct resource resources_uart3[] = {
34  {
35  .start = INT_UART3,
36  .end = INT_UART3,
37  .flags = IORESOURCE_IRQ,
38  },
39  {
40  .start = MSM_UART3_PHYS,
41  .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
42  .flags = IORESOURCE_MEM,
43  .name = "uart_resource"
44  },
45 };
46 
47 struct platform_device msm_device_uart3 = {
48  .name = "msm_serial",
49  .id = 2,
50  .num_resources = ARRAY_SIZE(resources_uart3),
51  .resource = resources_uart3,
52 };
53 
54 struct platform_device msm_device_smd = {
55  .name = "msm_smd",
56  .id = -1,
57 };
58 
59 static struct resource resources_otg[] = {
60  {
61  .start = MSM_HSUSB_PHYS,
62  .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
63  .flags = IORESOURCE_MEM,
64  },
65  {
66  .start = INT_USB_HS,
67  .end = INT_USB_HS,
68  .flags = IORESOURCE_IRQ,
69  },
70 };
71 
72 struct platform_device msm_device_otg = {
73  .name = "msm_otg",
74  .id = -1,
75  .num_resources = ARRAY_SIZE(resources_otg),
76  .resource = resources_otg,
77  .dev = {
78  .coherent_dma_mask = 0xffffffff,
79  },
80 };
81 
82 static struct resource resources_hsusb[] = {
83  {
84  .start = MSM_HSUSB_PHYS,
85  .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
86  .flags = IORESOURCE_MEM,
87  },
88  {
89  .start = INT_USB_HS,
90  .end = INT_USB_HS,
91  .flags = IORESOURCE_IRQ,
92  },
93 };
94 
95 struct platform_device msm_device_hsusb = {
96  .name = "msm_hsusb",
97  .id = -1,
98  .num_resources = ARRAY_SIZE(resources_hsusb),
99  .resource = resources_hsusb,
100  .dev = {
101  .coherent_dma_mask = 0xffffffff,
102  },
103 };
104 
105 static u64 dma_mask = 0xffffffffULL;
106 static struct resource resources_hsusb_host[] = {
107  {
108  .start = MSM_HSUSB_PHYS,
109  .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
110  .flags = IORESOURCE_MEM,
111  },
112  {
113  .start = INT_USB_HS,
114  .end = INT_USB_HS,
115  .flags = IORESOURCE_IRQ,
116  },
117 };
118 
119 struct platform_device msm_device_hsusb_host = {
120  .name = "msm_hsusb_host",
121  .id = -1,
122  .num_resources = ARRAY_SIZE(resources_hsusb_host),
123  .resource = resources_hsusb_host,
124  .dev = {
125  .dma_mask = &dma_mask,
126  .coherent_dma_mask = 0xffffffffULL,
127  },
128 };
129 
130 static struct resource resources_sdc1[] = {
131  {
132  .start = MSM_SDC1_PHYS,
133  .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
134  .flags = IORESOURCE_MEM,
135  },
136  {
137  .start = INT_SDC1_0,
138  .end = INT_SDC1_0,
139  .flags = IORESOURCE_IRQ,
140  .name = "cmd_irq",
141  },
142  {
143  .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
144  .name = "status_irq"
145  },
146  {
147  .start = 8,
148  .end = 8,
149  .flags = IORESOURCE_DMA,
150  },
151 };
152 
153 static struct resource resources_sdc2[] = {
154  {
155  .start = MSM_SDC2_PHYS,
156  .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
157  .flags = IORESOURCE_MEM,
158  },
159  {
160  .start = INT_SDC2_0,
161  .end = INT_SDC2_0,
162  .flags = IORESOURCE_IRQ,
163  .name = "cmd_irq",
164  },
165  {
166  .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
167  .name = "status_irq"
168  },
169  {
170  .start = 8,
171  .end = 8,
172  .flags = IORESOURCE_DMA,
173  },
174 };
175 
176 static struct resource resources_sdc3[] = {
177  {
178  .start = MSM_SDC3_PHYS,
179  .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
180  .flags = IORESOURCE_MEM,
181  },
182  {
183  .start = INT_SDC3_0,
184  .end = INT_SDC3_0,
185  .flags = IORESOURCE_IRQ,
186  .name = "cmd_irq",
187  },
188  {
189  .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
190  .name = "status_irq"
191  },
192  {
193  .start = 8,
194  .end = 8,
195  .flags = IORESOURCE_DMA,
196  },
197 };
198 
199 static struct resource resources_sdc4[] = {
200  {
201  .start = MSM_SDC4_PHYS,
202  .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
203  .flags = IORESOURCE_MEM,
204  },
205  {
206  .start = INT_SDC4_0,
207  .end = INT_SDC4_0,
208  .flags = IORESOURCE_IRQ,
209  .name = "cmd_irq",
210  },
211  {
212  .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
213  .name = "status_irq"
214  },
215  {
216  .start = 8,
217  .end = 8,
218  .flags = IORESOURCE_DMA,
219  },
220 };
221 
222 struct platform_device msm_device_sdc1 = {
223  .name = "msm_sdcc",
224  .id = 1,
225  .num_resources = ARRAY_SIZE(resources_sdc1),
226  .resource = resources_sdc1,
227  .dev = {
228  .coherent_dma_mask = 0xffffffff,
229  },
230 };
231 
232 struct platform_device msm_device_sdc2 = {
233  .name = "msm_sdcc",
234  .id = 2,
235  .num_resources = ARRAY_SIZE(resources_sdc2),
236  .resource = resources_sdc2,
237  .dev = {
238  .coherent_dma_mask = 0xffffffff,
239  },
240 };
241 
242 struct platform_device msm_device_sdc3 = {
243  .name = "msm_sdcc",
244  .id = 3,
245  .num_resources = ARRAY_SIZE(resources_sdc3),
246  .resource = resources_sdc3,
247  .dev = {
248  .coherent_dma_mask = 0xffffffff,
249  },
250 };
251 
252 struct platform_device msm_device_sdc4 = {
253  .name = "msm_sdcc",
254  .id = 4,
255  .num_resources = ARRAY_SIZE(resources_sdc4),
256  .resource = resources_sdc4,
257  .dev = {
258  .coherent_dma_mask = 0xffffffff,
259  },
260 };
261 
262 static struct platform_device *msm_sdcc_devices[] __initdata = {
263  &msm_device_sdc1,
264  &msm_device_sdc2,
265  &msm_device_sdc3,
266  &msm_device_sdc4,
267 };
268 
269 int __init msm_add_sdcc(unsigned int controller,
270  struct msm_mmc_platform_data *plat,
271  unsigned int stat_irq, unsigned long stat_irq_flags)
272 {
273  struct platform_device *pdev;
274  struct resource *res;
275 
276  if (controller < 1 || controller > 4)
277  return -EINVAL;
278 
279  pdev = msm_sdcc_devices[controller-1];
280  pdev->dev.platform_data = plat;
281 
282  res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
283  if (!res)
284  return -EINVAL;
285  else if (stat_irq) {
286  res->start = res->end = stat_irq;
287  res->flags &= ~IORESOURCE_DISABLED;
288  res->flags |= stat_irq_flags;
289  }
290 
291  return platform_device_register(pdev);
292 }
293 
294 struct clk_lookup msm_clocks_8x50[] = {
295  CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
296  CLK_PCOM("ce_clk", CE_CLK, NULL, 0),
297  CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
298  CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0),
299  CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0),
300  CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX),
301  CLK_PCOM("gp_clk", GP_CLK, NULL, 0),
302  CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0),
303  CLK_PCOM("i2c_clk", I2C_CLK, NULL, 0),
304  CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0),
305  CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0),
306  CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
307  CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0),
308  CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
309  CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
310  CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
311  CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
312  CLK_PCOM("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, 0),
313  CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN),
314  CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
315  CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
316  CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF),
317  CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF),
318  CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF),
319  CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF),
320  CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF),
321  CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF),
322  CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF),
323  CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF),
324  CLK_PCOM("spi_clk", SPI_CLK, NULL, 0),
325  CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0),
326  CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),
327  CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
328  CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
329  CLK_PCOM("uart_clk", UART1_CLK, NULL, OFF),
330  CLK_PCOM("uart_clk", UART2_CLK, NULL, 0),
331  CLK_PCOM("uart_clk", UART3_CLK, "msm_serial.2", OFF),
332  CLK_PCOM("uartdm_clk", UART1DM_CLK, NULL, OFF),
333  CLK_PCOM("uartdm_clk", UART2DM_CLK, NULL, 0),
334  CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF),
335  CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF),
336  CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0),
337  CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF | CLK_MIN),
338  CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF),
339  CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF),
340  CLK_PCOM("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
341  CLK_PCOM("usb_hs2_clk", USB_HS2_CLK, NULL, OFF),
342  CLK_PCOM("usb_hs2_pclk", USB_HS2_P_CLK, NULL, OFF),
343  CLK_PCOM("usb_hs3_clk", USB_HS3_CLK, NULL, OFF),
344  CLK_PCOM("usb_hs3_pclk", USB_HS3_P_CLK, NULL, OFF),
345  CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0),
346 };
347 
348 unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);
349 
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