|
| enum | {
EDSR = 0,
EDMR,
EDTRR,
EDRRR,
EESR,
EESIPR,
TDLAR,
TDFAR,
TDFXR,
TDFFR,
RDLAR,
RDFAR,
RDFXR,
RDFFR,
TRSCER,
RMFCR,
TFTR,
FDR,
RMCR,
EDOCR,
TFUCR,
RFOCR,
FCFTR,
RPADIR,
TRIMD,
RBWAR,
TBRAR,
ECMR,
ECSR,
ECSIPR,
PIR,
PSR,
RDMLR,
PIPR,
RFLR,
IPGR,
APR,
MPR,
PFTCR,
PFRCR,
RFCR,
RFCF,
TPAUSER,
TPAUSECR,
BCFR,
BCFRR,
GECMR,
BCULR,
MAHR,
MALR,
TROCR,
CDCR,
LCCR,
CNDCR,
CEFCR,
FRECR,
TSFRCR,
TLFRCR,
CERCR,
CEECR,
MAFCR,
RTRATE,
CSMR,
RMII_MII,
ARSTR,
TSU_CTRST,
TSU_FWEN0,
TSU_FWEN1,
TSU_FCM,
TSU_BSYSL0,
TSU_BSYSL1,
TSU_PRISL0,
TSU_PRISL1,
TSU_FWSL0,
TSU_FWSL1,
TSU_FWSLC,
TSU_QTAG0,
TSU_QTAG1,
TSU_QTAGM0,
TSU_QTAGM1,
TSU_FWSR,
TSU_FWINMK,
TSU_ADQT0,
TSU_ADQT1,
TSU_VTAG0,
TSU_VTAG1,
TSU_ADSBSY,
TSU_TEN,
TSU_POST1,
TSU_POST2,
TSU_POST3,
TSU_POST4,
TSU_ADRH0,
TSU_ADRL0,
TSU_ADRH31,
TSU_ADRL31,
TXNLCR0,
TXALCR0,
RXNLCR0,
RXALCR0,
FWNLCR0,
FWALCR0,
TXNLCR1,
TXALCR1,
RXNLCR1,
RXALCR1,
FWNLCR1,
FWALCR1,
SH_ETH_MAX_REGISTER_OFFSET
} |
| |
| enum | DMAC_M_BIT {
EDMR_EL = 0x40,
EDMR_DL1 = 0x20,
EDMR_DL0 = 0x10,
EDMR_SRST_GETHER = 0x03,
EDMR_SRST_ETHER = 0x01
} |
| |
| enum | DMAC_T_BIT { EDTRR_TRNS_GETHER = 0x03,
EDTRR_TRNS_ETHER = 0x01
} |
| |
| enum | EDRRR_R_BIT { EDRRR_R = 0x01
} |
| |
| enum | TPAUSER_BIT { TPAUSER_TPAUSE = 0x0000ffff,
TPAUSER_UNLIMITED = 0
} |
| |
| enum | BCFR_BIT { BCFR_RPAUSE = 0x0000ffff,
BCFR_UNLIMITED = 0
} |
| |
| enum | PIR_BIT { PIR_MDI = 0x08,
PIR_MDO = 0x04,
PIR_MMD = 0x02,
PIR_MDC = 0x01
} |
| |
| enum | PHY_STATUS_BIT { PHY_ST_LINK = 0x01
} |
| |
| enum | EESR_BIT {
EESR_TWB1 = 0x80000000,
EESR_TWB = 0x40000000,
EESR_TC1 = 0x20000000,
EESR_TUC = 0x10000000,
EESR_ROC = 0x08000000,
EESR_TABT = 0x04000000,
EESR_RABT = 0x02000000,
EESR_RFRMER = 0x01000000,
EESR_ADE = 0x00800000,
EESR_ECI = 0x00400000,
EESR_FTC = 0x00200000,
EESR_TDE = 0x00100000,
EESR_TFE = 0x00080000,
EESR_FRC = 0x00040000,
EESR_RDE = 0x00020000,
EESR_RFE = 0x00010000,
EESR_CND = 0x00000800,
EESR_DLC = 0x00000400,
EESR_CD = 0x00000200,
EESR_RTO = 0x00000100,
EESR_RMAF = 0x00000080,
EESR_CEEF = 0x00000040,
EESR_CELF = 0x00000020,
EESR_RRF = 0x00000010,
EESR_RTLF = 0x00000008,
EESR_RTSF = 0x00000004,
EESR_PRE = 0x00000002,
EESR_CERF = 0x00000001
} |
| |
| enum | DMAC_IM_BIT {
DMAC_M_TWB = 0x40000000,
DMAC_M_TABT = 0x04000000,
DMAC_M_RABT = 0x02000000,
DMAC_M_RFRMER = 0x01000000,
DMAC_M_ADF = 0x00800000,
DMAC_M_ECI = 0x00400000,
DMAC_M_FTC = 0x00200000,
DMAC_M_TDE = 0x00100000,
DMAC_M_TFE = 0x00080000,
DMAC_M_FRC = 0x00040000,
DMAC_M_RDE = 0x00020000,
DMAC_M_RFE = 0x00010000,
DMAC_M_TINT4 = 0x00000800,
DMAC_M_TINT3 = 0x00000400,
DMAC_M_TINT2 = 0x00000200,
DMAC_M_TINT1 = 0x00000100,
DMAC_M_RINT8 = 0x00000080,
DMAC_M_RINT5 = 0x00000010,
DMAC_M_RINT4 = 0x00000008,
DMAC_M_RINT3 = 0x00000004,
DMAC_M_RINT2 = 0x00000002,
DMAC_M_RINT1 = 0x00000001
} |
| |
| enum | RD_STS_BIT {
RD_RACT = 0x80000000,
RD_RDEL = 0x40000000,
RD_RFP1 = 0x20000000,
RD_RFP0 = 0x10000000,
RD_RFE = 0x08000000,
RD_RFS10 = 0x00000200,
RD_RFS9 = 0x00000100,
RD_RFS8 = 0x00000080,
RD_RFS7 = 0x00000040,
RD_RFS6 = 0x00000020,
RD_RFS5 = 0x00000010,
RD_RFS4 = 0x00000008,
RD_RFS3 = 0x00000004,
RD_RFS2 = 0x00000002,
RD_RFS1 = 0x00000001
} |
| |
| enum | FCFTR_BIT {
FCFTR_RFF2 = 0x00040000,
FCFTR_RFF1 = 0x00020000,
FCFTR_RFF0 = 0x00010000,
FCFTR_RFD2 = 0x00000004,
FCFTR_RFD1 = 0x00000002,
FCFTR_RFD0 = 0x00000001
} |
| |
| enum | TD_STS_BIT { TD_TACT = 0x80000000,
TD_TDLE = 0x40000000,
TD_TFP1 = 0x20000000,
TD_TFP0 = 0x10000000
} |
| |
| enum | FELIC_MODE_BIT {
ECMR_TRCCM = 0x04000000,
ECMR_RCSC = 0x00800000,
ECMR_DPAD = 0x00200000,
ECMR_RZPF = 0x00100000,
ECMR_ZPF = 0x00080000,
ECMR_PFR = 0x00040000,
ECMR_RXF = 0x00020000,
ECMR_TXF = 0x00010000,
ECMR_MCT = 0x00002000,
ECMR_PRCEF = 0x00001000,
ECMR_PMDE = 0x00000200,
ECMR_RE = 0x00000040,
ECMR_TE = 0x00000020,
ECMR_RTM = 0x00000010,
ECMR_ILB = 0x00000008,
ECMR_ELB = 0x00000004,
ECMR_DM = 0x00000002,
ECMR_PRM = 0x00000001
} |
| |
| enum | ECSR_STATUS_BIT {
ECSR_BRCRX = 0x20,
ECSR_PSRTO = 0x10,
ECSR_LCHNG = 0x04,
ECSR_MPD = 0x02,
ECSR_ICD = 0x01
} |
| |
| enum | ECSIPR_STATUS_MASK_BIT {
ECSIPR_BRCRXIP = 0x20,
ECSIPR_PSRTOIP = 0x10,
ECSIPR_LCHNGIP = 0x04,
ECSIPR_MPDIP = 0x02,
ECSIPR_ICDIP = 0x01
} |
| |
| enum | APR_BIT { APR_AP = 0x00000001
} |
| |
| enum | MPR_BIT { MPR_MP = 0x00000001
} |
| |
| enum | DESC_I_BIT {
DESC_I_TINT4 = 0x0800,
DESC_I_TINT3 = 0x0400,
DESC_I_TINT2 = 0x0200,
DESC_I_TINT1 = 0x0100,
DESC_I_RINT8 = 0x0080,
DESC_I_RINT5 = 0x0010,
DESC_I_RINT4 = 0x0008,
DESC_I_RINT3 = 0x0004,
DESC_I_RINT2 = 0x0002,
DESC_I_RINT1 = 0x0001
} |
| |
| enum | RPADIR_BIT { RPADIR_PADS1 = 0x20000,
RPADIR_PADS0 = 0x10000,
RPADIR_PADR = 0x0003f
} |
| |
| enum | ARSTR_BIT { ARSTR_ARSTR = 0x00000001
} |
| |
| enum | TSU_FWEN0_BIT { TSU_FWEN0_0 = 0x00000001
} |
| |
| enum | TSU_ADSBSY_BIT { TSU_ADSBSY_0 = 0x00000001
} |
| |
| enum | TSU_TEN_BIT { TSU_TEN_0 = 0x80000000
} |
| |
| enum | TSU_FWSL0_BIT {
TSU_FWSL0_FW50 = 0x1000,
TSU_FWSL0_FW40 = 0x0800,
TSU_FWSL0_FW30 = 0x0400,
TSU_FWSL0_FW20 = 0x0200,
TSU_FWSL0_FW10 = 0x0100,
TSU_FWSL0_RMSA0 = 0x0010
} |
| |
| enum | TSU_FWSLC_BIT {
TSU_FWSLC_POSTENU = 0x2000,
TSU_FWSLC_POSTENL = 0x1000,
TSU_FWSLC_CAMSEL03 = 0x0080,
TSU_FWSLC_CAMSEL02 = 0x0040,
TSU_FWSLC_CAMSEL01 = 0x0020,
TSU_FWSLC_CAMSEL00 = 0x0010,
TSU_FWSLC_CAMSEL13 = 0x0008,
TSU_FWSLC_CAMSEL12 = 0x0004,
TSU_FWSLC_CAMSEL11 = 0x0002,
TSU_FWSLC_CAMSEL10 = 0x0001
} |
| |
1.8.2