43 #if defined(CONFIG_ARCH_LUBBOCK) ||\
44 defined(CONFIG_MACH_MAINSTONE) ||\
45 defined(CONFIG_MACH_ZYLONITE) ||\
46 defined(CONFIG_MACH_LITTLETON) ||\
47 defined(CONFIG_MACH_ZYLONITE2) ||\
48 defined(CONFIG_ARCH_VIPER) ||\
49 defined(CONFIG_MACH_STARGATE2)
56 #define SMC_CAN_USE_8BIT 1
57 #define SMC_CAN_USE_16BIT 1
58 #define SMC_CAN_USE_32BIT 1
61 #define SMC_IO_SHIFT (lp->io_shift)
63 #define SMC_inb(a, r) readb((a) + (r))
64 #define SMC_inw(a, r) readw((a) + (r))
65 #define SMC_inl(a, r) readl((a) + (r))
66 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
67 #define SMC_outl(v, a, r) writel(v, (a) + (r))
68 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
69 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
70 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
71 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
72 #define SMC_IRQ_FLAGS (-1)
77 if ((machine_is_mainstone() || machine_is_stargate2()) && reg & 2) {
78 unsigned int v = val << 16;
79 v |=
readl(ioaddr + (reg & ~2)) & 0xffff;
80 writel(v, ioaddr + (reg & ~2));
86 #elif defined(CONFIG_SA1100_PLEB)
88 #define SMC_CAN_USE_8BIT 1
89 #define SMC_CAN_USE_16BIT 1
90 #define SMC_CAN_USE_32BIT 0
91 #define SMC_IO_SHIFT 0
94 #define SMC_inb(a, r) readb((a) + (r))
95 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
96 #define SMC_inw(a, r) readw((a) + (r))
97 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
98 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
99 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
100 #define SMC_outw(v, a, r) writew(v, (a) + (r))
101 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
103 #define SMC_IRQ_FLAGS (-1)
105 #elif defined(CONFIG_SA1100_ASSABET)
110 #define SMC_CAN_USE_8BIT 1
111 #define SMC_CAN_USE_16BIT 0
112 #define SMC_CAN_USE_32BIT 0
116 #define SMC_IO_SHIFT 2
118 #define SMC_inb(a, r) readb((a) + (r))
119 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
120 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
121 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
122 #define SMC_IRQ_FLAGS (-1)
124 #elif defined(CONFIG_MACH_LOGICPD_PXA270) || \
125 defined(CONFIG_MACH_NOMADIK_8815NHK)
127 #define SMC_CAN_USE_8BIT 0
128 #define SMC_CAN_USE_16BIT 1
129 #define SMC_CAN_USE_32BIT 0
130 #define SMC_IO_SHIFT 0
133 #define SMC_inw(a, r) readw((a) + (r))
134 #define SMC_outw(v, a, r) writew(v, (a) + (r))
135 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
136 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
138 #elif defined(CONFIG_ARCH_INNOKOM) || \
139 defined(CONFIG_ARCH_PXA_IDP) || \
140 defined(CONFIG_ARCH_RAMSES) || \
141 defined(CONFIG_ARCH_PCM027)
143 #define SMC_CAN_USE_8BIT 1
144 #define SMC_CAN_USE_16BIT 1
145 #define SMC_CAN_USE_32BIT 1
146 #define SMC_IO_SHIFT 0
148 #define SMC_USE_PXA_DMA 1
150 #define SMC_inb(a, r) readb((a) + (r))
151 #define SMC_inw(a, r) readw((a) + (r))
152 #define SMC_inl(a, r) readl((a) + (r))
153 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
154 #define SMC_outl(v, a, r) writel(v, (a) + (r))
155 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
156 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
157 #define SMC_IRQ_FLAGS (-1)
164 unsigned int v = val << 16;
165 v |=
readl(ioaddr + (reg & ~2)) & 0xffff;
166 writel(v, ioaddr + (reg & ~2));
168 writew(val, ioaddr + reg);
172 #elif defined(CONFIG_SH_SH4202_MICRODEV)
174 #define SMC_CAN_USE_8BIT 0
175 #define SMC_CAN_USE_16BIT 1
176 #define SMC_CAN_USE_32BIT 0
178 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
179 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
180 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
181 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
182 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
183 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
184 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
185 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
186 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
187 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
189 #define SMC_IRQ_FLAGS (0)
191 #elif defined(CONFIG_M32R)
193 #define SMC_CAN_USE_8BIT 0
194 #define SMC_CAN_USE_16BIT 1
195 #define SMC_CAN_USE_32BIT 0
197 #define SMC_inb(a, r) inb(((u32)a) + (r))
198 #define SMC_inw(a, r) inw(((u32)a) + (r))
199 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
200 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
201 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
202 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
204 #define SMC_IRQ_FLAGS (0)
206 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
207 #define RPC_LSB_DEFAULT RPC_LED_100_10
209 #elif defined(CONFIG_ARCH_VERSATILE)
211 #define SMC_CAN_USE_8BIT 1
212 #define SMC_CAN_USE_16BIT 1
213 #define SMC_CAN_USE_32BIT 1
216 #define SMC_inb(a, r) readb((a) + (r))
217 #define SMC_inw(a, r) readw((a) + (r))
218 #define SMC_inl(a, r) readl((a) + (r))
219 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
220 #define SMC_outw(v, a, r) writew(v, (a) + (r))
221 #define SMC_outl(v, a, r) writel(v, (a) + (r))
222 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
223 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
224 #define SMC_IRQ_FLAGS (-1)
226 #elif defined(CONFIG_MN10300)
234 #elif defined(CONFIG_ARCH_MSM)
236 #define SMC_CAN_USE_8BIT 0
237 #define SMC_CAN_USE_16BIT 1
238 #define SMC_CAN_USE_32BIT 0
241 #define SMC_inw(a, r) readw((a) + (r))
242 #define SMC_outw(v, a, r) writew(v, (a) + (r))
243 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
244 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
246 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
248 #elif defined(CONFIG_COLDFIRE)
250 #define SMC_CAN_USE_8BIT 0
251 #define SMC_CAN_USE_16BIT 1
252 #define SMC_CAN_USE_32BIT 0
255 static inline void mcf_insw(
void *
a,
unsigned char *
p,
int l)
262 static inline void mcf_outsw(
void *a,
unsigned char *p,
int l)
269 #define SMC_inw(a, r) _swapw(readw((a) + (r)))
270 #define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r))
271 #define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l)
272 #define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l)
274 #define SMC_IRQ_FLAGS (IRQF_DISABLED)
282 #define SMC_CAN_USE_8BIT 1
283 #define SMC_CAN_USE_16BIT 1
284 #define SMC_CAN_USE_32BIT 1
287 #define SMC_IO_SHIFT (lp->io_shift)
289 #define SMC_inb(a, r) readb((a) + (r))
290 #define SMC_inw(a, r) readw((a) + (r))
291 #define SMC_inl(a, r) readl((a) + (r))
292 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
293 #define SMC_outw(v, a, r) writew(v, (a) + (r))
294 #define SMC_outl(v, a, r) writel(v, (a) + (r))
295 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
296 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
297 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
298 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
300 #define RPC_LSA_DEFAULT RPC_LED_100_10
301 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
341 #ifdef CONFIG_ARCH_PXA
355 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
356 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
357 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
359 #ifdef CONFIG_ARCH_PXA
367 #include <mach/dma.h>
371 #define SMC_insl(a, r, p, l) \
372 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
377 u_long physaddr = lp->physaddr;
381 if (dma == (
unsigned char)-1) {
382 readsl(ioaddr + reg, buf, len);
410 #define SMC_insw(a, r, p, l) \
411 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
416 u_long physaddr = lp->physaddr;
420 if (dma == (
unsigned char)-1) {
421 readsw(ioaddr + reg, buf, len);
426 while ((
long)buf & 6) {
448 smc_pxa_dma_irq(
int dma,
void *
dummy)
462 #if ! SMC_CAN_USE_32BIT
463 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
464 #define SMC_outl(x, ioaddr, reg) BUG()
465 #define SMC_insl(a, r, p, l) BUG()
466 #define SMC_outsl(a, r, p, l) BUG()
469 #if !defined(SMC_insl) || !defined(SMC_outsl)
470 #define SMC_insl(a, r, p, l) BUG()
471 #define SMC_outsl(a, r, p, l) BUG()
474 #if ! SMC_CAN_USE_16BIT
480 #define SMC_outw(x, ioaddr, reg) \
482 unsigned int __val16 = (x); \
483 SMC_outb( __val16, ioaddr, reg ); \
484 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
486 #define SMC_inw(ioaddr, reg) \
488 unsigned int __val16; \
489 __val16 = SMC_inb( ioaddr, reg ); \
490 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
494 #define SMC_insw(a, r, p, l) BUG()
495 #define SMC_outsw(a, r, p, l) BUG()
499 #if !defined(SMC_insw) || !defined(SMC_outsw)
500 #define SMC_insw(a, r, p, l) BUG()
501 #define SMC_outsw(a, r, p, l) BUG()
504 #if ! SMC_CAN_USE_8BIT
505 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
506 #define SMC_outb(x, ioaddr, reg) BUG()
507 #define SMC_insb(a, r, p, l) BUG()
508 #define SMC_outsb(a, r, p, l) BUG()
511 #if !defined(SMC_insb) || !defined(SMC_outsb)
512 #define SMC_insb(a, r, p, l) BUG()
513 #define SMC_outsb(a, r, p, l) BUG()
516 #ifndef SMC_CAN_USE_DATACS
517 #define SMC_CAN_USE_DATACS 0
521 #define SMC_IO_SHIFT 0
524 #ifndef SMC_IRQ_FLAGS
525 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
528 #ifndef SMC_INTERRUPT_PREAMBLE
529 #define SMC_INTERRUPT_PREAMBLE
534 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
535 #define SMC_DATA_EXTENT (4)
544 #define BANK_SELECT (14 << SMC_IO_SHIFT)
549 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
550 #define TCR_ENABLE 0x0001 // When 1 we can transmit
551 #define TCR_LOOP 0x0002 // Controls output pin LBK
552 #define TCR_FORCOL 0x0004 // When 1 will force a collision
553 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
554 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
555 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
556 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
557 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
558 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
559 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
563 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
568 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
569 #define ES_TX_SUC 0x0001 // Last TX was successful
570 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
571 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
572 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
573 #define ES_16COL 0x0010 // 16 Collisions Reached
574 #define ES_SQET 0x0020 // Signal Quality Error Test
575 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
576 #define ES_TXDEFR 0x0080 // Transmit Deferred
577 #define ES_LATCOL 0x0200 // Late collision detected on last tx
578 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
579 #define ES_EXC_DEF 0x0800 // Excessive Deferral
580 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
581 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
582 #define ES_TXUNRN 0x8000 // Tx Underrun
587 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
588 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
589 #define RCR_PRMS 0x0002 // Enable promiscuous mode
590 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
591 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
592 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
593 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
594 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
595 #define RCR_SOFTRST 0x8000 // resets the chip
598 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
599 #define RCR_CLEAR 0x0 // set it to a base state
604 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
609 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
614 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
615 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
616 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
617 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
618 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
619 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
621 #ifndef RPC_LSA_DEFAULT
622 #define RPC_LSA_DEFAULT RPC_LED_100
624 #ifndef RPC_LSB_DEFAULT
625 #define RPC_LSB_DEFAULT RPC_LED_FD
628 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
635 #define BSR_REG 0x000E
640 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
641 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
642 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
643 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
644 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
647 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
652 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
657 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
658 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
659 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
664 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
669 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
670 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
671 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
672 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
673 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
674 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
675 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
676 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
677 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
682 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
683 #define MC_BUSY 1 // When 1 the last release has not completed
684 #define MC_NOP (0<<5) // No Op
685 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
686 #define MC_RESET (2<<5) // Reset MMU to initial state
687 #define MC_REMOVE (3<<5) // Remove the current rx packet
688 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
689 #define MC_FREEPKT (5<<5) // Release packet in PNR register
690 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
691 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
696 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
701 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
702 #define AR_FAILED 0x80 // Alocation Failed
707 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
708 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
712 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
713 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
715 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
719 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
720 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
721 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
722 #define PTR_READ 0x2000 // When 1 the operation is a read
727 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
732 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
737 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
738 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
739 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
740 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
741 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
742 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
743 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
744 #define IM_TX_INT 0x02 // Transmit Interrupt
745 #define IM_RCV_INT 0x01 // Receive Interrupt
750 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
751 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
752 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
753 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
758 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
759 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
760 #define MII_MDOE 0x0008 // MII Output Enable
761 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
762 #define MII_MDI 0x0002 // MII Input, pin MDI
763 #define MII_MDO 0x0001 // MII Output, pin MDO
769 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
775 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
776 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
777 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
782 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
790 #define CHIP_91100FD 8
791 #define CHIP_91111FD 9
793 static const char * chip_ids[ 16 ] = {
809 #define RS_ALGNERR 0x8000
810 #define RS_BRODCAST 0x4000
811 #define RS_BADCRC 0x2000
812 #define RS_ODDFRAME 0x1000
813 #define RS_TOOLONG 0x0800
814 #define RS_TOOSHORT 0x0400
815 #define RS_MULTICAST 0x0001
816 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
823 #define PHY_LAN83C183 0x0016f840
824 #define PHY_LAN83C180 0x02821c50
835 #define PHY_CFG1_REG 0x10
836 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
837 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
838 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
839 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
840 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
841 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
842 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
843 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
844 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
845 #define PHY_CFG1_TLVL_MASK 0x003C
846 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
850 #define PHY_CFG2_REG 0x11
851 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
852 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
853 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
854 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
857 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
858 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
859 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
860 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
861 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
862 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
863 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
864 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
865 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
866 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
867 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
870 #define PHY_MASK_REG 0x13 // Interrupt Mask
879 #define ECOR_RESET 0x80
880 #define ECOR_LEVEL_IRQ 0x40
881 #define ECOR_WR_ATTRIB 0x04
882 #define ECOR_ENABLE 0x01
885 #define ECSR_IOIS8 0x20
886 #define ECSR_PWRDWN 0x04
887 #define ECSR_INT 0x02
889 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
906 #define SMC_REG(lp, reg, bank) \
908 int __b = SMC_CURRENT_BANK(lp); \
909 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
910 printk( "%s: bank reg screwed (0x%04x)\n", \
917 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
929 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
931 #define SMC_GET_PN(lp) \
932 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
933 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
935 #define SMC_SET_PN(lp, x) \
937 if (SMC_MUST_ALIGN_WRITE(lp)) \
938 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
939 else if (SMC_8BIT(lp)) \
940 SMC_outb(x, ioaddr, PN_REG(lp)); \
942 SMC_outw(x, ioaddr, PN_REG(lp)); \
945 #define SMC_GET_AR(lp) \
946 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
947 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
949 #define SMC_GET_TXFIFO(lp) \
950 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
951 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
953 #define SMC_GET_RXFIFO(lp) \
954 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
955 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
957 #define SMC_GET_INT(lp) \
958 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
959 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
961 #define SMC_ACK_INT(lp, x) \
964 SMC_outb(x, ioaddr, INT_REG(lp)); \
966 unsigned long __flags; \
968 local_irq_save(__flags); \
969 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
970 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
971 local_irq_restore(__flags); \
975 #define SMC_GET_INT_MASK(lp) \
976 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
977 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
979 #define SMC_SET_INT_MASK(lp, x) \
982 SMC_outb(x, ioaddr, IM_REG(lp)); \
984 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
987 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
989 #define SMC_SELECT_BANK(lp, x) \
991 if (SMC_MUST_ALIGN_WRITE(lp)) \
992 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
994 SMC_outw(x, ioaddr, BANK_SELECT); \
997 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
999 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1001 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1003 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1005 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1007 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1009 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1011 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1013 #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
1015 #define SMC_SET_GP(lp, x) \
1017 if (SMC_MUST_ALIGN_WRITE(lp)) \
1018 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
1020 SMC_outw(x, ioaddr, GP_REG(lp)); \
1023 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1025 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1027 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1029 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1031 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1033 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1035 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1037 #define SMC_SET_PTR(lp, x) \
1039 if (SMC_MUST_ALIGN_WRITE(lp)) \
1040 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1042 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1045 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1047 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1049 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1051 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1053 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1055 #define SMC_SET_RPC(lp, x) \
1057 if (SMC_MUST_ALIGN_WRITE(lp)) \
1058 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1060 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1063 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1065 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1067 #ifndef SMC_GET_MAC_ADDR
1068 #define SMC_GET_MAC_ADDR(lp, addr) \
1071 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1072 addr[0] = __v; addr[1] = __v >> 8; \
1073 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1074 addr[2] = __v; addr[3] = __v >> 8; \
1075 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1076 addr[4] = __v; addr[5] = __v >> 8; \
1080 #define SMC_SET_MAC_ADDR(lp, addr) \
1082 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1083 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1084 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1087 #define SMC_SET_MCAST(lp, x) \
1089 const unsigned char *mt = (x); \
1090 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1091 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1092 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1093 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1096 #define SMC_PUT_PKT_HDR(lp, status, length) \
1098 if (SMC_32BIT(lp)) \
1099 SMC_outl((status) | (length)<<16, ioaddr, \
1102 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1103 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1107 #define SMC_GET_PKT_HDR(lp, status, length) \
1109 if (SMC_32BIT(lp)) { \
1110 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1111 (status) = __val & 0xffff; \
1112 (length) = __val >> 16; \
1114 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1115 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1119 #define SMC_PUSH_DATA(lp, p, l) \
1121 if (SMC_32BIT(lp)) { \
1122 void *__ptr = (p); \
1124 void __iomem *__ioaddr = ioaddr; \
1125 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1127 SMC_outw(*(u16 *)__ptr, ioaddr, \
1131 if (SMC_CAN_USE_DATACS && lp->datacs) \
1132 __ioaddr = lp->datacs; \
1133 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1135 __ptr += (__len & ~3); \
1136 SMC_outw(*((u16 *)__ptr), ioaddr, \
1139 } else if (SMC_16BIT(lp)) \
1140 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1141 else if (SMC_8BIT(lp)) \
1142 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1145 #define SMC_PULL_DATA(lp, p, l) \
1147 if (SMC_32BIT(lp)) { \
1148 void *__ptr = (p); \
1150 void __iomem *__ioaddr = ioaddr; \
1151 if ((unsigned long)__ptr & 2) { \
1168 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1170 if (SMC_CAN_USE_DATACS && lp->datacs) \
1171 __ioaddr = lp->datacs; \
1173 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1174 } else if (SMC_16BIT(lp)) \
1175 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1176 else if (SMC_8BIT(lp)) \
1177 SMC_insb(ioaddr, DATA_REG(lp), p, l); \