Macros
#define	IXP4XX_QMGR_BASE_PHYS 0x60000000

#define	IXP4XX_QMGR_BASE_VIRT IOMEM(0xFEF15000)

#define	IXP4XX_QMGR_REGION_SIZE 0x00004000

#define	IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000

#define	IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000)

#define	IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000

#define	IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000

#define	IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000)

#define	IXP4XX_PCI_CFG_REGION_SIZE 0x00001000

#define	IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000

#define	IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000

#define	IXP4XX_EXP_CFG_REGION_SIZE 0x00001000

#define	IXP4XX_EXP_CS0_OFFSET 0x00

#define	IXP4XX_EXP_CS1_OFFSET 0x04

#define	IXP4XX_EXP_CS2_OFFSET 0x08

#define	IXP4XX_EXP_CS3_OFFSET 0x0C

#define	IXP4XX_EXP_CS4_OFFSET 0x10

#define	IXP4XX_EXP_CS5_OFFSET 0x14

#define	IXP4XX_EXP_CS6_OFFSET 0x18

#define	IXP4XX_EXP_CS7_OFFSET 0x1C

#define	IXP4XX_EXP_CFG0_OFFSET 0x20

#define	IXP4XX_EXP_CFG1_OFFSET 0x24

#define	IXP4XX_EXP_CFG2_OFFSET 0x28

#define	IXP4XX_EXP_CFG3_OFFSET 0x2C

#define	IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))

#define	IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)

#define	IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)

#define	IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET)

#define	IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)

#define	IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)

#define	IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)

#define	IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)

#define	IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)

#define	IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET)

#define	IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET)

#define	IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET)

#define	IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)

#define	IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)

#define	IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)

#define	IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)

#define	IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)

#define	IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)

#define	IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)

#define	IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)

#define	IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)

#define	IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)

#define	IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)

#define	IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)

#define	IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)

#define	IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)

#define	IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)

#define	IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)

#define	IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)

#define	IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)

#define	IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)

#define	IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)

#define	IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)

#define	IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)

#define	IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)

#define	IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)

#define	IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)

#define	IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)

#define	IXP4XX_NPEA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000)

#define	IXP4XX_NPEB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000)

#define	IXP4XX_NPEC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000)

#define	IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)

#define	IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)

#define	IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)

#define	IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)

#define	IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)

#define	IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)

#define	IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)

#define	IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)

#define	IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)

#define	IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)

#define	IXP4XX_ICPR_OFFSET 0x00 /* Interrupt Status */

#define	IXP4XX_ICMR_OFFSET 0x04 /* Interrupt Enable */

#define	IXP4XX_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */

#define	IXP4XX_ICIP_OFFSET 0x0C /* IRQ Status */

#define	IXP4XX_ICFP_OFFSET 0x10 /* FIQ Status */

#define	IXP4XX_ICHR_OFFSET 0x14 /* Interrupt Priority */

#define	IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */

#define	IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */

#define	IXP4XX_ICPR2_OFFSET 0x20 /* Interrupt Status 2 */

#define	IXP4XX_ICMR2_OFFSET 0x24 /* Interrupt Enable 2 */

#define	IXP4XX_ICLR2_OFFSET 0x28 /* Interrupt IRQ/FIQ Select 2 */

#define	IXP4XX_ICIP2_OFFSET 0x2C /* IRQ Status */

#define	IXP4XX_ICFP2_OFFSET 0x30 /* FIQ Status */

#define	IXP4XX_ICEEN_OFFSET 0x34 /* Error High Pri Enable */

#define	IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))

#define	IXP4XX_ICPR IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)

#define	IXP4XX_ICMR IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)

#define	IXP4XX_ICLR IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)

#define	IXP4XX_ICIP IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)

#define	IXP4XX_ICFP IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)

#define	IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)

#define	IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET)

#define	IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)

#define	IXP4XX_ICPR2 IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)

#define	IXP4XX_ICMR2 IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)

#define	IXP4XX_ICLR2 IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)

#define	IXP4XX_ICIP2 IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)

#define	IXP4XX_ICFP2 IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)

#define	IXP4XX_ICEEN IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)

#define	IXP4XX_GPIO_GPOUTR_OFFSET 0x00

#define	IXP4XX_GPIO_GPOER_OFFSET 0x04

#define	IXP4XX_GPIO_GPINR_OFFSET 0x08

#define	IXP4XX_GPIO_GPISR_OFFSET 0x0C

#define	IXP4XX_GPIO_GPIT1R_OFFSET 0x10

#define	IXP4XX_GPIO_GPIT2R_OFFSET 0x14

#define	IXP4XX_GPIO_GPCLKR_OFFSET 0x18

#define	IXP4XX_GPIO_GPDBSELR_OFFSET 0x1C

#define	IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))

#define	IXP4XX_GPIO_GPOUTR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)

#define	IXP4XX_GPIO_GPOER IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)

#define	IXP4XX_GPIO_GPINR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)

#define	IXP4XX_GPIO_GPISR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)

#define	IXP4XX_GPIO_GPIT1R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)

#define	IXP4XX_GPIO_GPIT2R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)

#define	IXP4XX_GPIO_GPCLKR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)

#define	IXP4XX_GPIO_GPDBSELR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)

#define	IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0

#define	IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1

#define	IXP4XX_GPIO_STYLE_RISING_EDGE 0x2

#define	IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3

#define	IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4

#define	IXP4XX_GPIO_STYLE_CLEAR 0x7

#define	IXP4XX_GPIO_STYLE_SIZE 3

#define	IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */

#define	IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */

#define	IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */

#define	IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */

#define	IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */

#define	IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */

#define	IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */

#define	IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */

#define	IXP4XX_OSST_OFFSET 0x20 /* Timer Status */

#define	IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))

#define	IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)

#define	IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)

#define	IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)

#define	IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)

#define	IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)

#define	IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)

#define	IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)

#define	IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)

#define	IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)

#define	IXP4XX_OST_ENABLE 0x00000001

#define	IXP4XX_OST_ONE_SHOT 0x00000002

#define	IXP4XX_OST_RELOAD_MASK 0x00000003

#define	IXP4XX_OST_DISABLED 0x00000000

#define	IXP4XX_OSST_TIMER_1_PEND 0x00000001

#define	IXP4XX_OSST_TIMER_2_PEND 0x00000002

#define	IXP4XX_OSST_TIMER_TS_PEND 0x00000004

#define	IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008

#define	IXP4XX_OSST_TIMER_WARM_RESET 0x00000010

#define	IXP4XX_WDT_KEY 0x0000482E

#define	IXP4XX_WDT_RESET_ENABLE 0x00000001

#define	IXP4XX_WDT_IRQ_ENABLE 0x00000002

#define	IXP4XX_WDT_COUNT_ENABLE 0x00000004

#define	PCI_NP_AD_OFFSET 0x00

#define	PCI_NP_CBE_OFFSET 0x04

#define	PCI_NP_WDATA_OFFSET 0x08

#define	PCI_NP_RDATA_OFFSET 0x0c

#define	PCI_CRP_AD_CBE_OFFSET 0x10

#define	PCI_CRP_WDATA_OFFSET 0x14

#define	PCI_CRP_RDATA_OFFSET 0x18

#define	PCI_CSR_OFFSET 0x1c

#define	PCI_ISR_OFFSET 0x20

#define	PCI_INTEN_OFFSET 0x24

#define	PCI_DMACTRL_OFFSET 0x28

#define	PCI_AHBMEMBASE_OFFSET 0x2c

#define	PCI_AHBIOBASE_OFFSET 0x30

#define	PCI_PCIMEMBASE_OFFSET 0x34

#define	PCI_AHBDOORBELL_OFFSET 0x38

#define	PCI_PCIDOORBELL_OFFSET 0x3C

#define	PCI_ATPDMA0_AHBADDR_OFFSET 0x40

#define	PCI_ATPDMA0_PCIADDR_OFFSET 0x44

#define	PCI_ATPDMA0_LENADDR_OFFSET 0x48

#define	PCI_ATPDMA1_AHBADDR_OFFSET 0x4C

#define	PCI_ATPDMA1_PCIADDR_OFFSET 0x50

#define	PCI_ATPDMA1_LENADDR_OFFSET 0x54

#define	IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))

#define	PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)

#define	PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)

#define	PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)

#define	PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)

#define	PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)

#define	PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)

#define	PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)

#define	PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET)

#define	PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET)

#define	PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)

#define	PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)

#define	PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)

#define	PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)

#define	PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)

#define	PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)

#define	PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)

#define	PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)

#define	PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)

#define	PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)

#define	PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)

#define	PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)

#define	PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)

#define	PCI_CSR_HOST 0x00000001

#define	PCI_CSR_ARBEN 0x00000002

#define	PCI_CSR_ADS 0x00000004

#define	PCI_CSR_PDS 0x00000008

#define	PCI_CSR_ABE 0x00000010

#define	PCI_CSR_DBT 0x00000020

#define	PCI_CSR_ASE 0x00000100

#define	PCI_CSR_IC 0x00008000

#define	PCI_ISR_PSE 0x00000001

#define	PCI_ISR_PFE 0x00000002

#define	PCI_ISR_PPE 0x00000004

#define	PCI_ISR_AHBE 0x00000008

#define	PCI_ISR_APDC 0x00000010

#define	PCI_ISR_PADC 0x00000020

#define	PCI_ISR_ADB 0x00000040

#define	PCI_ISR_PDB 0x00000080

#define	PCI_INTEN_PSE 0x00000001

#define	PCI_INTEN_PFE 0x00000002

#define	PCI_INTEN_PPE 0x00000004

#define	PCI_INTEN_AHBE 0x00000008

#define	PCI_INTEN_APDC 0x00000010

#define	PCI_INTEN_PADC 0x00000020

#define	PCI_INTEN_ADB 0x00000040

#define	PCI_INTEN_PDB 0x00000080

#define	IXP4XX_PCI_NP_CBE_BESL 4

#define	NP_CMD_IOREAD 0x2

#define	NP_CMD_IOWRITE 0x3

#define	NP_CMD_CONFIGREAD 0xa

#define	NP_CMD_CONFIGWRITE 0xb

#define	NP_CMD_MEMREAD 0x6

#define	NP_CMD_MEMWRITE 0x7

#define	CRP_AD_CBE_BESL 20

#define	CRP_AD_CBE_WRITE 0x00010000

#define	IXP4XX_USB_REG(x) (((volatile u32 )(x)))

#define	UDC_RES1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)

#define	UDC_RES2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)

#define	UDC_RES3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)

#define	UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)

#define	UDCCS0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)

#define	UDCCS1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)

#define	UDCCS2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)

#define	UDCCS3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)

#define	UDCCS4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)

#define	UDCCS5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)

#define	UDCCS6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)

#define	UDCCS7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)

#define	UDCCS8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)

#define	UDCCS9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)

#define	UDCCS10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)

#define	UDCCS11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)

#define	UDCCS12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)

#define	UDCCS13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)

#define	UDCCS14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)

#define	UDCCS15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)

#define	UFNRH IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)

#define	UFNRL IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)

#define	UBCR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)

#define	UBCR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)

#define	UBCR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)

#define	UBCR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)

#define	UBCR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)

#define	UBCR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)

#define	UDDR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)

#define	UDDR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)

#define	UDDR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)

#define	UDDR3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)

#define	UDDR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)

#define	UDDR5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)

#define	UDDR6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)

#define	UDDR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)

#define	UDDR8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)

#define	UDDR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)

#define	UDDR10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)

#define	UDDR11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)

#define	UDDR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)

#define	UDDR13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)

#define	UDDR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)

#define	UDDR15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)

#define	UICR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)

#define	UICR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)

#define	USIR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)

#define	USIR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)

#define	UDCCR_UDE (1 << 0) /* UDC enable */

#define	UDCCR_UDA (1 << 1) /* UDC active */

#define	UDCCR_RSM (1 << 2) /* Device resume */

#define	UDCCR_RESIR (1 << 3) /* Resume interrupt request */

#define	UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */

#define	UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */

#define	UDCCR_RSTIR (1 << 6) /* Reset interrupt request */

#define	UDCCR_REM (1 << 7) /* Reset interrupt mask */

#define	UDCCS0_OPR (1 << 0) /* OUT packet ready */

#define	UDCCS0_IPR (1 << 1) /* IN packet ready */

#define	UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */

#define	UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */

#define	UDCCS0_SST (1 << 4) /* Sent stall */

#define	UDCCS0_FST (1 << 5) /* Force stall */

#define	UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */

#define	UDCCS0_SA (1 << 7) /* Setup active */

#define	UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */

#define	UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */

#define	UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */

#define	UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */

#define	UDCCS_BI_SST (1 << 4) /* Sent stall */

#define	UDCCS_BI_FST (1 << 5) /* Force stall */

#define	UDCCS_BI_TSP (1 << 7) /* Transmit short packet */

#define	UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */

#define	UDCCS_BO_RPC (1 << 1) /* Receive packet complete */

#define	UDCCS_BO_DME (1 << 3) /* DMA enable */

#define	UDCCS_BO_SST (1 << 4) /* Sent stall */

#define	UDCCS_BO_FST (1 << 5) /* Force stall */

#define	UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */

#define	UDCCS_BO_RSP (1 << 7) /* Receive short packet */

#define	UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */

#define	UDCCS_II_TPC (1 << 1) /* Transmit packet complete */

#define	UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */

#define	UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */

#define	UDCCS_II_TSP (1 << 7) /* Transmit short packet */

#define	UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */

#define	UDCCS_IO_RPC (1 << 1) /* Receive packet complete */

#define	UDCCS_IO_ROF (1 << 3) /* Receive overflow */

#define	UDCCS_IO_DME (1 << 3) /* DMA enable */

#define	UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */

#define	UDCCS_IO_RSP (1 << 7) /* Receive short packet */

#define	UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */

#define	UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */

#define	UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */

#define	UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */

#define	UDCCS_INT_SST (1 << 4) /* Sent stall */

#define	UDCCS_INT_FST (1 << 5) /* Force stall */

#define	UDCCS_INT_TSP (1 << 7) /* Transmit short packet */

#define	UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */

#define	UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */

#define	UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */

#define	UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */

#define	UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */

#define	UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */

#define	UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */

#define	UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */

#define	UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */

#define	UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */

#define	UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */

#define	UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */

#define	UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */

#define	UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */

#define	UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */

#define	UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */

#define	USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */

#define	USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */

#define	USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */

#define	USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */

#define	USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */

#define	USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */

#define	USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */

#define	USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */

#define	USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */

#define	USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */

#define	USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */

#define	USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */

#define	USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */

#define	USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */

#define	USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */

#define	USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */

#define	DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */

#define	IXP4XX_FEATURE_RCOMP (1 << 0)

#define	IXP4XX_FEATURE_USB_DEVICE (1 << 1)

#define	IXP4XX_FEATURE_HASH (1 << 2)

#define	IXP4XX_FEATURE_AES (1 << 3)

#define	IXP4XX_FEATURE_DES (1 << 4)

#define	IXP4XX_FEATURE_HDLC (1 << 5)

#define	IXP4XX_FEATURE_AAL (1 << 6)

#define	IXP4XX_FEATURE_HSS (1 << 7)

#define	IXP4XX_FEATURE_UTOPIA (1 << 8)

#define	IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)

#define	IXP4XX_FEATURE_NPEC_ETH (1 << 10)

#define	IXP4XX_FEATURE_RESET_NPEA (1 << 11)

#define	IXP4XX_FEATURE_RESET_NPEB (1 << 12)

#define	IXP4XX_FEATURE_RESET_NPEC (1 << 13)

#define	IXP4XX_FEATURE_PCI (1 << 14)

#define	IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)

#define	IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)

#define	IXP42X_FEATURE_MASK

#define	IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)

#define	IXP4XX_FEATURE_USB_HOST (1 << 18)

#define	IXP4XX_FEATURE_NPEA_ETH (1 << 19)

#define	IXP43X_FEATURE_MASK

#define	IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)

#define	IXP4XX_FEATURE_RSA (1 << 21)

#define	IXP46X_FEATURE_MASK

Macro Definition Documentation

#define CRP_AD_CBE_BESL 20

Definition at line 395 of file ixp4xx-regs.h.

#define CRP_AD_CBE_WRITE 0x00010000

Definition at line 396 of file ixp4xx-regs.h.

#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */

Definition at line 596 of file ixp4xx-regs.h.

#define IXP42X_FEATURE_MASK

Value:

(IXP4XX_FEATURE_RCOMP            | \
                     IXP4XX_FEATURE_USB_DEVICE       | \
                     IXP4XX_FEATURE_HASH             | \
                     IXP4XX_FEATURE_AES              | \
                     IXP4XX_FEATURE_DES              | \
                     IXP4XX_FEATURE_HDLC             | \
                     IXP4XX_FEATURE_AAL              | \
                     IXP4XX_FEATURE_HSS              | \
                     IXP4XX_FEATURE_UTOPIA           | \
                     IXP4XX_FEATURE_NPEB_ETH0        | \
                     IXP4XX_FEATURE_NPEC_ETH         | \
                     IXP4XX_FEATURE_RESET_NPEA       | \
                     IXP4XX_FEATURE_RESET_NPEB       | \
                     IXP4XX_FEATURE_RESET_NPEC       | \
                     IXP4XX_FEATURE_PCI              | \
                     IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \
                     IXP4XX_FEATURE_XSCALE_MAX_FREQ)

Definition at line 617 of file ixp4xx-regs.h.

#define IXP43X_FEATURE_MASK

Value:

(IXP42X_FEATURE_MASK             | \
                     IXP4XX_FEATURE_ECC_TIMESYNC     | \
                     IXP4XX_FEATURE_USB_HOST         | \
                     IXP4XX_FEATURE_NPEA_ETH)

Definition at line 640 of file ixp4xx-regs.h.

#define IXP46X_FEATURE_MASK

Value:

(IXP43X_FEATURE_MASK             | \
                     IXP4XX_FEATURE_NPEB_ETH_1_TO_3  | \
                     IXP4XX_FEATURE_RSA)

Definition at line 648 of file ixp4xx-regs.h.

#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)

Definition at line 120 of file ixp4xx-regs.h.

#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)

Definition at line 142 of file ixp4xx-regs.h.

#define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)

Definition at line 121 of file ixp4xx-regs.h.

#define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)

Definition at line 143 of file ixp4xx-regs.h.

#define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)

Definition at line 122 of file ixp4xx-regs.h.

#define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)

Definition at line 144 of file ixp4xx-regs.h.

#define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)

Definition at line 123 of file ixp4xx-regs.h.

#define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)

Definition at line 145 of file ixp4xx-regs.h.

#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)

Definition at line 116 of file ixp4xx-regs.h.

#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)

Definition at line 138 of file ixp4xx-regs.h.

#define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)

Definition at line 117 of file ixp4xx-regs.h.

#define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)

Definition at line 139 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET)

Definition at line 98 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CFG0_OFFSET 0x20

Definition at line 79 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET)

Definition at line 99 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CFG1_OFFSET 0x24

Definition at line 80 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET)

Definition at line 100 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CFG2_OFFSET 0x28

Definition at line 81 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)

Definition at line 101 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CFG3_OFFSET 0x2C

Definition at line 82 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000

Definition at line 67 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000

Definition at line 68 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000

Definition at line 69 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)

Definition at line 89 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS0_OFFSET 0x00

Definition at line 71 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)

Definition at line 90 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS1_OFFSET 0x04

Definition at line 72 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET)

Definition at line 91 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS2_OFFSET 0x08

Definition at line 73 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)

Definition at line 92 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS3_OFFSET 0x0C

Definition at line 74 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)

Definition at line 93 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS4_OFFSET 0x10

Definition at line 75 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)

Definition at line 94 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS5_OFFSET 0x14

Definition at line 76 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)

Definition at line 95 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS6_OFFSET 0x18

Definition at line 77 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)

Definition at line 96 of file ixp4xx-regs.h.

#define IXP4XX_EXP_CS7_OFFSET 0x1C

Definition at line 78 of file ixp4xx-regs.h.

#define IXP4XX_EXP_REG ( x ) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))

Definition at line 87 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_AAL (1 << 6)

Definition at line 606 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_AES (1 << 3)

Definition at line 603 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_DES (1 << 4)

Definition at line 604 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)

Definition at line 637 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_HASH (1 << 2)

Definition at line 602 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_HDLC (1 << 5)

Definition at line 605 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_HSS (1 << 7)

Definition at line 607 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)

Definition at line 639 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)

Definition at line 609 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)

Definition at line 646 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)

Definition at line 610 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_PCI (1 << 14)

Definition at line 614 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_RCOMP (1 << 0)

Definition at line 600 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)

Definition at line 611 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)

Definition at line 612 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)

Definition at line 613 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_RSA (1 << 21)

Definition at line 647 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)

Definition at line 601 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_USB_HOST (1 << 18)

Definition at line 638 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_UTOPIA (1 << 8)

Definition at line 608 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)

Definition at line 615 of file ixp4xx-regs.h.

#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)

Definition at line 616 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)

Definition at line 111 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)

Definition at line 133 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPCLKR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)

Definition at line 218 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPCLKR_OFFSET 0x18

Definition at line 203 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPDBSELR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)

Definition at line 219 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPDBSELR_OFFSET 0x1C

Definition at line 204 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPINR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)

Definition at line 214 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPINR_OFFSET 0x08

Definition at line 199 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPISR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)

Definition at line 215 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPISR_OFFSET 0x0C

Definition at line 200 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPIT1R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)

Definition at line 216 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPIT1R_OFFSET 0x10

Definition at line 201 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPIT2R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)

Definition at line 217 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPIT2R_OFFSET 0x14

Definition at line 202 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPOER IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)

Definition at line 213 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPOER_OFFSET 0x04

Definition at line 198 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPOUTR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)

Definition at line 212 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_GPOUTR_OFFSET 0x00

Definition at line 197 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_REG ( x ) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))

Definition at line 210 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0

Definition at line 227 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1

Definition at line 228 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_STYLE_CLEAR 0x7

Definition at line 236 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3

Definition at line 230 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2

Definition at line 229 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_STYLE_SIZE 3

Definition at line 237 of file ixp4xx-regs.h.

#define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4

Definition at line 231 of file ixp4xx-regs.h.

#define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)

Definition at line 125 of file ixp4xx-regs.h.

#define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)

Definition at line 147 of file ixp4xx-regs.h.

#define IXP4XX_ICEEN IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)

Definition at line 192 of file ixp4xx-regs.h.

#define IXP4XX_ICEEN_OFFSET 0x34 /* Error High Pri Enable */

Definition at line 170 of file ixp4xx-regs.h.

#define IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)

Definition at line 186 of file ixp4xx-regs.h.

#define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */

Definition at line 160 of file ixp4xx-regs.h.

#define IXP4XX_ICFP IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)

Definition at line 183 of file ixp4xx-regs.h.

#define IXP4XX_ICFP2 IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)

Definition at line 191 of file ixp4xx-regs.h.

#define IXP4XX_ICFP2_OFFSET 0x30 /* FIQ Status */

Definition at line 169 of file ixp4xx-regs.h.

#define IXP4XX_ICFP_OFFSET 0x10 /* FIQ Status */

Definition at line 157 of file ixp4xx-regs.h.

#define IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)

Definition at line 184 of file ixp4xx-regs.h.

#define IXP4XX_ICHR_OFFSET 0x14 /* Interrupt Priority */

Definition at line 158 of file ixp4xx-regs.h.

#define IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET)

Definition at line 185 of file ixp4xx-regs.h.

#define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */

Definition at line 159 of file ixp4xx-regs.h.

#define IXP4XX_ICIP IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)

Definition at line 182 of file ixp4xx-regs.h.

#define IXP4XX_ICIP2 IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)

Definition at line 190 of file ixp4xx-regs.h.

#define IXP4XX_ICIP2_OFFSET 0x2C /* IRQ Status */

Definition at line 168 of file ixp4xx-regs.h.

#define IXP4XX_ICIP_OFFSET 0x0C /* IRQ Status */

Definition at line 156 of file ixp4xx-regs.h.

#define IXP4XX_ICLR IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)

Definition at line 181 of file ixp4xx-regs.h.

#define IXP4XX_ICLR2 IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)

Definition at line 189 of file ixp4xx-regs.h.

#define IXP4XX_ICLR2_OFFSET 0x28 /* Interrupt IRQ/FIQ Select 2 */

Definition at line 167 of file ixp4xx-regs.h.

#define IXP4XX_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */

Definition at line 155 of file ixp4xx-regs.h.

#define IXP4XX_ICMR IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)

Definition at line 180 of file ixp4xx-regs.h.

#define IXP4XX_ICMR2 IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)

Definition at line 188 of file ixp4xx-regs.h.

#define IXP4XX_ICMR2_OFFSET 0x24 /* Interrupt Enable 2 */

Definition at line 166 of file ixp4xx-regs.h.

#define IXP4XX_ICMR_OFFSET 0x04 /* Interrupt Enable */

Definition at line 154 of file ixp4xx-regs.h.

#define IXP4XX_ICPR IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)

Definition at line 179 of file ixp4xx-regs.h.

#define IXP4XX_ICPR2 IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)

Definition at line 187 of file ixp4xx-regs.h.

#define IXP4XX_ICPR2_OFFSET 0x20 /* Interrupt Status 2 */

Definition at line 165 of file ixp4xx-regs.h.

#define IXP4XX_ICPR_OFFSET 0x00 /* Interrupt Status */

Definition at line 153 of file ixp4xx-regs.h.

#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)

Definition at line 110 of file ixp4xx-regs.h.

#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)

Definition at line 132 of file ixp4xx-regs.h.

#define IXP4XX_INTC_REG ( x ) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))

Definition at line 177 of file ixp4xx-regs.h.

#define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)

Definition at line 113 of file ixp4xx-regs.h.

#define IXP4XX_NPEA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000)

Definition at line 135 of file ixp4xx-regs.h.

#define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)

Definition at line 114 of file ixp4xx-regs.h.

#define IXP4XX_NPEB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000)

Definition at line 136 of file ixp4xx-regs.h.

#define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)

Definition at line 115 of file ixp4xx-regs.h.

#define IXP4XX_NPEC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000)

Definition at line 137 of file ixp4xx-regs.h.

#define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)

Definition at line 260 of file ixp4xx-regs.h.

#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */

Definition at line 244 of file ixp4xx-regs.h.

#define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)

Definition at line 262 of file ixp4xx-regs.h.

#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */

Definition at line 246 of file ixp4xx-regs.h.

#define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)

Definition at line 266 of file ixp4xx-regs.h.

#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */

Definition at line 250 of file ixp4xx-regs.h.

#define IXP4XX_OSST_TIMER_1_PEND 0x00000001

Definition at line 276 of file ixp4xx-regs.h.

#define IXP4XX_OSST_TIMER_2_PEND 0x00000002

Definition at line 277 of file ixp4xx-regs.h.

#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004

Definition at line 278 of file ixp4xx-regs.h.

#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010

Definition at line 280 of file ixp4xx-regs.h.

#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008

Definition at line 279 of file ixp4xx-regs.h.

#define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)

Definition at line 259 of file ixp4xx-regs.h.

#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */

Definition at line 243 of file ixp4xx-regs.h.

#define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)

Definition at line 261 of file ixp4xx-regs.h.

#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */

Definition at line 245 of file ixp4xx-regs.h.

#define IXP4XX_OST_DISABLED 0x00000000

Definition at line 275 of file ixp4xx-regs.h.

#define IXP4XX_OST_ENABLE 0x00000001

Definition at line 271 of file ixp4xx-regs.h.

#define IXP4XX_OST_ONE_SHOT 0x00000002

Definition at line 272 of file ixp4xx-regs.h.

#define IXP4XX_OST_RELOAD_MASK 0x00000003

Definition at line 274 of file ixp4xx-regs.h.

#define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)

Definition at line 258 of file ixp4xx-regs.h.

#define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */

Definition at line 242 of file ixp4xx-regs.h.

#define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)

Definition at line 264 of file ixp4xx-regs.h.

#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */

Definition at line 248 of file ixp4xx-regs.h.

#define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)

Definition at line 265 of file ixp4xx-regs.h.

#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */

Definition at line 249 of file ixp4xx-regs.h.

#define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)

Definition at line 263 of file ixp4xx-regs.h.

#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */

Definition at line 247 of file ixp4xx-regs.h.

#define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000

Definition at line 60 of file ixp4xx-regs.h.

#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000)

Definition at line 61 of file ixp4xx-regs.h.

#define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000

Definition at line 62 of file ixp4xx-regs.h.

#define IXP4XX_PCI_CSR ( x ) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))

Definition at line 318 of file ixp4xx-regs.h.

#define IXP4XX_PCI_NP_CBE_BESL 4

Definition at line 380 of file ixp4xx-regs.h.

#define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000

Definition at line 53 of file ixp4xx-regs.h.

#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000)

Definition at line 54 of file ixp4xx-regs.h.

#define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000

Definition at line 55 of file ixp4xx-regs.h.

#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)

Definition at line 109 of file ixp4xx-regs.h.

#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)

Definition at line 131 of file ixp4xx-regs.h.

#define IXP4XX_QMGR_BASE_PHYS 0x60000000

Definition at line 45 of file ixp4xx-regs.h.

#define IXP4XX_QMGR_BASE_VIRT IOMEM(0xFEF15000)

Definition at line 46 of file ixp4xx-regs.h.

#define IXP4XX_QMGR_REGION_SIZE 0x00004000

Definition at line 47 of file ixp4xx-regs.h.

#define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)

Definition at line 126 of file ixp4xx-regs.h.

#define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)

Definition at line 148 of file ixp4xx-regs.h.

#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)

Definition at line 112 of file ixp4xx-regs.h.

#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)

Definition at line 134 of file ixp4xx-regs.h.

#define IXP4XX_TIMER_REG ( x ) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))

Definition at line 256 of file ixp4xx-regs.h.

#define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)

Definition at line 124 of file ixp4xx-regs.h.

#define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)

Definition at line 146 of file ixp4xx-regs.h.

#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)

Definition at line 107 of file ixp4xx-regs.h.

#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)

Definition at line 129 of file ixp4xx-regs.h.

#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)

Definition at line 108 of file ixp4xx-regs.h.

#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)

Definition at line 130 of file ixp4xx-regs.h.

#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)

Definition at line 118 of file ixp4xx-regs.h.

#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)

Definition at line 140 of file ixp4xx-regs.h.

#define IXP4XX_USB_REG ( x ) (*((volatile u32 *)(x)))

Definition at line 406 of file ixp4xx-regs.h.

#define IXP4XX_WDT_COUNT_ENABLE 0x00000004

Definition at line 286 of file ixp4xx-regs.h.

#define IXP4XX_WDT_IRQ_ENABLE 0x00000002

Definition at line 285 of file ixp4xx-regs.h.

#define IXP4XX_WDT_KEY 0x0000482E

Definition at line 282 of file ixp4xx-regs.h.

#define IXP4XX_WDT_RESET_ENABLE 0x00000001

Definition at line 284 of file ixp4xx-regs.h.

#define NP_CMD_CONFIGREAD 0xa

Definition at line 387 of file ixp4xx-regs.h.

#define NP_CMD_CONFIGWRITE 0xb

Definition at line 388 of file ixp4xx-regs.h.

#define NP_CMD_IOREAD 0x2

Definition at line 385 of file ixp4xx-regs.h.

#define NP_CMD_IOWRITE 0x3

Definition at line 386 of file ixp4xx-regs.h.

#define NP_CMD_MEMREAD 0x6

Definition at line 389 of file ixp4xx-regs.h.

#define NP_CMD_MEMWRITE 0x7

Definition at line 390 of file ixp4xx-regs.h.

#define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)

Definition at line 334 of file ixp4xx-regs.h.

#define PCI_AHBDOORBELL_OFFSET 0x38

Definition at line 306 of file ixp4xx-regs.h.

#define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)

Definition at line 332 of file ixp4xx-regs.h.

#define PCI_AHBIOBASE_OFFSET 0x30

Definition at line 304 of file ixp4xx-regs.h.

#define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)

Definition at line 331 of file ixp4xx-regs.h.

#define PCI_AHBMEMBASE_OFFSET 0x2c

Definition at line 303 of file ixp4xx-regs.h.

#define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)

Definition at line 336 of file ixp4xx-regs.h.

#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40

Definition at line 308 of file ixp4xx-regs.h.

#define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)

Definition at line 338 of file ixp4xx-regs.h.

#define PCI_ATPDMA0_LENADDR_OFFSET 0x48

Definition at line 310 of file ixp4xx-regs.h.

#define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)

Definition at line 337 of file ixp4xx-regs.h.

#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44

Definition at line 309 of file ixp4xx-regs.h.

#define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)

Definition at line 339 of file ixp4xx-regs.h.

#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C

Definition at line 311 of file ixp4xx-regs.h.

#define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)

Definition at line 341 of file ixp4xx-regs.h.

#define PCI_ATPDMA1_LENADDR_OFFSET 0x54

Definition at line 313 of file ixp4xx-regs.h.

#define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)

Definition at line 340 of file ixp4xx-regs.h.

#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50

Definition at line 312 of file ixp4xx-regs.h.

#define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)

Definition at line 324 of file ixp4xx-regs.h.

#define PCI_CRP_AD_CBE_OFFSET 0x10

Definition at line 296 of file ixp4xx-regs.h.

#define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)

Definition at line 326 of file ixp4xx-regs.h.

#define PCI_CRP_RDATA_OFFSET 0x18

Definition at line 298 of file ixp4xx-regs.h.

#define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)

Definition at line 325 of file ixp4xx-regs.h.

#define PCI_CRP_WDATA_OFFSET 0x14

Definition at line 297 of file ixp4xx-regs.h.

#define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET)

Definition at line 327 of file ixp4xx-regs.h.

#define PCI_CSR_ABE 0x00000010

Definition at line 352 of file ixp4xx-regs.h.

#define PCI_CSR_ADS 0x00000004

Definition at line 350 of file ixp4xx-regs.h.

#define PCI_CSR_ARBEN 0x00000002

Definition at line 349 of file ixp4xx-regs.h.

#define PCI_CSR_ASE 0x00000100

Definition at line 354 of file ixp4xx-regs.h.

#define PCI_CSR_DBT 0x00000020

Definition at line 353 of file ixp4xx-regs.h.

#define PCI_CSR_HOST 0x00000001

Definition at line 348 of file ixp4xx-regs.h.

#define PCI_CSR_IC 0x00008000

Definition at line 355 of file ixp4xx-regs.h.

#define PCI_CSR_OFFSET 0x1c

Definition at line 299 of file ixp4xx-regs.h.

#define PCI_CSR_PDS 0x00000008

Definition at line 351 of file ixp4xx-regs.h.

#define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)

Definition at line 330 of file ixp4xx-regs.h.

#define PCI_DMACTRL_OFFSET 0x28

Definition at line 302 of file ixp4xx-regs.h.

#define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)

Definition at line 329 of file ixp4xx-regs.h.

#define PCI_INTEN_ADB 0x00000040

Definition at line 374 of file ixp4xx-regs.h.

#define PCI_INTEN_AHBE 0x00000008

Definition at line 371 of file ixp4xx-regs.h.

#define PCI_INTEN_APDC 0x00000010

Definition at line 372 of file ixp4xx-regs.h.

#define PCI_INTEN_OFFSET 0x24

Definition at line 301 of file ixp4xx-regs.h.

#define PCI_INTEN_PADC 0x00000020

Definition at line 373 of file ixp4xx-regs.h.

#define PCI_INTEN_PDB 0x00000080

Definition at line 375 of file ixp4xx-regs.h.

#define PCI_INTEN_PFE 0x00000002

Definition at line 369 of file ixp4xx-regs.h.

#define PCI_INTEN_PPE 0x00000004

Definition at line 370 of file ixp4xx-regs.h.

#define PCI_INTEN_PSE 0x00000001

Definition at line 368 of file ixp4xx-regs.h.

#define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET)

Definition at line 328 of file ixp4xx-regs.h.

#define PCI_ISR_ADB 0x00000040

Definition at line 364 of file ixp4xx-regs.h.

#define PCI_ISR_AHBE 0x00000008

Definition at line 361 of file ixp4xx-regs.h.

#define PCI_ISR_APDC 0x00000010

Definition at line 362 of file ixp4xx-regs.h.

#define PCI_ISR_OFFSET 0x20

Definition at line 300 of file ixp4xx-regs.h.

#define PCI_ISR_PADC 0x00000020

Definition at line 363 of file ixp4xx-regs.h.

#define PCI_ISR_PDB 0x00000080

Definition at line 365 of file ixp4xx-regs.h.

#define PCI_ISR_PFE 0x00000002

Definition at line 359 of file ixp4xx-regs.h.

#define PCI_ISR_PPE 0x00000004

Definition at line 360 of file ixp4xx-regs.h.

#define PCI_ISR_PSE 0x00000001

Definition at line 358 of file ixp4xx-regs.h.

#define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)

Definition at line 320 of file ixp4xx-regs.h.

#define PCI_NP_AD_OFFSET 0x00

Definition at line 292 of file ixp4xx-regs.h.

#define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)

Definition at line 321 of file ixp4xx-regs.h.

#define PCI_NP_CBE_OFFSET 0x04

Definition at line 293 of file ixp4xx-regs.h.

#define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)

Definition at line 323 of file ixp4xx-regs.h.

#define PCI_NP_RDATA_OFFSET 0x0c

Definition at line 295 of file ixp4xx-regs.h.

#define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)

Definition at line 322 of file ixp4xx-regs.h.

#define PCI_NP_WDATA_OFFSET 0x08

Definition at line 294 of file ixp4xx-regs.h.

#define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)

Definition at line 335 of file ixp4xx-regs.h.

#define PCI_PCIDOORBELL_OFFSET 0x3C

Definition at line 307 of file ixp4xx-regs.h.

#define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)

Definition at line 333 of file ixp4xx-regs.h.

#define PCI_PCIMEMBASE_OFFSET 0x34

Definition at line 305 of file ixp4xx-regs.h.

#define UBCR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)

Definition at line 461 of file ixp4xx-regs.h.

#define UBCR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)

Definition at line 463 of file ixp4xx-regs.h.

#define UBCR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)

Definition at line 453 of file ixp4xx-regs.h.

#define UBCR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)

Definition at line 455 of file ixp4xx-regs.h.

#define UBCR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)

Definition at line 457 of file ixp4xx-regs.h.

#define UBCR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)

Definition at line 459 of file ixp4xx-regs.h.

#define UDC_RES1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)

Definition at line 409 of file ixp4xx-regs.h.

#define UDC_RES2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)

Definition at line 411 of file ixp4xx-regs.h.

#define UDC_RES3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)

Definition at line 413 of file ixp4xx-regs.h.

#define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)

Definition at line 415 of file ixp4xx-regs.h.

#define UDCCR_REM (1 << 7) /* Reset interrupt mask */

Definition at line 512 of file ixp4xx-regs.h.

#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */

Definition at line 508 of file ixp4xx-regs.h.

#define UDCCR_RSM (1 << 2) /* Device resume */

Definition at line 507 of file ixp4xx-regs.h.

#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */

Definition at line 511 of file ixp4xx-regs.h.

#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */

Definition at line 510 of file ixp4xx-regs.h.

#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */

Definition at line 509 of file ixp4xx-regs.h.

#define UDCCR_UDA (1 << 1) /* UDC active */

Definition at line 506 of file ixp4xx-regs.h.

#define UDCCR_UDE (1 << 0) /* UDC enable */

Definition at line 505 of file ixp4xx-regs.h.

#define UDCCS0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)

Definition at line 417 of file ixp4xx-regs.h.

#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */

Definition at line 517 of file ixp4xx-regs.h.

#define UDCCS0_FST (1 << 5) /* Force stall */

Definition at line 519 of file ixp4xx-regs.h.

#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */

Definition at line 516 of file ixp4xx-regs.h.

#define UDCCS0_IPR (1 << 1) /* IN packet ready */

Definition at line 515 of file ixp4xx-regs.h.

#define UDCCS0_OPR (1 << 0) /* OUT packet ready */

Definition at line 514 of file ixp4xx-regs.h.

#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */

Definition at line 520 of file ixp4xx-regs.h.

#define UDCCS0_SA (1 << 7) /* Setup active */

Definition at line 521 of file ixp4xx-regs.h.

#define UDCCS0_SST (1 << 4) /* Sent stall */

Definition at line 518 of file ixp4xx-regs.h.

#define UDCCS1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)

Definition at line 419 of file ixp4xx-regs.h.

#define UDCCS10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)

Definition at line 437 of file ixp4xx-regs.h.

#define UDCCS11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)

Definition at line 439 of file ixp4xx-regs.h.

#define UDCCS12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)

Definition at line 441 of file ixp4xx-regs.h.

#define UDCCS13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)

Definition at line 443 of file ixp4xx-regs.h.

#define UDCCS14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)

Definition at line 445 of file ixp4xx-regs.h.

#define UDCCS15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)

Definition at line 447 of file ixp4xx-regs.h.

#define UDCCS2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)

Definition at line 421 of file ixp4xx-regs.h.

#define UDCCS3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)

Definition at line 423 of file ixp4xx-regs.h.

#define UDCCS4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)

Definition at line 425 of file ixp4xx-regs.h.

#define UDCCS5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)

Definition at line 427 of file ixp4xx-regs.h.

#define UDCCS6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)

Definition at line 429 of file ixp4xx-regs.h.

#define UDCCS7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)

Definition at line 431 of file ixp4xx-regs.h.

#define UDCCS8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)

Definition at line 433 of file ixp4xx-regs.h.

#define UDCCS9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)

Definition at line 435 of file ixp4xx-regs.h.

#define UDCCS_BI_FST (1 << 5) /* Force stall */

Definition at line 528 of file ixp4xx-regs.h.

#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */

Definition at line 525 of file ixp4xx-regs.h.

#define UDCCS_BI_SST (1 << 4) /* Sent stall */

Definition at line 527 of file ixp4xx-regs.h.

#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */

Definition at line 523 of file ixp4xx-regs.h.

#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */

Definition at line 524 of file ixp4xx-regs.h.

#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */

Definition at line 529 of file ixp4xx-regs.h.

#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */

Definition at line 526 of file ixp4xx-regs.h.

#define UDCCS_BO_DME (1 << 3) /* DMA enable */

Definition at line 533 of file ixp4xx-regs.h.

#define UDCCS_BO_FST (1 << 5) /* Force stall */

Definition at line 535 of file ixp4xx-regs.h.

#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */

Definition at line 531 of file ixp4xx-regs.h.

#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */

Definition at line 536 of file ixp4xx-regs.h.

#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */

Definition at line 532 of file ixp4xx-regs.h.

#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */

Definition at line 537 of file ixp4xx-regs.h.

#define UDCCS_BO_SST (1 << 4) /* Sent stall */

Definition at line 534 of file ixp4xx-regs.h.

#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */

Definition at line 541 of file ixp4xx-regs.h.

#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */

Definition at line 539 of file ixp4xx-regs.h.

#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */

Definition at line 540 of file ixp4xx-regs.h.

#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */

Definition at line 543 of file ixp4xx-regs.h.

#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */

Definition at line 542 of file ixp4xx-regs.h.

#define UDCCS_INT_FST (1 << 5) /* Force stall */

Definition at line 557 of file ixp4xx-regs.h.

#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */

Definition at line 554 of file ixp4xx-regs.h.

#define UDCCS_INT_SST (1 << 4) /* Sent stall */

Definition at line 556 of file ixp4xx-regs.h.

#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */

Definition at line 552 of file ixp4xx-regs.h.

#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */

Definition at line 553 of file ixp4xx-regs.h.

#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */

Definition at line 558 of file ixp4xx-regs.h.

#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */

Definition at line 555 of file ixp4xx-regs.h.

#define UDCCS_IO_DME (1 << 3) /* DMA enable */

Definition at line 548 of file ixp4xx-regs.h.

#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */

Definition at line 545 of file ixp4xx-regs.h.

#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */

Definition at line 549 of file ixp4xx-regs.h.

#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */

Definition at line 547 of file ixp4xx-regs.h.

#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */

Definition at line 546 of file ixp4xx-regs.h.

#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */

Definition at line 550 of file ixp4xx-regs.h.

#define UDDR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)

Definition at line 465 of file ixp4xx-regs.h.

#define UDDR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)

Definition at line 467 of file ixp4xx-regs.h.

#define UDDR10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)

Definition at line 485 of file ixp4xx-regs.h.

#define UDDR11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)

Definition at line 487 of file ixp4xx-regs.h.

#define UDDR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)

Definition at line 489 of file ixp4xx-regs.h.

#define UDDR13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)

Definition at line 491 of file ixp4xx-regs.h.

#define UDDR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)

Definition at line 493 of file ixp4xx-regs.h.

#define UDDR15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)

Definition at line 495 of file ixp4xx-regs.h.

#define UDDR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)

Definition at line 469 of file ixp4xx-regs.h.

#define UDDR3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)

Definition at line 471 of file ixp4xx-regs.h.

#define UDDR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)

Definition at line 473 of file ixp4xx-regs.h.

#define UDDR5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)

Definition at line 475 of file ixp4xx-regs.h.

#define UDDR6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)

Definition at line 477 of file ixp4xx-regs.h.

#define UDDR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)

Definition at line 479 of file ixp4xx-regs.h.

#define UDDR8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)

Definition at line 481 of file ixp4xx-regs.h.

#define UDDR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)

Definition at line 483 of file ixp4xx-regs.h.

#define UFNRH IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)

Definition at line 449 of file ixp4xx-regs.h.

#define UFNRL IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)

Definition at line 451 of file ixp4xx-regs.h.

#define UICR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)

Definition at line 497 of file ixp4xx-regs.h.

#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */

Definition at line 560 of file ixp4xx-regs.h.

#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */

Definition at line 561 of file ixp4xx-regs.h.

#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */

Definition at line 562 of file ixp4xx-regs.h.

#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */

Definition at line 563 of file ixp4xx-regs.h.

#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */

Definition at line 564 of file ixp4xx-regs.h.

#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */

Definition at line 565 of file ixp4xx-regs.h.

#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */

Definition at line 566 of file ixp4xx-regs.h.

#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */

Definition at line 567 of file ixp4xx-regs.h.

#define UICR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)

Definition at line 499 of file ixp4xx-regs.h.

#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */

Definition at line 571 of file ixp4xx-regs.h.

#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */

Definition at line 572 of file ixp4xx-regs.h.

#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */

Definition at line 573 of file ixp4xx-regs.h.

#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */

Definition at line 574 of file ixp4xx-regs.h.

#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */

Definition at line 575 of file ixp4xx-regs.h.

#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */

Definition at line 576 of file ixp4xx-regs.h.

#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */

Definition at line 569 of file ixp4xx-regs.h.

#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */

Definition at line 570 of file ixp4xx-regs.h.

#define USIR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)

Definition at line 501 of file ixp4xx-regs.h.

#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */

Definition at line 578 of file ixp4xx-regs.h.

#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */

Definition at line 579 of file ixp4xx-regs.h.

#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */

Definition at line 580 of file ixp4xx-regs.h.

#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */

Definition at line 581 of file ixp4xx-regs.h.

#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */

Definition at line 582 of file ixp4xx-regs.h.

#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */

Definition at line 583 of file ixp4xx-regs.h.

#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */

Definition at line 584 of file ixp4xx-regs.h.

#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */

Definition at line 585 of file ixp4xx-regs.h.

#define USIR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)

Definition at line 503 of file ixp4xx-regs.h.

#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */

Definition at line 589 of file ixp4xx-regs.h.

#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */

Definition at line 590 of file ixp4xx-regs.h.

#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */

Definition at line 591 of file ixp4xx-regs.h.

#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */

Definition at line 592 of file ixp4xx-regs.h.

#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */

Definition at line 593 of file ixp4xx-regs.h.

#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */

Definition at line 594 of file ixp4xx-regs.h.

#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */

Definition at line 587 of file ixp4xx-regs.h.

#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */

Definition at line 588 of file ixp4xx-regs.h.

Macros

Macro Definition Documentation