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common.h
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1 /*******************************************************************************
2  STMMAC Common Header File
3 
4  Copyright (C) 2007-2009 STMicroelectronics Ltd
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13  more details.
14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21 
22  Author: Giuseppe Cavallaro <[email protected]>
23 *******************************************************************************/
24 
25 #ifndef __COMMON_H__
26 #define __COMMON_H__
27 
28 #include <linux/etherdevice.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
34 #define STMMAC_VLAN_TAG_USED
35 #include <linux/if_vlan.h>
36 #endif
37 
38 #include "descs.h"
39 #include "mmc.h"
40 
41 #undef CHIP_DEBUG_PRINT
42 /* Turn-on extra printk debug for MAC core, dma and descriptors */
43 /* #define CHIP_DEBUG_PRINT */
44 
45 #ifdef CHIP_DEBUG_PRINT
46 #define CHIP_DBG(fmt, args...) printk(fmt, ## args)
47 #else
48 #define CHIP_DBG(fmt, args...) do { } while (0)
49 #endif
50 
51 #undef FRAME_FILTER_DEBUG
52 /* #define FRAME_FILTER_DEBUG */
53 
55  /* Transmit errors */
56  unsigned long tx_underflow ____cacheline_aligned;
57  unsigned long tx_carrier;
58  unsigned long tx_losscarrier;
59  unsigned long vlan_tag;
60  unsigned long tx_deferred;
61  unsigned long tx_vlan;
62  unsigned long tx_jabber;
63  unsigned long tx_frame_flushed;
64  unsigned long tx_payload_error;
65  unsigned long tx_ip_header_error;
66  /* Receive errors */
67  unsigned long rx_desc;
68  unsigned long sa_filter_fail;
69  unsigned long overflow_error;
70  unsigned long ipc_csum_error;
71  unsigned long rx_collision;
72  unsigned long rx_crc;
73  unsigned long dribbling_bit;
74  unsigned long rx_length;
75  unsigned long rx_mii;
76  unsigned long rx_multicast;
77  unsigned long rx_gmac_overflow;
78  unsigned long rx_watchdog;
79  unsigned long da_rx_filter_fail;
80  unsigned long sa_rx_filter_fail;
81  unsigned long rx_missed_cntr;
82  unsigned long rx_overflow_cntr;
83  unsigned long rx_vlan;
84  /* Tx/Rx IRQ errors */
85  unsigned long tx_undeflow_irq;
86  unsigned long tx_process_stopped_irq;
87  unsigned long tx_jabber_irq;
88  unsigned long rx_overflow_irq;
89  unsigned long rx_buf_unav_irq;
90  unsigned long rx_process_stopped_irq;
91  unsigned long rx_watchdog_irq;
92  unsigned long tx_early_irq;
93  unsigned long fatal_bus_error_irq;
94  /* Extra info */
95  unsigned long threshold;
96  unsigned long tx_pkt_n;
97  unsigned long rx_pkt_n;
98  unsigned long poll_n;
99  unsigned long sched_timer_n;
100  unsigned long normal_irq_n;
101  unsigned long mmc_tx_irq_n;
102  unsigned long mmc_rx_irq_n;
104  /* EEE */
105  unsigned long irq_receive_pmt_irq_n;
110  unsigned long phy_eee_wakeup_error_n;
111 };
112 
113 /* CSR Frequency Access Defines*/
114 #define CSR_F_35M 35000000
115 #define CSR_F_60M 60000000
116 #define CSR_F_100M 100000000
117 #define CSR_F_150M 150000000
118 #define CSR_F_250M 250000000
119 #define CSR_F_300M 300000000
120 
121 #define MAC_CSR_H_FRQ_MASK 0x20
122 
123 #define HASH_TABLE_SIZE 64
124 #define PAUSE_TIME 0x200
125 
126 /* Flow Control defines */
127 #define FLOW_OFF 0
128 #define FLOW_RX 1
129 #define FLOW_TX 2
130 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
131 
132 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
133 
134 /* DAM HW feature register fields */
135 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
136 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
137 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
138 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
139 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
140 #define DMA_HW_FEAT_ADDMACADRSEL 0x00000020 /* Multiple MAC Addr Reg */
141 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
142 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
143 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
144 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
145 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
146 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
147 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 Timestamp */
148 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 Adv Timestamp */
149 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
150 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
151 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
152 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP csum Offload(Type 1) in Rx */
153 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP csum Offload(Type 2) in Rx */
154 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
155 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. of additional Rx Channels */
156 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. of additional Tx Channels */
157 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate (Enhanced Descriptor) */
158 #define DMA_HW_FEAT_INTTSEN 0x02000000 /* Timestamping with Internal
159  System Time */
160 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
161 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN Insertion */
162 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY interface */
163 #define DEFAULT_DMA_PBL 8
165 enum rx_frame_status { /* IPC status */
169  llc_snap = 4,
170 };
175  handle_tx_rx = 3,
176 };
187 };
188 
189 /* DMA HW capabilities */
190 struct dma_features {
191  unsigned int mbps_10_100;
192  unsigned int mbps_1000;
193  unsigned int half_duplex;
194  unsigned int hash_filter;
195  unsigned int multi_addr;
196  unsigned int pcs;
197  unsigned int sma_mdio;
198  unsigned int pmt_remote_wake_up;
199  unsigned int pmt_magic_frame;
200  unsigned int rmon;
201  /* IEEE 1588-2002*/
202  unsigned int time_stamp;
203  /* IEEE 1588-2008*/
204  unsigned int atime_stamp;
205  /* 802.3az - Energy-Efficient Ethernet (EEE) */
206  unsigned int eee;
207  unsigned int av;
208  /* TX and RX csum */
209  unsigned int tx_coe;
210  unsigned int rx_coe_type1;
211  unsigned int rx_coe_type2;
212  unsigned int rxfifo_over_2048;
213  /* TX and RX number of channels */
214  unsigned int number_rx_channel;
215  unsigned int number_tx_channel;
216  /* Alternate (enhanced) DESC mode*/
217  unsigned int enh_desc;
218 };
219 
220 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
221 #define BUF_SIZE_16KiB 16384
222 #define BUF_SIZE_8KiB 8192
223 #define BUF_SIZE_4KiB 4096
224 #define BUF_SIZE_2KiB 2048
225 
226 /* Power Down and WOL */
227 #define PMT_NOT_SUPPORTED 0
228 #define PMT_SUPPORTED 1
229 
230 /* Common MAC defines */
231 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
232 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
233 #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
234 
235 /* Default LPI timers */
236 #define STMMAC_DEFAULT_LIT_LS_TIMER 0x3E8
237 #define STMMAC_DEFAULT_TWT_LS_TIMER 0x0
239 struct stmmac_desc_ops {
240  /* DMA RX descriptor ring initialization */
241  void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
242  int disable_rx_ic);
243  /* DMA TX descriptor ring initialization */
244  void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);
245 
246  /* Invoked by the xmit function to prepare the tx descriptor */
247  void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
248  int csum_flag);
249  /* Set/get the owner of the descriptor */
250  void (*set_tx_owner) (struct dma_desc *p);
251  int (*get_tx_owner) (struct dma_desc *p);
252  /* Invoked by the xmit function to close the tx descriptor */
253  void (*close_tx_desc) (struct dma_desc *p);
254  /* Clean the tx descriptor as soon as the tx irq is received */
255  void (*release_tx_desc) (struct dma_desc *p);
256  /* Clear interrupt on tx frame completion. When this bit is
257  * set an interrupt happens as soon as the frame is transmitted */
258  void (*clear_tx_ic) (struct dma_desc *p);
259  /* Last tx segment reports the transmit status */
260  int (*get_tx_ls) (struct dma_desc *p);
261  /* Return the transmit status looking at the TDES1 */
262  int (*tx_status) (void *data, struct stmmac_extra_stats *x,
263  struct dma_desc *p, void __iomem *ioaddr);
264  /* Get the buffer size from the descriptor */
265  int (*get_tx_len) (struct dma_desc *p);
266  /* Handle extra events on specific interrupts hw dependent */
267  int (*get_rx_owner) (struct dma_desc *p);
268  void (*set_rx_owner) (struct dma_desc *p);
269  /* Get the receive frame size */
270  int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
271  /* Return the reception status looking at the RDES1 */
272  int (*rx_status) (void *data, struct stmmac_extra_stats *x,
273  struct dma_desc *p);
274 };
276 struct stmmac_dma_ops {
277  /* DMA core initialization */
278  int (*init) (void __iomem *ioaddr, int pbl, int fb, int mb,
279  int burst_len, u32 dma_tx, u32 dma_rx);
280  /* Dump DMA registers */
281  void (*dump_regs) (void __iomem *ioaddr);
282  /* Set tx/rx threshold in the csr6 register
283  * An invalid value enables the store-and-forward mode */
284  void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
285  /* To track extra statistic (if supported) */
286  void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
287  void __iomem *ioaddr);
289  void (*enable_dma_irq) (void __iomem *ioaddr);
290  void (*disable_dma_irq) (void __iomem *ioaddr);
291  void (*start_tx) (void __iomem *ioaddr);
292  void (*stop_tx) (void __iomem *ioaddr);
293  void (*start_rx) (void __iomem *ioaddr);
294  void (*stop_rx) (void __iomem *ioaddr);
295  int (*dma_interrupt) (void __iomem *ioaddr,
296  struct stmmac_extra_stats *x);
297  /* If supported then get the optional core features */
298  unsigned int (*get_hw_feature) (void __iomem *ioaddr);
299 };
301 struct stmmac_ops {
302  /* MAC core initialization */
303  void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned;
304  /* Enable and verify that the IPC module is supported */
305  int (*rx_ipc) (void __iomem *ioaddr);
306  /* Dump MAC registers */
307  void (*dump_regs) (void __iomem *ioaddr);
308  /* Handle extra events on specific interrupts hw dependent */
309  int (*host_irq_status) (void __iomem *ioaddr);
310  /* Multicast filter setting */
311  void (*set_filter) (struct net_device *dev, int id);
312  /* Flow control setting */
313  void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
314  unsigned int fc, unsigned int pause_time);
315  /* Set power management mode (e.g. magic frame) */
316  void (*pmt) (void __iomem *ioaddr, unsigned long mode);
317  /* Set/Get Unicast MAC addresses */
318  void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
319  unsigned int reg_n);
320  void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
321  unsigned int reg_n);
322  void (*set_eee_mode) (void __iomem *ioaddr);
323  void (*reset_eee_mode) (void __iomem *ioaddr);
324  void (*set_eee_timer) (void __iomem *ioaddr, int ls, int tw);
325  void (*set_eee_pls) (void __iomem *ioaddr, int link);
326 };
328 struct mac_link {
329  int port;
330  int duplex;
331  int speed;
332 };
334 struct mii_regs {
335  unsigned int addr; /* MII Address */
336  unsigned int data; /* MII Data */
337 };
340  unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
341  unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
342  void (*refill_desc3) (int bfsize, struct dma_desc *p);
343  void (*init_desc3) (int des3_as_data_buf, struct dma_desc *p);
344  void (*init_dma_chain) (struct dma_desc *des, dma_addr_t phy_addr,
345  unsigned int size);
346  void (*clean_desc3) (struct dma_desc *p);
347  int (*set_16kib_bfsize) (int mtu);
348 };
351  const struct stmmac_ops *mac;
352  const struct stmmac_desc_ops *desc;
353  const struct stmmac_dma_ops *dma;
354  const struct stmmac_ring_mode_ops *ring;
355  struct mii_regs mii; /* MII register Addresses */
356  struct mac_link link;
357  unsigned int synopsys_uid;
358 };
359 
360 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
361 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
362 
363 extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
364  unsigned int high, unsigned int low);
365 extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
366  unsigned int high, unsigned int low);
367 
368 extern void stmmac_set_mac(void __iomem *ioaddr, bool enable);
369 
370 extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
371 extern const struct stmmac_ring_mode_ops ring_mode_ops;
372 
373 #endif /* __COMMON_H__ */