#include <linux/pci.h>
#include <linux/pcieport_if.h>
#include <linux/interrupt.h>
#include "main.h"
Go to the source code of this file.
| #define CPU_INTR_DNLD_RDY BIT(0) |
| #define CPU_INTR_DOOR_BELL BIT(1) |
| #define CPU_INTR_RESET BIT(3) |
| #define CPU_INTR_SLEEP_CFM_DONE BIT(2) |
| #define FW_AWAKE_COOKIE (0xAA55AA55) |
| #define HOST_INTR_CMD_DONE BIT(2) |
| #define HOST_INTR_DNLD_DONE BIT(0) |
| #define HOST_INTR_EVENT_RDY BIT(3) |
Value:
HOST_INTR_UPLD_RDY | \
HOST_INTR_CMD_DONE | \
HOST_INTR_EVENT_RDY)
Definition at line 70 of file pcie.h.
| #define HOST_INTR_UPLD_RDY BIT(1) |
| #define MAX_WRITE_IOMEM_RETRY 2 |
| #define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0) |
| #define MWIFIEX_BD_FLAG_LAST_DESC BIT(1) |
| #define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7) |
| #define MWIFIEX_EVTBD_MASK 0x07 |
| #define MWIFIEX_MAX_EVT_BD 0x04 |
| #define MWIFIEX_MAX_TXRX_BD 0x20 |
| #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256 |
| #define MWIFIEX_RXBD_MASK 0x3F |
| #define MWIFIEX_TXBD_MASK 0x3F |
| #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin" |
| #define PCIE_CPU_INT_EVENT 0xC18 |
| #define PCIE_CPU_INT_STATUS 0xC1C |
| #define PCIE_HOST_INT_MASK 0xC34 |
| #define PCIE_HOST_INT_STATUS 0xC30 |
| #define PCIE_HOST_INT_STATUS_MASK 0xC3C |
| #define PCIE_SCRATCH_0_REG 0xC10 |
| #define PCIE_SCRATCH_10_REG 0xCE8 |
| #define PCIE_SCRATCH_11_REG 0xCEC |
| #define PCIE_SCRATCH_12_REG 0xCF0 |
| #define PCIE_SCRATCH_1_REG 0xC14 |
| #define PCIE_SCRATCH_2_REG 0xC40 |
| #define PCIE_SCRATCH_3_REG 0xC44 |
| #define PCIE_SCRATCH_4_REG 0xCD0 |
| #define PCIE_SCRATCH_5_REG 0xCD4 |
| #define PCIE_SCRATCH_6_REG 0xCD8 |
| #define PCIE_SCRATCH_7_REG 0xCDC |
| #define PCIE_SCRATCH_8_REG 0xCE0 |
| #define PCIE_SCRATCH_9_REG 0xCE4 |
1.8.2