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Macros
reg.h File Reference

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Macros

#define REG_SYS_ISO_CTRL   0x0000
 
#define REG_SYS_FUNC_EN   0x0002
 
#define REG_APS_FSMCO   0x0004
 
#define REG_SYS_CLKR   0x0008
 
#define REG_9346CR   0x000A
 
#define REG_EE_VPD   0x000C
 
#define REG_AFE_MISC   0x0010
 
#define REG_SPS0_CTRL   0x0011
 
#define REG_POWER_OFF_IN_PROCESS   0x0017
 
#define REG_SPS_OCP_CFG   0x0018
 
#define REG_RSV_CTRL   0x001C
 
#define REG_RF_CTRL   0x001F
 
#define REG_LDOA15_CTRL   0x0020
 
#define REG_LDOV12D_CTRL   0x0021
 
#define REG_LDOHCI12_CTRL   0x0022
 
#define REG_LPLDO_CTRL   0x0023
 
#define REG_AFE_XTAL_CTRL   0x0024
 
#define REG_AFE_PLL_CTRL   0x0028
 
#define REG_MAC_PHY_CTRL   0x002c
 
#define REG_EFUSE_CTRL   0x0030
 
#define REG_EFUSE_TEST   0x0034
 
#define REG_PWR_DATA   0x0038
 
#define REG_CAL_TIMER   0x003C
 
#define REG_ACLK_MON   0x003E
 
#define REG_GPIO_MUXCFG   0x0040
 
#define REG_GPIO_IO_SEL   0x0042
 
#define REG_MAC_PINMUX_CFG   0x0043
 
#define REG_GPIO_PIN_CTRL   0x0044
 
#define REG_GPIO_INTM   0x0048
 
#define REG_LEDCFG0   0x004C
 
#define REG_LEDCFG1   0x004D
 
#define REG_LEDCFG2   0x004E
 
#define REG_LEDCFG3   0x004F
 
#define REG_FSIMR   0x0050
 
#define REG_FSISR   0x0054
 
#define REG_MCUFWDL   0x0080
 
#define REG_HMEBOX_EXT_0   0x0088
 
#define REG_HMEBOX_EXT_1   0x008A
 
#define REG_HMEBOX_EXT_2   0x008C
 
#define REG_HMEBOX_EXT_3   0x008E
 
#define REG_BIST_SCAN   0x00D0
 
#define REG_BIST_RPT   0x00D4
 
#define REG_BIST_ROM_RPT   0x00D8
 
#define REG_USB_SIE_INTF   0x00E0
 
#define REG_PCIE_MIO_INTF   0x00E4
 
#define REG_PCIE_MIO_INTD   0x00E8
 
#define REG_HPON_FSM   0x00EC
 
#define REG_SYS_CFG   0x00F0
 
#define REG_MAC_PHY_CTRL_NORMAL   0x00f8
 
#define REG_MAC0   0x0081
 
#define REG_MAC1   0x0053
 
#define FW_MAC0_READY   0x18
 
#define FW_MAC1_READY   0x1A
 
#define MAC0_ON   BIT(7)
 
#define MAC1_ON   BIT(0)
 
#define MAC0_READY   BIT(0)
 
#define MAC1_READY   BIT(0)
 
#define REG_CR   0x0100
 
#define REG_PBP   0x0104
 
#define REG_TRXDMA_CTRL   0x010C
 
#define REG_TRXFF_BNDY   0x0114
 
#define REG_TRXFF_STATUS   0x0118
 
#define REG_RXFF_PTR   0x011C
 
#define REG_HIMR   0x0120
 
#define REG_HISR   0x0124
 
#define REG_HIMRE   0x0128
 
#define REG_HISRE   0x012C
 
#define REG_CPWM   0x012F
 
#define REG_FWIMR   0x0130
 
#define REG_FWISR   0x0134
 
#define REG_PKTBUF_DBG_CTRL   0x0140
 
#define REG_PKTBUF_DBG_DATA_L   0x0144
 
#define REG_PKTBUF_DBG_DATA_H   0x0148
 
#define REG_TC0_CTRL   0x0150
 
#define REG_TC1_CTRL   0x0154
 
#define REG_TC2_CTRL   0x0158
 
#define REG_TC3_CTRL   0x015C
 
#define REG_TC4_CTRL   0x0160
 
#define REG_TCUNIT_BASE   0x0164
 
#define REG_MBIST_START   0x0174
 
#define REG_MBIST_DONE   0x0178
 
#define REG_MBIST_FAIL   0x017C
 
#define REG_C2HEVT_MSG_NORMAL   0x01A0
 
#define REG_C2HEVT_MSG_TEST   0x01B8
 
#define REG_C2HEVT_CLEAR   0x01BF
 
#define REG_MCUTST_1   0x01c0
 
#define REG_FMETHR   0x01C8
 
#define REG_HMETFR   0x01CC
 
#define REG_HMEBOX_0   0x01D0
 
#define REG_HMEBOX_1   0x01D4
 
#define REG_HMEBOX_2   0x01D8
 
#define REG_HMEBOX_3   0x01DC
 
#define REG_LLT_INIT   0x01E0
 
#define REG_BB_ACCEESS_CTRL   0x01E8
 
#define REG_BB_ACCESS_DATA   0x01EC
 
#define REG_RQPN   0x0200
 
#define REG_FIFOPAGE   0x0204
 
#define REG_TDECTRL   0x0208
 
#define REG_TXDMA_OFFSET_CHK   0x020C
 
#define REG_TXDMA_STATUS   0x0210
 
#define REG_RQPN_NPQ   0x0214
 
#define REG_RXDMA_AGG_PG_TH   0x0280
 
#define REG_RXPKT_NUM   0x0284
 
#define REG_RXDMA_STATUS   0x0288
 
#define REG_PCIE_CTRL_REG   0x0300
 
#define REG_INT_MIG   0x0304
 
#define REG_BCNQ_DESA   0x0308
 
#define REG_HQ_DESA   0x0310
 
#define REG_MGQ_DESA   0x0318
 
#define REG_VOQ_DESA   0x0320
 
#define REG_VIQ_DESA   0x0328
 
#define REG_BEQ_DESA   0x0330
 
#define REG_BKQ_DESA   0x0338
 
#define REG_RX_DESA   0x0340
 
#define REG_DBI   0x0348
 
#define REG_DBI_WDATA   0x0348
 
#define REG_DBI_RDATA   0x034C
 
#define REG_DBI_CTRL   0x0350
 
#define REG_DBI_FLAG   0x0352
 
#define REG_MDIO   0x0354
 
#define REG_DBG_SEL   0x0360
 
#define REG_PCIE_HRPWM   0x0361
 
#define REG_PCIE_HCPWM   0x0363
 
#define REG_UART_CTRL   0x0364
 
#define REG_UART_TX_DESA   0x0370
 
#define REG_UART_RX_DESA   0x0378
 
#define REG_VOQ_INFORMATION   0x0400
 
#define REG_VIQ_INFORMATION   0x0404
 
#define REG_BEQ_INFORMATION   0x0408
 
#define REG_BKQ_INFORMATION   0x040C
 
#define REG_MGQ_INFORMATION   0x0410
 
#define REG_HGQ_INFORMATION   0x0414
 
#define REG_BCNQ_INFORMATION   0x0418
 
#define REG_CPU_MGQ_INFORMATION   0x041C
 
#define REG_FWHW_TXQ_CTRL   0x0420
 
#define REG_HWSEQ_CTRL   0x0423
 
#define REG_TXPKTBUF_BCNQ_BDNY   0x0424
 
#define REG_TXPKTBUF_MGQ_BDNY   0x0425
 
#define REG_MULTI_BCNQ_EN   0x0426
 
#define REG_MULTI_BCNQ_OFFSET   0x0427
 
#define REG_SPEC_SIFS   0x0428
 
#define REG_RL   0x042A
 
#define REG_DARFRC   0x0430
 
#define REG_RARFRC   0x0438
 
#define REG_RRSR   0x0440
 
#define REG_ARFR0   0x0444
 
#define REG_ARFR1   0x0448
 
#define REG_ARFR2   0x044C
 
#define REG_ARFR3   0x0450
 
#define REG_AGGLEN_LMT   0x0458
 
#define REG_AMPDU_MIN_SPACE   0x045C
 
#define REG_TXPKTBUF_WMAC_LBK_BF_HD   0x045D
 
#define REG_FAST_EDCA_CTRL   0x0460
 
#define REG_RD_RESP_PKT_TH   0x0463
 
#define REG_INIRTS_RATE_SEL   0x0480
 
#define REG_INIDATA_RATE_SEL   0x0484
 
#define REG_POWER_STATUS   0x04A4
 
#define REG_POWER_STAGE1   0x04B4
 
#define REG_POWER_STAGE2   0x04B8
 
#define REG_PKT_LIFE_TIME   0x04C0
 
#define REG_STBC_SETTING   0x04C4
 
#define REG_PROT_MODE_CTRL   0x04C8
 
#define REG_MAX_AGGR_NUM   0x04CA
 
#define REG_RTS_MAX_AGGR_NUM   0x04CB
 
#define REG_BAR_MODE_CTRL   0x04CC
 
#define REG_RA_TRY_RATE_AGG_LMT   0x04CF
 
#define REG_EARLY_MODE_CONTROL   0x4D0
 
#define REG_NQOS_SEQ   0x04DC
 
#define REG_QOS_SEQ   0x04DE
 
#define REG_NEED_CPU_HANDLE   0x04E0
 
#define REG_PKT_LOSE_RPT   0x04E1
 
#define REG_PTCL_ERR_STATUS   0x04E2
 
#define REG_DUMMY   0x04FC
 
#define REG_EDCA_VO_PARAM   0x0500
 
#define REG_EDCA_VI_PARAM   0x0504
 
#define REG_EDCA_BE_PARAM   0x0508
 
#define REG_EDCA_BK_PARAM   0x050C
 
#define REG_BCNTCFG   0x0510
 
#define REG_PIFS   0x0512
 
#define REG_RDG_PIFS   0x0513
 
#define REG_SIFS_CTX   0x0514
 
#define REG_SIFS_TRX   0x0516
 
#define REG_AGGR_BREAK_TIME   0x051A
 
#define REG_SLOT   0x051B
 
#define REG_TX_PTCL_CTRL   0x0520
 
#define REG_TXPAUSE   0x0522
 
#define REG_DIS_TXREQ_CLR   0x0523
 
#define REG_RD_CTRL   0x0524
 
#define REG_TBTT_PROHIBIT   0x0540
 
#define REG_RD_NAV_NXT   0x0544
 
#define REG_NAV_PROT_LEN   0x0546
 
#define REG_BCN_CTRL   0x0550
 
#define REG_USTIME_TSF   0x0551
 
#define REG_MBID_NUM   0x0552
 
#define REG_DUAL_TSF_RST   0x0553
 
#define REG_BCN_INTERVAL   0x0554
 
#define REG_MBSSID_BCN_SPACE   0x0554
 
#define REG_DRVERLYINT   0x0558
 
#define REG_BCNDMATIM   0x0559
 
#define REG_ATIMWND   0x055A
 
#define REG_BCN_MAX_ERR   0x055D
 
#define REG_RXTSF_OFFSET_CCK   0x055E
 
#define REG_RXTSF_OFFSET_OFDM   0x055F
 
#define REG_TSFTR   0x0560
 
#define REG_INIT_TSFTR   0x0564
 
#define REG_PSTIMER   0x0580
 
#define REG_TIMER0   0x0584
 
#define REG_TIMER1   0x0588
 
#define REG_ACMHWCTRL   0x05C0
 
#define REG_ACMRSTCTRL   0x05C1
 
#define REG_ACMAVG   0x05C2
 
#define REG_VO_ADMTIME   0x05C4
 
#define REG_VI_ADMTIME   0x05C6
 
#define REG_BE_ADMTIME   0x05C8
 
#define REG_EDCA_RANDOM_GEN   0x05CC
 
#define REG_SCH_TXCMD   0x05D0
 
#define REG_DMC   0x05F0
 
#define REG_APSD_CTRL   0x0600
 
#define REG_BWOPMODE   0x0603
 
#define REG_TCR   0x0604
 
#define REG_RCR   0x0608
 
#define REG_RX_PKT_LIMIT   0x060C
 
#define REG_RX_DLK_TIME   0x060D
 
#define REG_RX_DRVINFO_SZ   0x060F
 
#define REG_MACID   0x0610
 
#define REG_BSSID   0x0618
 
#define REG_MAR   0x0620
 
#define REG_MBIDCAMCFG   0x0628
 
#define REG_USTIME_EDCA   0x0638
 
#define REG_MAC_SPEC_SIFS   0x063A
 
#define REG_RESP_SIFS_CCK   0x063C
 
#define REG_RESP_SIFS_OFDM   0x063E
 
#define REG_ACKTO   0x0640
 
#define REG_CTS2TO   0x0641
 
#define REG_EIFS   0x0642
 
#define REG_NAV_CTRL   0x0650
 
#define REG_BACAMCMD   0x0654
 
#define REG_BACAMCONTENT   0x0658
 
#define REG_LBDLY   0x0660
 
#define REG_FWDLY   0x0661
 
#define REG_RXERR_RPT   0x0664
 
#define REG_WMAC_TRXPTCL_CTL   0x0668
 
#define REG_CAMCMD   0x0670
 
#define REG_CAMWRITE   0x0674
 
#define REG_CAMREAD   0x0678
 
#define REG_CAMDBG   0x067C
 
#define REG_SECCFG   0x0680
 
#define REG_WOW_CTRL   0x0690
 
#define REG_PSSTATUS   0x0691
 
#define REG_PS_RX_INFO   0x0692
 
#define REG_LPNAV_CTRL   0x0694
 
#define REG_WKFMCAM_CMD   0x0698
 
#define REG_WKFMCAM_RWD   0x069C
 
#define REG_RXFLTMAP0   0x06A0
 
#define REG_RXFLTMAP1   0x06A2
 
#define REG_RXFLTMAP2   0x06A4
 
#define REG_BCN_PSR_RPT   0x06A8
 
#define REG_CALB32K_CTRL   0x06AC
 
#define REG_PKT_MON_CTRL   0x06B4
 
#define REG_BT_COEX_TABLE   0x06C0
 
#define REG_WMAC_RESP_TXINFO   0x06D8
 
#define CR9346   REG_9346CR
 
#define MSR   (REG_CR + 2)
 
#define ISR   REG_HISR
 
#define TSFR   REG_TSFTR
 
#define MACIDR0   REG_MACID
 
#define MACIDR4   (REG_MACID + 4)
 
#define PBP   REG_PBP
 
#define IDR0   MACIDR0
 
#define IDR4   MACIDR4
 
#define MSR_NOLINK   0x00
 
#define MSR_ADHOC   0x01
 
#define MSR_INFRA   0x02
 
#define MSR_AP   0x03
 
#define RRSR_RSC_OFFSET   21
 
#define RRSR_SHORT_OFFSET   23
 
#define RRSR_RSC_BW_40M   0x600000
 
#define RRSR_RSC_UPSUBCHNL   0x400000
 
#define RRSR_RSC_LOWSUBCHNL   0x200000
 
#define RRSR_SHORT   0x800000
 
#define RRSR_1M   BIT0
 
#define RRSR_2M   BIT1
 
#define RRSR_5_5M   BIT2
 
#define RRSR_11M   BIT3
 
#define RRSR_6M   BIT4
 
#define RRSR_9M   BIT5
 
#define RRSR_12M   BIT6
 
#define RRSR_18M   BIT7
 
#define RRSR_24M   BIT8
 
#define RRSR_36M   BIT9
 
#define RRSR_48M   BIT10
 
#define RRSR_54M   BIT11
 
#define RRSR_MCS0   BIT12
 
#define RRSR_MCS1   BIT13
 
#define RRSR_MCS2   BIT14
 
#define RRSR_MCS3   BIT15
 
#define RRSR_MCS4   BIT16
 
#define RRSR_MCS5   BIT17
 
#define RRSR_MCS6   BIT18
 
#define RRSR_MCS7   BIT19
 
#define BRSR_ACKSHORTPMB   BIT23
 
#define RATR_1M   0x00000001
 
#define RATR_2M   0x00000002
 
#define RATR_55M   0x00000004
 
#define RATR_11M   0x00000008
 
#define RATR_6M   0x00000010
 
#define RATR_9M   0x00000020
 
#define RATR_12M   0x00000040
 
#define RATR_18M   0x00000080
 
#define RATR_24M   0x00000100
 
#define RATR_36M   0x00000200
 
#define RATR_48M   0x00000400
 
#define RATR_54M   0x00000800
 
#define RATR_MCS0   0x00001000
 
#define RATR_MCS1   0x00002000
 
#define RATR_MCS2   0x00004000
 
#define RATR_MCS3   0x00008000
 
#define RATR_MCS4   0x00010000
 
#define RATR_MCS5   0x00020000
 
#define RATR_MCS6   0x00040000
 
#define RATR_MCS7   0x00080000
 
#define RATR_MCS8   0x00100000
 
#define RATR_MCS9   0x00200000
 
#define RATR_MCS10   0x00400000
 
#define RATR_MCS11   0x00800000
 
#define RATR_MCS12   0x01000000
 
#define RATR_MCS13   0x02000000
 
#define RATR_MCS14   0x04000000
 
#define RATR_MCS15   0x08000000
 
#define RATE_1M   BIT(0)
 
#define RATE_2M   BIT(1)
 
#define RATE_5_5M   BIT(2)
 
#define RATE_11M   BIT(3)
 
#define RATE_6M   BIT(4)
 
#define RATE_9M   BIT(5)
 
#define RATE_12M   BIT(6)
 
#define RATE_18M   BIT(7)
 
#define RATE_24M   BIT(8)
 
#define RATE_36M   BIT(9)
 
#define RATE_48M   BIT(10)
 
#define RATE_54M   BIT(11)
 
#define RATE_MCS0   BIT(12)
 
#define RATE_MCS1   BIT(13)
 
#define RATE_MCS2   BIT(14)
 
#define RATE_MCS3   BIT(15)
 
#define RATE_MCS4   BIT(16)
 
#define RATE_MCS5   BIT(17)
 
#define RATE_MCS6   BIT(18)
 
#define RATE_MCS7   BIT(19)
 
#define RATE_MCS8   BIT(20)
 
#define RATE_MCS9   BIT(21)
 
#define RATE_MCS10   BIT(22)
 
#define RATE_MCS11   BIT(23)
 
#define RATE_MCS12   BIT(24)
 
#define RATE_MCS13   BIT(25)
 
#define RATE_MCS14   BIT(26)
 
#define RATE_MCS15   BIT(27)
 
#define RATE_ALL_CCK
 
#define RATE_ALL_OFDM_AG
 
#define RATE_ALL_OFDM_1SS
 
#define RATE_ALL_OFDM_2SS
 
#define BW_OPMODE_20MHZ   BIT(2)
 
#define BW_OPMODE_5G   BIT(1)
 
#define BW_OPMODE_11J   BIT(0)
 
#define CAM_VALID   BIT(15)
 
#define CAM_NOTVALID   0x0000
 
#define CAM_USEDK   BIT(5)
 
#define CAM_NONE   0x0
 
#define CAM_WEP40   0x01
 
#define CAM_TKIP   0x02
 
#define CAM_AES   0x04
 
#define CAM_WEP104   0x05
 
#define CAM_SMS4   0x6
 
#define TOTAL_CAM_ENTRY   32
 
#define HALF_CAM_ENTRY   16
 
#define CAM_WRITE   BIT(16)
 
#define CAM_READ   0x00000000
 
#define CAM_POLLINIG   BIT(31)
 
#define WOW_PMEN   BIT0 /* Power management Enable. */
 
#define WOW_WOMEN   BIT1 /* WoW function on or off. */
 
#define WOW_MAGIC   BIT2 /* Magic packet */
 
#define WOW_UWF   BIT3 /* Unicast Wakeup frame. */
 
#define IMR8190_DISABLED   0x0
 
#define IMR_BCNDMAINT6   BIT(31)
 
#define IMR_BCNDMAINT5   BIT(30)
 
#define IMR_BCNDMAINT4   BIT(29)
 
#define IMR_BCNDMAINT3   BIT(28)
 
#define IMR_BCNDMAINT2   BIT(27)
 
#define IMR_BCNDMAINT1   BIT(26)
 
#define IMR_BCNDOK8   BIT(25)
 
#define IMR_BCNDOK7   BIT(24)
 
#define IMR_BCNDOK6   BIT(23)
 
#define IMR_BCNDOK5   BIT(22)
 
#define IMR_BCNDOK4   BIT(21)
 
#define IMR_BCNDOK3   BIT(20)
 
#define IMR_BCNDOK2   BIT(19)
 
#define IMR_BCNDOK1   BIT(18)
 
#define IMR_TIMEOUT2   BIT(17)
 
#define IMR_TIMEOUT1   BIT(16)
 
#define IMR_TXFOVW   BIT(15)
 
#define IMR_PSTIMEOUT   BIT(14)
 
#define IMR_BcnInt   BIT(13)
 
#define IMR_RXFOVW   BIT(12)
 
#define IMR_RDU   BIT(11)
 
#define IMR_ATIMEND   BIT(10)
 
#define IMR_BDOK   BIT(9)
 
#define IMR_HIGHDOK   BIT(8)
 
#define IMR_TBDOK   BIT(7)
 
#define IMR_MGNTDOK   BIT(6)
 
#define IMR_TBDER   BIT(5)
 
#define IMR_BKDOK   BIT(4)
 
#define IMR_BEDOK   BIT(3)
 
#define IMR_VIDOK   BIT(2)
 
#define IMR_VODOK   BIT(1)
 
#define IMR_ROK   BIT(0)
 
#define IMR_TXERR   BIT(11)
 
#define IMR_RXERR   BIT(10)
 
#define IMR_C2HCMD   BIT(9)
 
#define IMR_CPWM   BIT(8)
 
#define IMR_OCPINT   BIT(1)
 
#define IMR_WLANOFF   BIT(0)
 
#define HWSET_MAX_SIZE   256
 
#define EFUSE_MAX_SECTION   32
 
#define EFUSE_REAL_CONTENT_LEN   512
 
#define EEPROM_DEFAULT_TSSI   0x0
 
#define EEPROM_DEFAULT_CRYSTALCAP   0x0
 
#define EEPROM_DEFAULT_THERMALMETER   0x12
 
#define EEPROM_DEFAULT_TXPOWERLEVEL_2G   0x2C
 
#define EEPROM_DEFAULT_TXPOWERLEVEL_5G   0x22
 
#define EEPROM_DEFAULT_HT40_2SDIFF   0x0
 
#define EEPROM_DEFAULT_HT20_DIFF   2
 
#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF   0x4
 
#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET   0
 
#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET   0
 
#define EEPROM_CHANNEL_PLAN_FCC   0x0
 
#define EEPROM_CHANNEL_PLAN_IC   0x1
 
#define EEPROM_CHANNEL_PLAN_ETSI   0x2
 
#define EEPROM_CHANNEL_PLAN_SPAIN   0x3
 
#define EEPROM_CHANNEL_PLAN_FRANCE   0x4
 
#define EEPROM_CHANNEL_PLAN_MKK   0x5
 
#define EEPROM_CHANNEL_PLAN_MKK1   0x6
 
#define EEPROM_CHANNEL_PLAN_ISRAEL   0x7
 
#define EEPROM_CHANNEL_PLAN_TELEC   0x8
 
#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN   0x9
 
#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13   0xA
 
#define EEPROM_CHANNEL_PLAN_NCC   0xB
 
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK   0x80
 
#define EEPROM_CID_DEFAULT   0x0
 
#define EEPROM_CID_TOSHIBA   0x4
 
#define EEPROM_CID_CCX   0x10
 
#define EEPROM_CID_QMI   0x0D
 
#define EEPROM_CID_WHQL   0xFE
 
#define RTL8192_EEPROM_ID   0x8129
 
#define EEPROM_WAPI_SUPPORT   0x78
 
#define RTL8190_EEPROM_ID   0x8129 /* 0-1 */
 
#define EEPROM_HPON   0x02 /* LDO settings.2-5 */
 
#define EEPROM_CLK   0x06 /* Clock settings.6-7 */
 
#define EEPROM_MAC_FUNCTION   0x08 /* SE Test mode.8 */
 
#define EEPROM_VID   0x28 /* SE Vendor ID.A-B */
 
#define EEPROM_DID   0x2A /* SE Device ID. C-D */
 
#define EEPROM_SVID   0x2C /* SE Vendor ID.E-F */
 
#define EEPROM_SMID   0x2E /* SE PCI Subsystem ID. 10-11 */
 
#define EEPROM_MAC_ADDR   0x16 /* SEMAC Address. 12-17 */
 
#define EEPROM_MAC_ADDR_MAC0_92D   0x55
 
#define EEPROM_MAC_ADDR_MAC1_92D   0x5B
 
#define EEPROM_CCK_TX_PWR_INX_2G   0x61
 
#define EEPROM_HT40_1S_TX_PWR_INX_2G   0x67
 
#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G   0x6D
 
#define EEPROM_HT20_TX_PWR_INX_DIFF_2G   0x70
 
#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G   0x73
 
#define EEPROM_HT40_MAX_PWR_OFFSET_2G   0x76
 
#define EEPROM_HT20_MAX_PWR_OFFSET_2G   0x79
 
#define EEPROM_HT40_1S_TX_PWR_INX_5GL   0x7C
 
#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL   0x82
 
#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL   0x85
 
#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL   0x88
 
#define EEPROM_HT40_MAX_PWR_OFFSET_5GL   0x8B
 
#define EEPROM_HT20_MAX_PWR_OFFSET_5GL   0x8E
 
#define EEPROM_HT40_1S_TX_PWR_INX_5GM   0x91
 
#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM   0x97
 
#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM   0x9A
 
#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM   0x9D
 
#define EEPROM_HT40_MAX_PWR_OFFSET_5GM   0xA0
 
#define EEPROM_HT20_MAX_PWR_OFFSET_5GM   0xA3
 
#define EEPROM_HT40_1S_TX_PWR_INX_5GH   0xA6
 
#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH   0xAC
 
#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH   0xAF
 
#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH   0xB2
 
#define EEPROM_HT40_MAX_PWR_OFFSET_5GH   0xB5
 
#define EEPROM_HT20_MAX_PWR_OFFSET_5GH   0xB8
 
#define EEPROM_CHANNEL_PLAN   0xBB
 
#define EEPROM_IQK_DELTA   0xBC
 
#define EEPROM_LCK_DELTA   0xBC
 
#define EEPROM_XTAL_K   0xBD /* [7:5] */
 
#define EEPROM_TSSI_A_5G   0xBE
 
#define EEPROM_TSSI_B_5G   0xBF
 
#define EEPROM_TSSI_AB_5G   0xC0
 
#define EEPROM_THERMAL_METER   0xC3 /* [4:0] */
 
#define EEPROM_RF_OPT1   0xC4
 
#define EEPROM_RF_OPT2   0xC5
 
#define EEPROM_RF_OPT3   0xC6
 
#define EEPROM_RF_OPT4   0xC7
 
#define EEPROM_RF_OPT5   0xC8
 
#define EEPROM_RF_OPT6   0xC9
 
#define EEPROM_VERSION   0xCA
 
#define EEPROM_CUSTOMER_ID   0xCB
 
#define EEPROM_RF_OPT7   0xCC
 
#define EEPROM_DEF_PART_NO   0x3FD /* Byte */
 
#define EEPROME_CHIP_VERSION_L   0x3FF
 
#define EEPROME_CHIP_VERSION_H   0x3FE
 
#define RCR_APPFCS   BIT(31)
 
#define RCR_APP_MIC   BIT(30)
 
#define RCR_APP_ICV   BIT(29)
 
#define RCR_APP_PHYST_RXFF   BIT(28)
 
#define RCR_APP_BA_SSN   BIT(27)
 
#define RCR_ENMBID   BIT(24)
 
#define RCR_LSIGEN   BIT(23)
 
#define RCR_MFBEN   BIT(22)
 
#define RCR_HTC_LOC_CTRL   BIT(14)
 
#define RCR_AMF   BIT(13)
 
#define RCR_ACF   BIT(12)
 
#define RCR_ADF   BIT(11)
 
#define RCR_AICV   BIT(9)
 
#define RCR_ACRC32   BIT(8)
 
#define RCR_CBSSID_BCN   BIT(7)
 
#define RCR_CBSSID_DATA   BIT(6)
 
#define RCR_APWRMGT   BIT(5)
 
#define RCR_ADD3   BIT(4)
 
#define RCR_AB   BIT(3)
 
#define RCR_AM   BIT(2)
 
#define RCR_APM   BIT(1)
 
#define RCR_AAP   BIT(0)
 
#define RCR_MXDMA_OFFSET   8
 
#define RCR_FIFO_OFFSET   13
 
#define SW18_FPWM   BIT(3)
 
#define ISO_MD2PP   BIT(0)
 
#define ISO_UA2USB   BIT(1)
 
#define ISO_UD2CORE   BIT(2)
 
#define ISO_PA2PCIE   BIT(3)
 
#define ISO_PD2CORE   BIT(4)
 
#define ISO_IP2MAC   BIT(5)
 
#define ISO_DIOP   BIT(6)
 
#define ISO_DIOE   BIT(7)
 
#define ISO_EB2CORE   BIT(8)
 
#define ISO_DIOR   BIT(9)
 
#define PWC_EV25V   BIT(14)
 
#define PWC_EV12V   BIT(15)
 
#define FEN_BBRSTB   BIT(0)
 
#define FEN_BB_GLB_RSTn   BIT(1)
 
#define FEN_USBA   BIT(2)
 
#define FEN_UPLL   BIT(3)
 
#define FEN_USBD   BIT(4)
 
#define FEN_DIO_PCIE   BIT(5)
 
#define FEN_PCIEA   BIT(6)
 
#define FEN_PPLL   BIT(7)
 
#define FEN_PCIED   BIT(8)
 
#define FEN_DIOE   BIT(9)
 
#define FEN_CPUEN   BIT(10)
 
#define FEN_DCORE   BIT(11)
 
#define FEN_ELDR   BIT(12)
 
#define FEN_DIO_RF   BIT(13)
 
#define FEN_HWPDN   BIT(14)
 
#define FEN_MREGEN   BIT(15)
 
#define PFM_LDALL   BIT(0)
 
#define PFM_ALDN   BIT(1)
 
#define PFM_LDKP   BIT(2)
 
#define PFM_WOWL   BIT(3)
 
#define EnPDN   BIT(4)
 
#define PDN_PL   BIT(5)
 
#define APFM_ONMAC   BIT(8)
 
#define APFM_OFF   BIT(9)
 
#define APFM_RSM   BIT(10)
 
#define AFSM_HSUS   BIT(11)
 
#define AFSM_PCIE   BIT(12)
 
#define APDM_MAC   BIT(13)
 
#define APDM_HOST   BIT(14)
 
#define APDM_HPDN   BIT(15)
 
#define RDY_MACON   BIT(16)
 
#define SUS_HOST   BIT(17)
 
#define ROP_ALD   BIT(20)
 
#define ROP_PWR   BIT(21)
 
#define ROP_SPS   BIT(22)
 
#define SOP_MRST   BIT(25)
 
#define SOP_FUSE   BIT(26)
 
#define SOP_ABG   BIT(27)
 
#define SOP_AMB   BIT(28)
 
#define SOP_RCK   BIT(29)
 
#define SOP_A8M   BIT(30)
 
#define XOP_BTCK   BIT(31)
 
#define ANAD16V_EN   BIT(0)
 
#define ANA8M   BIT(1)
 
#define MACSLP   BIT(4)
 
#define LOADER_CLK_EN   BIT(5)
 
#define _80M_SSC_DIS   BIT(7)
 
#define _80M_SSC_EN_HO   BIT(8)
 
#define PHY_SSC_RSTB   BIT(9)
 
#define SEC_CLK_EN   BIT(10)
 
#define MAC_CLK_EN   BIT(11)
 
#define SYS_CLK_EN   BIT(12)
 
#define RING_CLK_EN   BIT(13)
 
#define BOOT_FROM_EEPROM   BIT(4)
 
#define EEPROM_EN   BIT(5)
 
#define AFE_BGEN   BIT(0)
 
#define AFE_MBEN   BIT(1)
 
#define MAC_ID_EN   BIT(7)
 
#define WLOCK_ALL   BIT(0)
 
#define WLOCK_00   BIT(1)
 
#define WLOCK_04   BIT(2)
 
#define WLOCK_08   BIT(3)
 
#define WLOCK_40   BIT(4)
 
#define R_DIS_PRST_0   BIT(5)
 
#define R_DIS_PRST_1   BIT(6)
 
#define LOCK_ALL_EN   BIT(7)
 
#define RF_EN   BIT(0)
 
#define RF_RSTB   BIT(1)
 
#define RF_SDMRSTB   BIT(2)
 
#define LDA15_EN   BIT(0)
 
#define LDA15_STBY   BIT(1)
 
#define LDA15_OBUF   BIT(2)
 
#define LDA15_REG_VOS   BIT(3)
 
#define _LDA15_VOADJ(x)   (((x) & 0x7) << 4)
 
#define LDV12_EN   BIT(0)
 
#define LDV12_SDBY   BIT(1)
 
#define LPLDO_HSM   BIT(2)
 
#define LPLDO_LSM_DIS   BIT(3)
 
#define _LDV12_VADJ(x)   (((x) & 0xF) << 4)
 
#define XTAL_EN   BIT(0)
 
#define XTAL_BSEL   BIT(1)
 
#define _XTAL_BOSC(x)   (((x) & 0x3) << 2)
 
#define _XTAL_CADJ(x)   (((x) & 0xF) << 4)
 
#define XTAL_GATE_USB   BIT(8)
 
#define _XTAL_USB_DRV(x)   (((x) & 0x3) << 9)
 
#define XTAL_GATE_AFE   BIT(11)
 
#define _XTAL_AFE_DRV(x)   (((x) & 0x3) << 12)
 
#define XTAL_RF_GATE   BIT(14)
 
#define _XTAL_RF_DRV(x)   (((x) & 0x3) << 15)
 
#define XTAL_GATE_DIG   BIT(17)
 
#define _XTAL_DIG_DRV(x)   (((x) & 0x3) << 18)
 
#define XTAL_BT_GATE   BIT(20)
 
#define _XTAL_BT_DRV(x)   (((x) & 0x3) << 21)
 
#define _XTAL_GPIO(x)   (((x) & 0x7) << 23)
 
#define CKDLY_AFE   BIT(26)
 
#define CKDLY_USB   BIT(27)
 
#define CKDLY_DIG   BIT(28)
 
#define CKDLY_BT   BIT(29)
 
#define APLL_EN   BIT(0)
 
#define APLL_320_EN   BIT(1)
 
#define APLL_FREF_SEL   BIT(2)
 
#define APLL_EDGE_SEL   BIT(3)
 
#define APLL_WDOGB   BIT(4)
 
#define APLL_LPFEN   BIT(5)
 
#define APLL_REF_CLK_13MHZ   0x1
 
#define APLL_REF_CLK_19_2MHZ   0x2
 
#define APLL_REF_CLK_20MHZ   0x3
 
#define APLL_REF_CLK_25MHZ   0x4
 
#define APLL_REF_CLK_26MHZ   0x5
 
#define APLL_REF_CLK_38_4MHZ   0x6
 
#define APLL_REF_CLK_40MHZ   0x7
 
#define APLL_320EN   BIT(14)
 
#define APLL_80EN   BIT(15)
 
#define APLL_1MEN   BIT(24)
 
#define ALD_EN   BIT(18)
 
#define EF_PD   BIT(19)
 
#define EF_FLAG   BIT(31)
 
#define EF_TRPT   BIT(7)
 
#define LDOE25_EN   BIT(31)
 
#define MCUFWDL_EN   BIT(0)
 
#define MCUFWDL_RDY   BIT(1)
 
#define FWDL_ChkSum_rpt   BIT(2)
 
#define MACINI_RDY   BIT(3)
 
#define BBINI_RDY   BIT(4)
 
#define RFINI_RDY   BIT(5)
 
#define WINTINI_RDY   BIT(6)
 
#define MAC1_WINTINI_RDY   BIT(11)
 
#define CPRST   BIT(23)
 
#define XCLK_VLD   BIT(0)
 
#define ACLK_VLD   BIT(1)
 
#define UCLK_VLD   BIT(2)
 
#define PCLK_VLD   BIT(3)
 
#define PCIRSTB   BIT(4)
 
#define V15_VLD   BIT(5)
 
#define TRP_B15V_EN   BIT(7)
 
#define SIC_IDLE   BIT(8)
 
#define BD_MAC2   BIT(9)
 
#define BD_MAC1   BIT(10)
 
#define IC_MACPHY_MODE   BIT(11)
 
#define PAD_HWPD_IDN   BIT(22)
 
#define TRP_VAUX_EN   BIT(23)
 
#define TRP_BT_EN   BIT(24)
 
#define BD_PKG_SEL   BIT(25)
 
#define BD_HCI_SEL   BIT(26)
 
#define TYPE_ID   BIT(27)
 
#define _LLT_NO_ACTIVE   0x0
 
#define _LLT_WRITE_ACCESS   0x1
 
#define _LLT_READ_ACCESS   0x2
 
#define _LLT_INIT_DATA(x)   ((x) & 0xFF)
 
#define _LLT_INIT_ADDR(x)   (((x) & 0xFF) << 8)
 
#define _LLT_OP(x)   (((x) & 0x3) << 30)
 
#define _LLT_OP_VALUE(x)   (((x) >> 30) & 0x3)
 
#define RETRY_LIMIT_SHORT_SHIFT   8
 
#define RETRY_LIMIT_LONG_SHIFT   0
 
#define AC_PARAM_TXOP_LIMIT_OFFSET   16
 
#define AC_PARAM_ECW_MAX_OFFSET   12
 
#define AC_PARAM_ECW_MIN_OFFSET   8
 
#define AC_PARAM_AIFS_OFFSET   0
 
#define ACMHW_HWEN   BIT(0)
 
#define ACMHW_BEQEN   BIT(1)
 
#define ACMHW_VIQEN   BIT(2)
 
#define ACMHW_VOQEN   BIT(3)
 
#define TSFRST   BIT(0)
 
#define DIS_GCLK   BIT(1)
 
#define PAD_SEL   BIT(2)
 
#define PWR_ST   BIT(6)
 
#define PWRBIT_OW_EN   BIT(7)
 
#define ACRC   BIT(8)
 
#define CFENDFORM   BIT(9)
 
#define ICV   BIT(10)
 
#define SCR_TXUSEDK   BIT(0)
 
#define SCR_RXUSEDK   BIT(1)
 
#define SCR_TXENCENABLE   BIT(2)
 
#define SCR_RXENCENABLE   BIT(3)
 
#define SCR_SKBYA2   BIT(4)
 
#define SCR_NOSKMC   BIT(5)
 
#define SCR_TXBCUSEDK   BIT(6)
 
#define SCR_RXBCUSEDK   BIT(7)
 
#define LAST_ENTRY_OF_TX_PKT_BUFFER   255
 
#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC   127
 
#define POLLING_LLT_THRESHOLD   20
 
#define POLLING_READY_TIMEOUT_COUNT   1000
 
#define MAX_MSS_DENSITY_2T   0x13
 
#define MAX_MSS_DENSITY_1T   0x0A
 
#define RFPGA0_RFMOD   0x800
 
#define RFPGA0_TXINFO   0x804
 
#define RFPGA0_PSDFUNCTION   0x808
 
#define RFPGA0_TXGAINSTAGE   0x80c
 
#define RFPGA0_RFTIMING1   0x810
 
#define RFPGA0_RFTIMING2   0x814
 
#define RFPGA0_XA_HSSIPARAMETER1   0x820
 
#define RFPGA0_XA_HSSIPARAMETER2   0x824
 
#define RFPGA0_XB_HSSIPARAMETER1   0x828
 
#define RFPGA0_XB_HSSIPARAMETER2   0x82c
 
#define RFPGA0_XA_LSSIPARAMETER   0x840
 
#define RFPGA0_XB_LSSIPARAMETER   0x844
 
#define RFPGA0_RFWAkEUPPARAMETER   0x850
 
#define RFPGA0_RFSLEEPUPPARAMETER   0x854
 
#define RFPGA0_XAB_SWITCHCONTROL   0x858
 
#define RFPGA0_XCD_SWITCHCONTROL   0x85c
 
#define RFPGA0_XA_RFINTERFACEOE   0x860
 
#define RFPGA0_XB_RFINTERFACEOE   0x864
 
#define RFPGA0_XAB_RFINTERFACESW   0x870
 
#define RFPGA0_XCD_RFINTERFACESW   0x874
 
#define RFPGA0_XAB_RFPARAMETER   0x878
 
#define RFPGA0_XCD_RFPARAMETER   0x87c
 
#define RFPGA0_ANALOGPARAMETER1   0x880
 
#define RFPGA0_ANALOGPARAMETER2   0x884
 
#define RFPGA0_ANALOGPARAMETER3   0x888
 
#define RFPGA0_ADDALLOCKEN   0x888
 
#define RFPGA0_ANALOGPARAMETER4   0x88c
 
#define RFPGA0_XA_LSSIREADBACK   0x8a0
 
#define RFPGA0_XB_LSSIREADBACK   0x8a4
 
#define RFPGA0_XC_LSSIREADBACK   0x8a8
 
#define RFPGA0_XD_LSSIREADBACK   0x8ac
 
#define RFPGA0_PSDREPORT   0x8b4
 
#define TRANSCEIVERA_HSPI_READBACK   0x8b8
 
#define TRANSCEIVERB_HSPI_READBACK   0x8bc
 
#define RFPGA0_XAB_RFINTERFACERB   0x8e0
 
#define RFPGA0_XCD_RFINTERFACERB   0x8e4
 
#define RFPGA1_RFMOD   0x900
 
#define RFPGA1_TXBLOCK   0x904
 
#define RFPGA1_DEBUGSELECT   0x908
 
#define RFPGA1_TXINFO   0x90c
 
#define RCCK0_SYSTEM   0xa00
 
#define RCCK0_AFESSTTING   0xa04
 
#define RCCK0_CCA   0xa08
 
#define RCCK0_RXAGC1   0xa0c
 
#define RCCK0_RXAGC2   0xa10
 
#define RCCK0_RXHP   0xa14
 
#define RCCK0_DSPPARAMETER1   0xa18
 
#define RCCK0_DSPPARAMETER2   0xa1c
 
#define RCCK0_TXFILTER1   0xa20
 
#define RCCK0_TXFILTER2   0xa24
 
#define RCCK0_DEBUGPORT   0xa28
 
#define RCCK0_FALSEALARMREPORT   0xa2c
 
#define RCCK0_TRSSIREPORT   0xa50
 
#define RCCK0_RXREPORT   0xa54
 
#define RCCK0_FACOUNTERLOWER   0xa5c
 
#define RCCK0_FACOUNTERUPPER   0xa58
 
#define ROFDM0_LSTF   0xc00
 
#define ROFDM0_TRXPATHENABLE   0xc04
 
#define ROFDM0_TRMUXPAR   0xc08
 
#define ROFDM0_TRSWISOLATION   0xc0c
 
#define ROFDM0_XARXAFE   0xc10
 
#define ROFDM0_XARXIQIMBALANCE   0xc14
 
#define ROFDM0_XBRXAFE   0xc18
 
#define ROFDM0_XBRXIQIMBALANCE   0xc1c
 
#define ROFDM0_XCRXAFE   0xc20
 
#define ROFDM0_XCRXIQIMBALANCE   0xc24
 
#define ROFDM0_XDRXAFE   0xc28
 
#define ROFDM0_XDRXIQIMBALANCE   0xc2c
 
#define ROFDM0_RXDETECTOR1   0xc30
 
#define ROFDM0_RXDETECTOR2   0xc34
 
#define ROFDM0_RXDETECTOR3   0xc38
 
#define ROFDM0_RXDETECTOR4   0xc3c
 
#define ROFDM0_RXDSP   0xc40
 
#define ROFDM0_CFOANDDAGC   0xc44
 
#define ROFDM0_CCADROPTHRESHOLD   0xc48
 
#define ROFDM0_ECCATHRESHOLD   0xc4c
 
#define ROFDM0_XAAGCCORE1   0xc50
 
#define ROFDM0_XAAGCCORE2   0xc54
 
#define ROFDM0_XBAGCCORE1   0xc58
 
#define ROFDM0_XBAGCCORE2   0xc5c
 
#define ROFDM0_XCAGCCORE1   0xc60
 
#define ROFDM0_XCAGCCORE2   0xc64
 
#define ROFDM0_XDAGCCORE1   0xc68
 
#define ROFDM0_XDAGCCORE2   0xc6c
 
#define ROFDM0_AGCPARAMETER1   0xc70
 
#define ROFDM0_AGCPARAMETER2   0xc74
 
#define ROFDM0_AGCRSSITABLE   0xc78
 
#define ROFDM0_HTSTFAGC   0xc7c
 
#define ROFDM0_XATxIQIMBALANCE   0xc80
 
#define ROFDM0_XATxAFE   0xc84
 
#define ROFDM0_XBTxIQIMBALANCE   0xc88
 
#define ROFDM0_XBTxAFE   0xc8c
 
#define ROFDM0_XCTxIQIMBALANCE   0xc90
 
#define ROFDM0_XCTxAFE   0xc94
 
#define ROFDM0_XDTxIQIMBALANCE   0xc98
 
#define ROFDM0_XDTxAFE   0xc9c
 
#define ROFDM0_RXHPPARAMETER   0xce0
 
#define ROFDM0_TXPSEUDONOISEWGT   0xce4
 
#define ROFDM0_FRAMESYNC   0xcf0
 
#define ROFDM0_DFSREPORT   0xcf4
 
#define ROFDM0_TXCOEFF1   0xca4
 
#define ROFDM0_TXCOEFF2   0xca8
 
#define ROFDM0_TXCOEFF3   0xcac
 
#define ROFDM0_TXCOEFF4   0xcb0
 
#define ROFDM0_TXCOEFF5   0xcb4
 
#define ROFDM0_TXCOEFF6   0xcb8
 
#define ROFDM1_LSTF   0xd00
 
#define ROFDM1_TRXPATHENABLE   0xd04
 
#define ROFDM1_CFO   0xd08
 
#define ROFDM1_CSI1   0xd10
 
#define ROFDM1_SBD   0xd14
 
#define ROFDM1_CSI2   0xd18
 
#define ROFDM1_CFOTRACKING   0xd2c
 
#define ROFDM1_TRXMESAURE1   0xd34
 
#define ROFDM1_INTFDET   0xd3c
 
#define ROFDM1_PSEUDONOISESTATEAB   0xd50
 
#define ROFDM1_PSEUDONOISESTATECD   0xd54
 
#define ROFDM1_RXPSEUDONOISEWGT   0xd58
 
#define ROFDM_PHYCOUNTER1   0xda0
 
#define ROFDM_PHYCOUNTER2   0xda4
 
#define ROFDM_PHYCOUNTER3   0xda8
 
#define ROFDM_SHORTCFOAB   0xdac
 
#define ROFDM_SHORTCFOCD   0xdb0
 
#define ROFDM_LONGCFOAB   0xdb4
 
#define ROFDM_LONGCFOCD   0xdb8
 
#define ROFDM_TAILCFOAB   0xdbc
 
#define ROFDM_TAILCFOCD   0xdc0
 
#define ROFDM_PWMEASURE1   0xdc4
 
#define ROFDM_PWMEASURE2   0xdc8
 
#define ROFDM_BWREPORT   0xdcc
 
#define ROFDM_AGCREPORT   0xdd0
 
#define ROFDM_RXSNR   0xdd4
 
#define ROFDM_RXEVMCSI   0xdd8
 
#define ROFDM_SIGReport   0xddc
 
#define RTXAGC_A_RATE18_06   0xe00
 
#define RTXAGC_A_RATE54_24   0xe04
 
#define RTXAGC_A_CCK1_MCS32   0xe08
 
#define RTXAGC_A_MCS03_MCS00   0xe10
 
#define RTXAGC_A_MCS07_MCS04   0xe14
 
#define RTXAGC_A_MCS11_MCS08   0xe18
 
#define RTXAGC_A_MCS15_MCS12   0xe1c
 
#define RTXAGC_B_RATE18_06   0x830
 
#define RTXAGC_B_RATE54_24   0x834
 
#define RTXAGC_B_CCK1_55_MCS32   0x838
 
#define RTXAGC_B_MCS03_MCS00   0x83c
 
#define RTXAGC_B_MCS07_MCS04   0x848
 
#define RTXAGC_B_MCS11_MCS08   0x84c
 
#define RTXAGC_B_MCS15_MCS12   0x868
 
#define RTXAGC_B_CCK11_A_CCK2_11   0x86c
 
#define RF_AC   0x00
 
#define RF_IQADJ_G1   0x01
 
#define RF_IQADJ_G2   0x02
 
#define RF_POW_TRSW   0x05
 
#define RF_GAIN_RX   0x06
 
#define RF_GAIN_TX   0x07
 
#define RF_TXM_IDAC   0x08
 
#define RF_BS_IQGEN   0x0F
 
#define RF_MODE1   0x10
 
#define RF_MODE2   0x11
 
#define RF_RX_AGC_HP   0x12
 
#define RF_TX_AGC   0x13
 
#define RF_BIAS   0x14
 
#define RF_IPA   0x15
 
#define RF_POW_ABILITY   0x17
 
#define RF_MODE_AG   0x18
 
#define rRfChannel   0x18
 
#define RF_CHNLBW   0x18
 
#define RF_TOP   0x19
 
#define RF_RX_G1   0x1A
 
#define RF_RX_G2   0x1B
 
#define RF_RX_BB2   0x1C
 
#define RF_RX_BB1   0x1D
 
#define RF_RCK1   0x1E
 
#define RF_RCK2   0x1F
 
#define RF_TX_G1   0x20
 
#define RF_TX_G2   0x21
 
#define RF_TX_G3   0x22
 
#define RF_TX_BB1   0x23
 
#define RF_T_METER   0x42
 
#define RF_SYN_G1   0x25
 
#define RF_SYN_G2   0x26
 
#define RF_SYN_G3   0x27
 
#define RF_SYN_G4   0x28
 
#define RF_SYN_G5   0x29
 
#define RF_SYN_G6   0x2A
 
#define RF_SYN_G7   0x2B
 
#define RF_SYN_G8   0x2C
 
#define RF_RCK_OS   0x30
 
#define RF_TXPA_G1   0x31
 
#define RF_TXPA_G2   0x32
 
#define RF_TXPA_G3   0x33
 
#define BRFMOD   0x1
 
#define BCCKTXSC   0x30
 
#define BCCKEN   0x1000000
 
#define BOFDMEN   0x2000000
 
#define B3WIREDATALENGTH   0x800
 
#define B3WIREADDRESSLENGTH   0x400
 
#define BRFSI_RFENV   0x10
 
#define BLSSIREADADDRESS   0x7f800000
 
#define BLSSIREADEDGE   0x80000000
 
#define BLSSIREADBACKDATA   0xfffff
 
#define BCCKSIDEBAND   0x10
 
#define BBYTE0   0x1
 
#define BBYTE1   0x2
 
#define BBYTE2   0x4
 
#define BBYTE3   0x8
 
#define BWORD0   0x3
 
#define BWORD1   0xc
 
#define BDWORD   0xf
 
#define BMASKBYTE0   0xff
 
#define BMASKBYTE1   0xff00
 
#define BMASKBYTE2   0xff0000
 
#define BMASKBYTE3   0xff000000
 
#define BMASKHWORD   0xffff0000
 
#define BMASKLWORD   0x0000ffff
 
#define BMASKDWORD   0xffffffff
 
#define BMASK12BITS   0xfff
 
#define BMASKH4BITS   0xf0000000
 
#define BMASKOFDM_D   0xffc00000
 
#define BMASKCCK   0x3f3f3f3f
 
#define BRFREGOFFSETMASK   0xfffff
 

Macro Definition Documentation

#define _80M_SSC_DIS   BIT(7)

Definition at line 807 of file reg.h.

#define _80M_SSC_EN_HO   BIT(8)

Definition at line 808 of file reg.h.

#define _LDA15_VOADJ (   x)    (((x) & 0x7) << 4)

Definition at line 847 of file reg.h.

#define _LDV12_VADJ (   x)    (((x) & 0xF) << 4)

Definition at line 856 of file reg.h.

#define _LLT_INIT_ADDR (   x)    (((x) & 0xFF) << 8)

Definition at line 949 of file reg.h.

#define _LLT_INIT_DATA (   x)    ((x) & 0xFF)

Definition at line 948 of file reg.h.

#define _LLT_NO_ACTIVE   0x0

Definition at line 944 of file reg.h.

#define _LLT_OP (   x)    (((x) & 0x3) << 30)

Definition at line 950 of file reg.h.

#define _LLT_OP_VALUE (   x)    (((x) >> 30) & 0x3)

Definition at line 951 of file reg.h.

#define _LLT_READ_ACCESS   0x2

Definition at line 946 of file reg.h.

#define _LLT_WRITE_ACCESS   0x1

Definition at line 945 of file reg.h.

#define _XTAL_AFE_DRV (   x)    (((x) & 0x3) << 12)

Definition at line 867 of file reg.h.

#define _XTAL_BOSC (   x)    (((x) & 0x3) << 2)

Definition at line 862 of file reg.h.

#define _XTAL_BT_DRV (   x)    (((x) & 0x3) << 21)

Definition at line 873 of file reg.h.

#define _XTAL_CADJ (   x)    (((x) & 0xF) << 4)

Definition at line 863 of file reg.h.

#define _XTAL_DIG_DRV (   x)    (((x) & 0x3) << 18)

Definition at line 871 of file reg.h.

#define _XTAL_GPIO (   x)    (((x) & 0x7) << 23)

Definition at line 874 of file reg.h.

#define _XTAL_RF_DRV (   x)    (((x) & 0x3) << 15)

Definition at line 869 of file reg.h.

#define _XTAL_USB_DRV (   x)    (((x) & 0x3) << 9)

Definition at line 865 of file reg.h.

#define AC_PARAM_AIFS_OFFSET   0

Definition at line 968 of file reg.h.

#define AC_PARAM_ECW_MAX_OFFSET   12

Definition at line 966 of file reg.h.

#define AC_PARAM_ECW_MIN_OFFSET   8

Definition at line 967 of file reg.h.

#define AC_PARAM_TXOP_LIMIT_OFFSET   16

Definition at line 965 of file reg.h.

#define ACLK_VLD   BIT(1)

Definition at line 926 of file reg.h.

#define ACMHW_BEQEN   BIT(1)

Definition at line 972 of file reg.h.

#define ACMHW_HWEN   BIT(0)

Definition at line 971 of file reg.h.

#define ACMHW_VIQEN   BIT(2)

Definition at line 973 of file reg.h.

#define ACMHW_VOQEN   BIT(3)

Definition at line 974 of file reg.h.

#define ACRC   BIT(8)

Definition at line 986 of file reg.h.

#define AFE_BGEN   BIT(0)

Definition at line 821 of file reg.h.

#define AFE_MBEN   BIT(1)

Definition at line 822 of file reg.h.

#define AFSM_HSUS   BIT(11)

Definition at line 784 of file reg.h.

#define AFSM_PCIE   BIT(12)

Definition at line 785 of file reg.h.

#define ALD_EN   BIT(18)

Definition at line 905 of file reg.h.

#define ANA8M   BIT(1)

Definition at line 804 of file reg.h.

#define ANAD16V_EN   BIT(0)

Definition at line 803 of file reg.h.

#define APDM_HOST   BIT(14)

Definition at line 787 of file reg.h.

#define APDM_HPDN   BIT(15)

Definition at line 788 of file reg.h.

#define APDM_MAC   BIT(13)

Definition at line 786 of file reg.h.

#define APFM_OFF   BIT(9)

Definition at line 782 of file reg.h.

#define APFM_ONMAC   BIT(8)

Definition at line 781 of file reg.h.

#define APFM_RSM   BIT(10)

Definition at line 783 of file reg.h.

#define APLL_1MEN   BIT(24)

Definition at line 901 of file reg.h.

#define APLL_320_EN   BIT(1)

Definition at line 885 of file reg.h.

#define APLL_320EN   BIT(14)

Definition at line 899 of file reg.h.

#define APLL_80EN   BIT(15)

Definition at line 900 of file reg.h.

#define APLL_EDGE_SEL   BIT(3)

Definition at line 887 of file reg.h.

#define APLL_EN   BIT(0)

Definition at line 884 of file reg.h.

#define APLL_FREF_SEL   BIT(2)

Definition at line 886 of file reg.h.

#define APLL_LPFEN   BIT(5)

Definition at line 889 of file reg.h.

#define APLL_REF_CLK_13MHZ   0x1

Definition at line 891 of file reg.h.

#define APLL_REF_CLK_19_2MHZ   0x2

Definition at line 892 of file reg.h.

#define APLL_REF_CLK_20MHZ   0x3

Definition at line 893 of file reg.h.

#define APLL_REF_CLK_25MHZ   0x4

Definition at line 894 of file reg.h.

#define APLL_REF_CLK_26MHZ   0x5

Definition at line 895 of file reg.h.

#define APLL_REF_CLK_38_4MHZ   0x6

Definition at line 896 of file reg.h.

#define APLL_REF_CLK_40MHZ   0x7

Definition at line 897 of file reg.h.

#define APLL_WDOGB   BIT(4)

Definition at line 888 of file reg.h.

#define B3WIREADDRESSLENGTH   0x400

Definition at line 1279 of file reg.h.

#define B3WIREDATALENGTH   0x800

Definition at line 1278 of file reg.h.

#define BBINI_RDY   BIT(4)

Definition at line 918 of file reg.h.

#define BBYTE0   0x1

Definition at line 1290 of file reg.h.

#define BBYTE1   0x2

Definition at line 1291 of file reg.h.

#define BBYTE2   0x4

Definition at line 1292 of file reg.h.

#define BBYTE3   0x8

Definition at line 1293 of file reg.h.

#define BCCKEN   0x1000000

Definition at line 1275 of file reg.h.

#define BCCKSIDEBAND   0x10

Definition at line 1287 of file reg.h.

#define BCCKTXSC   0x30

Definition at line 1274 of file reg.h.

#define BD_HCI_SEL   BIT(26)

Definition at line 940 of file reg.h.

#define BD_MAC1   BIT(10)

Definition at line 934 of file reg.h.

#define BD_MAC2   BIT(9)

Definition at line 933 of file reg.h.

#define BD_PKG_SEL   BIT(25)

Definition at line 939 of file reg.h.

#define BDWORD   0xf

Definition at line 1296 of file reg.h.

#define BLSSIREADADDRESS   0x7f800000

Definition at line 1283 of file reg.h.

#define BLSSIREADBACKDATA   0xfffff

Definition at line 1285 of file reg.h.

#define BLSSIREADEDGE   0x80000000

Definition at line 1284 of file reg.h.

#define BMASK12BITS   0xfff

Definition at line 1305 of file reg.h.

#define BMASKBYTE0   0xff

Definition at line 1298 of file reg.h.

#define BMASKBYTE1   0xff00

Definition at line 1299 of file reg.h.

#define BMASKBYTE2   0xff0000

Definition at line 1300 of file reg.h.

#define BMASKBYTE3   0xff000000

Definition at line 1301 of file reg.h.

#define BMASKCCK   0x3f3f3f3f

Definition at line 1308 of file reg.h.

#define BMASKDWORD   0xffffffff

Definition at line 1304 of file reg.h.

#define BMASKH4BITS   0xf0000000

Definition at line 1306 of file reg.h.

#define BMASKHWORD   0xffff0000

Definition at line 1302 of file reg.h.

#define BMASKLWORD   0x0000ffff

Definition at line 1303 of file reg.h.

#define BMASKOFDM_D   0xffc00000

Definition at line 1307 of file reg.h.

#define BOFDMEN   0x2000000

Definition at line 1276 of file reg.h.

#define BOOT_FROM_EEPROM   BIT(4)

Definition at line 817 of file reg.h.

#define BRFMOD   0x1

Definition at line 1273 of file reg.h.

#define BRFREGOFFSETMASK   0xfffff

Definition at line 1310 of file reg.h.

#define BRFSI_RFENV   0x10

Definition at line 1281 of file reg.h.

#define BRSR_ACKSHORTPMB   BIT23

Definition at line 403 of file reg.h.

#define BW_OPMODE_11J   BIT(0)

Definition at line 492 of file reg.h.

#define BW_OPMODE_20MHZ   BIT(2)

Definition at line 490 of file reg.h.

#define BW_OPMODE_5G   BIT(1)

Definition at line 491 of file reg.h.

#define BWORD0   0x3

Definition at line 1294 of file reg.h.

#define BWORD1   0xc

Definition at line 1295 of file reg.h.

#define CAM_AES   0x04

Definition at line 505 of file reg.h.

#define CAM_NONE   0x0

Definition at line 502 of file reg.h.

#define CAM_NOTVALID   0x0000

Definition at line 499 of file reg.h.

#define CAM_POLLINIG   BIT(31)

Definition at line 515 of file reg.h.

#define CAM_READ   0x00000000

Definition at line 514 of file reg.h.

#define CAM_SMS4   0x6

Definition at line 507 of file reg.h.

#define CAM_TKIP   0x02

Definition at line 504 of file reg.h.

#define CAM_USEDK   BIT(5)

Definition at line 500 of file reg.h.

#define CAM_VALID   BIT(15)

Definition at line 498 of file reg.h.

#define CAM_WEP104   0x05

Definition at line 506 of file reg.h.

#define CAM_WEP40   0x01

Definition at line 503 of file reg.h.

#define CAM_WRITE   BIT(16)

Definition at line 513 of file reg.h.

#define CFENDFORM   BIT(9)

Definition at line 987 of file reg.h.

#define CKDLY_AFE   BIT(26)

Definition at line 877 of file reg.h.

#define CKDLY_BT   BIT(29)

Definition at line 880 of file reg.h.

#define CKDLY_DIG   BIT(28)

Definition at line 879 of file reg.h.

#define CKDLY_USB   BIT(27)

Definition at line 878 of file reg.h.

#define CPRST   BIT(23)

Definition at line 922 of file reg.h.

#define CR9346   REG_9346CR

Definition at line 352 of file reg.h.

#define DIS_GCLK   BIT(1)

Definition at line 982 of file reg.h.

#define EEPROM_CCK_TX_PWR_INX_2G   0x61

Definition at line 633 of file reg.h.

#define EEPROM_CHANNEL_PLAN   0xBB

Definition at line 666 of file reg.h.

#define EEPROM_CHANNEL_PLAN_BY_HW_MASK   0x80

Definition at line 605 of file reg.h.

#define EEPROM_CHANNEL_PLAN_ETSI   0x2

Definition at line 595 of file reg.h.

#define EEPROM_CHANNEL_PLAN_FCC   0x0

Definition at line 593 of file reg.h.

#define EEPROM_CHANNEL_PLAN_FRANCE   0x4

Definition at line 597 of file reg.h.

#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN   0x9

Definition at line 602 of file reg.h.

#define EEPROM_CHANNEL_PLAN_IC   0x1

Definition at line 594 of file reg.h.

#define EEPROM_CHANNEL_PLAN_ISRAEL   0x7

Definition at line 600 of file reg.h.

#define EEPROM_CHANNEL_PLAN_MKK   0x5

Definition at line 598 of file reg.h.

#define EEPROM_CHANNEL_PLAN_MKK1   0x6

Definition at line 599 of file reg.h.

#define EEPROM_CHANNEL_PLAN_NCC   0xB

Definition at line 604 of file reg.h.

#define EEPROM_CHANNEL_PLAN_SPAIN   0x3

Definition at line 596 of file reg.h.

#define EEPROM_CHANNEL_PLAN_TELEC   0x8

Definition at line 601 of file reg.h.

#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13   0xA

Definition at line 603 of file reg.h.

#define EEPROM_CID_CCX   0x10

Definition at line 609 of file reg.h.

#define EEPROM_CID_DEFAULT   0x0

Definition at line 607 of file reg.h.

#define EEPROM_CID_QMI   0x0D

Definition at line 610 of file reg.h.

#define EEPROM_CID_TOSHIBA   0x4

Definition at line 608 of file reg.h.

#define EEPROM_CID_WHQL   0xFE

Definition at line 611 of file reg.h.

#define EEPROM_CLK   0x06 /* Clock settings.6-7 */

Definition at line 620 of file reg.h.

#define EEPROM_CUSTOMER_ID   0xCB

Definition at line 681 of file reg.h.

#define EEPROM_DEF_PART_NO   0x3FD /* Byte */

Definition at line 684 of file reg.h.

#define EEPROM_DEFAULT_CRYSTALCAP   0x0

Definition at line 579 of file reg.h.

#define EEPROM_DEFAULT_HT20_DIFF   2

Definition at line 587 of file reg.h.

#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET   0

Definition at line 591 of file reg.h.

#define EEPROM_DEFAULT_HT40_2SDIFF   0x0

Definition at line 585 of file reg.h.

#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET   0

Definition at line 590 of file reg.h.

#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF   0x4

Definition at line 589 of file reg.h.

#define EEPROM_DEFAULT_THERMALMETER   0x12

Definition at line 580 of file reg.h.

#define EEPROM_DEFAULT_TSSI   0x0

Definition at line 578 of file reg.h.

#define EEPROM_DEFAULT_TXPOWERLEVEL_2G   0x2C

Definition at line 582 of file reg.h.

#define EEPROM_DEFAULT_TXPOWERLEVEL_5G   0x22

Definition at line 583 of file reg.h.

#define EEPROM_DID   0x2A /* SE Device ID. C-D */

Definition at line 624 of file reg.h.

#define EEPROM_EN   BIT(5)

Definition at line 818 of file reg.h.

#define EEPROM_HPON   0x02 /* LDO settings.2-5 */

Definition at line 619 of file reg.h.

#define EEPROM_HT20_MAX_PWR_OFFSET_2G   0x79

Definition at line 639 of file reg.h.

#define EEPROM_HT20_MAX_PWR_OFFSET_5GH   0xB8

Definition at line 663 of file reg.h.

#define EEPROM_HT20_MAX_PWR_OFFSET_5GL   0x8E

Definition at line 647 of file reg.h.

#define EEPROM_HT20_MAX_PWR_OFFSET_5GM   0xA3

Definition at line 655 of file reg.h.

#define EEPROM_HT20_TX_PWR_INX_DIFF_2G   0x70

Definition at line 636 of file reg.h.

#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH   0xAF

Definition at line 660 of file reg.h.

#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL   0x85

Definition at line 644 of file reg.h.

#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM   0x9A

Definition at line 652 of file reg.h.

#define EEPROM_HT40_1S_TX_PWR_INX_2G   0x67

Definition at line 634 of file reg.h.

#define EEPROM_HT40_1S_TX_PWR_INX_5GH   0xA6

Definition at line 658 of file reg.h.

#define EEPROM_HT40_1S_TX_PWR_INX_5GL   0x7C

Definition at line 642 of file reg.h.

#define EEPROM_HT40_1S_TX_PWR_INX_5GM   0x91

Definition at line 650 of file reg.h.

#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G   0x6D

Definition at line 635 of file reg.h.

#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH   0xAC

Definition at line 659 of file reg.h.

#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL   0x82

Definition at line 643 of file reg.h.

#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM   0x97

Definition at line 651 of file reg.h.

#define EEPROM_HT40_MAX_PWR_OFFSET_2G   0x76

Definition at line 638 of file reg.h.

#define EEPROM_HT40_MAX_PWR_OFFSET_5GH   0xB5

Definition at line 662 of file reg.h.

#define EEPROM_HT40_MAX_PWR_OFFSET_5GL   0x8B

Definition at line 646 of file reg.h.

#define EEPROM_HT40_MAX_PWR_OFFSET_5GM   0xA0

Definition at line 654 of file reg.h.

#define EEPROM_IQK_DELTA   0xBC

Definition at line 667 of file reg.h.

#define EEPROM_LCK_DELTA   0xBC

Definition at line 668 of file reg.h.

#define EEPROM_MAC_ADDR   0x16 /* SEMAC Address. 12-17 */

Definition at line 628 of file reg.h.

#define EEPROM_MAC_ADDR_MAC0_92D   0x55

Definition at line 629 of file reg.h.

#define EEPROM_MAC_ADDR_MAC1_92D   0x5B

Definition at line 630 of file reg.h.

#define EEPROM_MAC_FUNCTION   0x08 /* SE Test mode.8 */

Definition at line 621 of file reg.h.

#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G   0x73

Definition at line 637 of file reg.h.

#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH   0xB2

Definition at line 661 of file reg.h.

#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL   0x88

Definition at line 645 of file reg.h.

#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM   0x9D

Definition at line 653 of file reg.h.

#define EEPROM_RF_OPT1   0xC4

Definition at line 674 of file reg.h.

#define EEPROM_RF_OPT2   0xC5

Definition at line 675 of file reg.h.

#define EEPROM_RF_OPT3   0xC6

Definition at line 676 of file reg.h.

#define EEPROM_RF_OPT4   0xC7

Definition at line 677 of file reg.h.

#define EEPROM_RF_OPT5   0xC8

Definition at line 678 of file reg.h.

#define EEPROM_RF_OPT6   0xC9

Definition at line 679 of file reg.h.

#define EEPROM_RF_OPT7   0xCC

Definition at line 682 of file reg.h.

#define EEPROM_SMID   0x2E /* SE PCI Subsystem ID. 10-11 */

Definition at line 626 of file reg.h.

#define EEPROM_SVID   0x2C /* SE Vendor ID.E-F */

Definition at line 625 of file reg.h.

#define EEPROM_THERMAL_METER   0xC3 /* [4:0] */

Definition at line 673 of file reg.h.

#define EEPROM_TSSI_A_5G   0xBE

Definition at line 670 of file reg.h.

#define EEPROM_TSSI_AB_5G   0xC0

Definition at line 672 of file reg.h.

#define EEPROM_TSSI_B_5G   0xBF

Definition at line 671 of file reg.h.

#define EEPROM_VERSION   0xCA

Definition at line 680 of file reg.h.

#define EEPROM_VID   0x28 /* SE Vendor ID.A-B */

Definition at line 623 of file reg.h.

#define EEPROM_WAPI_SUPPORT   0x78

Definition at line 615 of file reg.h.

#define EEPROM_XTAL_K   0xBD /* [7:5] */

Definition at line 669 of file reg.h.

#define EEPROME_CHIP_VERSION_H   0x3FE

Definition at line 686 of file reg.h.

#define EEPROME_CHIP_VERSION_L   0x3FF

Definition at line 685 of file reg.h.

#define EF_FLAG   BIT(31)

Definition at line 907 of file reg.h.

#define EF_PD   BIT(19)

Definition at line 906 of file reg.h.

#define EF_TRPT   BIT(7)

Definition at line 910 of file reg.h.

#define EFUSE_MAX_SECTION   32

Definition at line 572 of file reg.h.

#define EFUSE_REAL_CONTENT_LEN   512

Definition at line 573 of file reg.h.

#define EnPDN   BIT(4)

Definition at line 779 of file reg.h.

#define FEN_BB_GLB_RSTn   BIT(1)

Definition at line 758 of file reg.h.

#define FEN_BBRSTB   BIT(0)

Definition at line 757 of file reg.h.

#define FEN_CPUEN   BIT(10)

Definition at line 767 of file reg.h.

#define FEN_DCORE   BIT(11)

Definition at line 768 of file reg.h.

#define FEN_DIO_PCIE   BIT(5)

Definition at line 762 of file reg.h.

#define FEN_DIO_RF   BIT(13)

Definition at line 770 of file reg.h.

#define FEN_DIOE   BIT(9)

Definition at line 766 of file reg.h.

#define FEN_ELDR   BIT(12)

Definition at line 769 of file reg.h.

#define FEN_HWPDN   BIT(14)

Definition at line 771 of file reg.h.

#define FEN_MREGEN   BIT(15)

Definition at line 772 of file reg.h.

#define FEN_PCIEA   BIT(6)

Definition at line 763 of file reg.h.

#define FEN_PCIED   BIT(8)

Definition at line 765 of file reg.h.

#define FEN_PPLL   BIT(7)

Definition at line 764 of file reg.h.

#define FEN_UPLL   BIT(3)

Definition at line 760 of file reg.h.

#define FEN_USBA   BIT(2)

Definition at line 759 of file reg.h.

#define FEN_USBD   BIT(4)

Definition at line 761 of file reg.h.

#define FW_MAC0_READY   0x18

Definition at line 92 of file reg.h.

#define FW_MAC1_READY   0x1A

Definition at line 93 of file reg.h.

#define FWDL_ChkSum_rpt   BIT(2)

Definition at line 916 of file reg.h.

#define HALF_CAM_ENTRY   16

Definition at line 511 of file reg.h.

#define HWSET_MAX_SIZE   256

Definition at line 571 of file reg.h.

#define IC_MACPHY_MODE   BIT(11)

Definition at line 935 of file reg.h.

#define ICV   BIT(10)

Definition at line 988 of file reg.h.

#define IDR0   MACIDR0

Definition at line 362 of file reg.h.

#define IDR4   MACIDR4

Definition at line 363 of file reg.h.

#define IMR8190_DISABLED   0x0

Definition at line 527 of file reg.h.

#define IMR_ATIMEND   BIT(10)

Definition at line 549 of file reg.h.

#define IMR_BCNDMAINT1   BIT(26)

Definition at line 533 of file reg.h.

#define IMR_BCNDMAINT2   BIT(27)

Definition at line 532 of file reg.h.

#define IMR_BCNDMAINT3   BIT(28)

Definition at line 531 of file reg.h.

#define IMR_BCNDMAINT4   BIT(29)

Definition at line 530 of file reg.h.

#define IMR_BCNDMAINT5   BIT(30)

Definition at line 529 of file reg.h.

#define IMR_BCNDMAINT6   BIT(31)

Definition at line 528 of file reg.h.

#define IMR_BCNDOK1   BIT(18)

Definition at line 541 of file reg.h.

#define IMR_BCNDOK2   BIT(19)

Definition at line 540 of file reg.h.

#define IMR_BCNDOK3   BIT(20)

Definition at line 539 of file reg.h.

#define IMR_BCNDOK4   BIT(21)

Definition at line 538 of file reg.h.

#define IMR_BCNDOK5   BIT(22)

Definition at line 537 of file reg.h.

#define IMR_BCNDOK6   BIT(23)

Definition at line 536 of file reg.h.

#define IMR_BCNDOK7   BIT(24)

Definition at line 535 of file reg.h.

#define IMR_BCNDOK8   BIT(25)

Definition at line 534 of file reg.h.

#define IMR_BcnInt   BIT(13)

Definition at line 546 of file reg.h.

#define IMR_BDOK   BIT(9)

Definition at line 550 of file reg.h.

#define IMR_BEDOK   BIT(3)

Definition at line 556 of file reg.h.

#define IMR_BKDOK   BIT(4)

Definition at line 555 of file reg.h.

#define IMR_C2HCMD   BIT(9)

Definition at line 563 of file reg.h.

#define IMR_CPWM   BIT(8)

Definition at line 564 of file reg.h.

#define IMR_HIGHDOK   BIT(8)

Definition at line 551 of file reg.h.

#define IMR_MGNTDOK   BIT(6)

Definition at line 553 of file reg.h.

#define IMR_OCPINT   BIT(1)

Definition at line 565 of file reg.h.

#define IMR_PSTIMEOUT   BIT(14)

Definition at line 545 of file reg.h.

#define IMR_RDU   BIT(11)

Definition at line 548 of file reg.h.

#define IMR_ROK   BIT(0)

Definition at line 559 of file reg.h.

#define IMR_RXERR   BIT(10)

Definition at line 562 of file reg.h.

#define IMR_RXFOVW   BIT(12)

Definition at line 547 of file reg.h.

#define IMR_TBDER   BIT(5)

Definition at line 554 of file reg.h.

#define IMR_TBDOK   BIT(7)

Definition at line 552 of file reg.h.

#define IMR_TIMEOUT1   BIT(16)

Definition at line 543 of file reg.h.

#define IMR_TIMEOUT2   BIT(17)

Definition at line 542 of file reg.h.

#define IMR_TXERR   BIT(11)

Definition at line 561 of file reg.h.

#define IMR_TXFOVW   BIT(15)

Definition at line 544 of file reg.h.

#define IMR_VIDOK   BIT(2)

Definition at line 557 of file reg.h.

#define IMR_VODOK   BIT(1)

Definition at line 558 of file reg.h.

#define IMR_WLANOFF   BIT(0)

Definition at line 566 of file reg.h.

#define ISO_DIOE   BIT(7)

Definition at line 748 of file reg.h.

#define ISO_DIOP   BIT(6)

Definition at line 747 of file reg.h.

#define ISO_DIOR   BIT(9)

Definition at line 750 of file reg.h.

#define ISO_EB2CORE   BIT(8)

Definition at line 749 of file reg.h.

#define ISO_IP2MAC   BIT(5)

Definition at line 746 of file reg.h.

#define ISO_MD2PP   BIT(0)

Definition at line 741 of file reg.h.

#define ISO_PA2PCIE   BIT(3)

Definition at line 744 of file reg.h.

#define ISO_PD2CORE   BIT(4)

Definition at line 745 of file reg.h.

#define ISO_UA2USB   BIT(1)

Definition at line 742 of file reg.h.

#define ISO_UD2CORE   BIT(2)

Definition at line 743 of file reg.h.

#define ISR   REG_HISR

Definition at line 354 of file reg.h.

#define LAST_ENTRY_OF_TX_PKT_BUFFER   255

Definition at line 1001 of file reg.h.

#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC   127

Definition at line 1002 of file reg.h.

#define LDA15_EN   BIT(0)

Definition at line 843 of file reg.h.

#define LDA15_OBUF   BIT(2)

Definition at line 845 of file reg.h.

#define LDA15_REG_VOS   BIT(3)

Definition at line 846 of file reg.h.

#define LDA15_STBY   BIT(1)

Definition at line 844 of file reg.h.

#define LDOE25_EN   BIT(31)

Definition at line 911 of file reg.h.

#define LDV12_EN   BIT(0)

Definition at line 852 of file reg.h.

#define LDV12_SDBY   BIT(1)

Definition at line 853 of file reg.h.

#define LOADER_CLK_EN   BIT(5)

Definition at line 806 of file reg.h.

#define LOCK_ALL_EN   BIT(7)

Definition at line 833 of file reg.h.

#define LPLDO_HSM   BIT(2)

Definition at line 854 of file reg.h.

#define LPLDO_LSM_DIS   BIT(3)

Definition at line 855 of file reg.h.

#define MAC0_ON   BIT(7)

Definition at line 94 of file reg.h.

#define MAC0_READY   BIT(0)

Definition at line 96 of file reg.h.

#define MAC1_ON   BIT(0)

Definition at line 95 of file reg.h.

#define MAC1_READY   BIT(0)

Definition at line 97 of file reg.h.

#define MAC1_WINTINI_RDY   BIT(11)

Definition at line 921 of file reg.h.

#define MAC_CLK_EN   BIT(11)

Definition at line 811 of file reg.h.

#define MAC_ID_EN   BIT(7)

Definition at line 823 of file reg.h.

#define MACIDR0   REG_MACID

Definition at line 357 of file reg.h.

#define MACIDR4   (REG_MACID + 4)

Definition at line 358 of file reg.h.

#define MACINI_RDY   BIT(3)

Definition at line 917 of file reg.h.

#define MACSLP   BIT(4)

Definition at line 805 of file reg.h.

#define MAX_MSS_DENSITY_1T   0x0A

Definition at line 1009 of file reg.h.

#define MAX_MSS_DENSITY_2T   0x13

Definition at line 1008 of file reg.h.

#define MCUFWDL_EN   BIT(0)

Definition at line 914 of file reg.h.

#define MCUFWDL_RDY   BIT(1)

Definition at line 915 of file reg.h.

#define MSR   (REG_CR + 2)

Definition at line 353 of file reg.h.

#define MSR_ADHOC   0x01

Definition at line 369 of file reg.h.

#define MSR_AP   0x03

Definition at line 371 of file reg.h.

#define MSR_INFRA   0x02

Definition at line 370 of file reg.h.

#define MSR_NOLINK   0x00

Definition at line 368 of file reg.h.

#define PAD_HWPD_IDN   BIT(22)

Definition at line 936 of file reg.h.

#define PAD_SEL   BIT(2)

Definition at line 983 of file reg.h.

#define PBP   REG_PBP

Definition at line 360 of file reg.h.

#define PCIRSTB   BIT(4)

Definition at line 929 of file reg.h.

#define PCLK_VLD   BIT(3)

Definition at line 928 of file reg.h.

#define PDN_PL   BIT(5)

Definition at line 780 of file reg.h.

#define PFM_ALDN   BIT(1)

Definition at line 776 of file reg.h.

#define PFM_LDALL   BIT(0)

Definition at line 775 of file reg.h.

#define PFM_LDKP   BIT(2)

Definition at line 777 of file reg.h.

#define PFM_WOWL   BIT(3)

Definition at line 778 of file reg.h.

#define PHY_SSC_RSTB   BIT(9)

Definition at line 809 of file reg.h.

#define POLLING_LLT_THRESHOLD   20

Definition at line 1004 of file reg.h.

#define POLLING_READY_TIMEOUT_COUNT   1000

Definition at line 1005 of file reg.h.

#define PWC_EV12V   BIT(15)

Definition at line 753 of file reg.h.

#define PWC_EV25V   BIT(14)

Definition at line 752 of file reg.h.

#define PWR_ST   BIT(6)

Definition at line 984 of file reg.h.

#define PWRBIT_OW_EN   BIT(7)

Definition at line 985 of file reg.h.

#define R_DIS_PRST_0   BIT(5)

Definition at line 831 of file reg.h.

#define R_DIS_PRST_1   BIT(6)

Definition at line 832 of file reg.h.

#define RATE_11M   BIT(3)

Definition at line 445 of file reg.h.

#define RATE_12M   BIT(6)

Definition at line 449 of file reg.h.

#define RATE_18M   BIT(7)

Definition at line 450 of file reg.h.

#define RATE_1M   BIT(0)

Definition at line 442 of file reg.h.

#define RATE_24M   BIT(8)

Definition at line 451 of file reg.h.

#define RATE_2M   BIT(1)

Definition at line 443 of file reg.h.

#define RATE_36M   BIT(9)

Definition at line 452 of file reg.h.

#define RATE_48M   BIT(10)

Definition at line 453 of file reg.h.

#define RATE_54M   BIT(11)

Definition at line 454 of file reg.h.

#define RATE_5_5M   BIT(2)

Definition at line 444 of file reg.h.

#define RATE_6M   BIT(4)

Definition at line 447 of file reg.h.

#define RATE_9M   BIT(5)

Definition at line 448 of file reg.h.

#define RATE_ALL_CCK
Value:
(RATR_1M | RATR_2M | RATR_55M | \
RATR_11M)

Definition at line 475 of file reg.h.

#define RATE_ALL_OFDM_1SS
Value:
(RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \
RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
RATR_MCS6 | RATR_MCS7)

Definition at line 480 of file reg.h.

#define RATE_ALL_OFDM_2SS
Value:
(RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \
RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
RATR_MCS14 | RATR_MCS15)

Definition at line 483 of file reg.h.

#define RATE_ALL_OFDM_AG
Value:
(RATR_6M | RATR_9M | RATR_12M | \
RATR_18M | RATR_24M | \
RATR_36M | RATR_48M | RATR_54M)

Definition at line 477 of file reg.h.

#define RATE_MCS0   BIT(12)

Definition at line 456 of file reg.h.

#define RATE_MCS1   BIT(13)

Definition at line 457 of file reg.h.

#define RATE_MCS10   BIT(22)

Definition at line 467 of file reg.h.

#define RATE_MCS11   BIT(23)

Definition at line 468 of file reg.h.

#define RATE_MCS12   BIT(24)

Definition at line 469 of file reg.h.

#define RATE_MCS13   BIT(25)

Definition at line 470 of file reg.h.

#define RATE_MCS14   BIT(26)

Definition at line 471 of file reg.h.

#define RATE_MCS15   BIT(27)

Definition at line 472 of file reg.h.

#define RATE_MCS2   BIT(14)

Definition at line 458 of file reg.h.

#define RATE_MCS3   BIT(15)

Definition at line 459 of file reg.h.

#define RATE_MCS4   BIT(16)

Definition at line 460 of file reg.h.

#define RATE_MCS5   BIT(17)

Definition at line 461 of file reg.h.

#define RATE_MCS6   BIT(18)

Definition at line 462 of file reg.h.

#define RATE_MCS7   BIT(19)

Definition at line 463 of file reg.h.

#define RATE_MCS8   BIT(20)

Definition at line 465 of file reg.h.

#define RATE_MCS9   BIT(21)

Definition at line 466 of file reg.h.

#define RATR_11M   0x00000008

Definition at line 412 of file reg.h.

#define RATR_12M   0x00000040

Definition at line 416 of file reg.h.

#define RATR_18M   0x00000080

Definition at line 417 of file reg.h.

#define RATR_1M   0x00000001

Definition at line 409 of file reg.h.

#define RATR_24M   0x00000100

Definition at line 418 of file reg.h.

#define RATR_2M   0x00000002

Definition at line 410 of file reg.h.

#define RATR_36M   0x00000200

Definition at line 419 of file reg.h.

#define RATR_48M   0x00000400

Definition at line 420 of file reg.h.

#define RATR_54M   0x00000800

Definition at line 421 of file reg.h.

#define RATR_55M   0x00000004

Definition at line 411 of file reg.h.

#define RATR_6M   0x00000010

Definition at line 414 of file reg.h.

#define RATR_9M   0x00000020

Definition at line 415 of file reg.h.

#define RATR_MCS0   0x00001000

Definition at line 423 of file reg.h.

#define RATR_MCS1   0x00002000

Definition at line 424 of file reg.h.

#define RATR_MCS10   0x00400000

Definition at line 434 of file reg.h.

#define RATR_MCS11   0x00800000

Definition at line 435 of file reg.h.

#define RATR_MCS12   0x01000000

Definition at line 436 of file reg.h.

#define RATR_MCS13   0x02000000

Definition at line 437 of file reg.h.

#define RATR_MCS14   0x04000000

Definition at line 438 of file reg.h.

#define RATR_MCS15   0x08000000

Definition at line 439 of file reg.h.

#define RATR_MCS2   0x00004000

Definition at line 425 of file reg.h.

#define RATR_MCS3   0x00008000

Definition at line 426 of file reg.h.

#define RATR_MCS4   0x00010000

Definition at line 427 of file reg.h.

#define RATR_MCS5   0x00020000

Definition at line 428 of file reg.h.

#define RATR_MCS6   0x00040000

Definition at line 429 of file reg.h.

#define RATR_MCS7   0x00080000

Definition at line 430 of file reg.h.

#define RATR_MCS8   0x00100000

Definition at line 432 of file reg.h.

#define RATR_MCS9   0x00200000

Definition at line 433 of file reg.h.

#define RCCK0_AFESSTTING   0xa04

Definition at line 1081 of file reg.h.

#define RCCK0_CCA   0xa08

Definition at line 1082 of file reg.h.

#define RCCK0_DEBUGPORT   0xa28

Definition at line 1094 of file reg.h.

#define RCCK0_DSPPARAMETER1   0xa18

Definition at line 1089 of file reg.h.

#define RCCK0_DSPPARAMETER2   0xa1c

Definition at line 1090 of file reg.h.

#define RCCK0_FACOUNTERLOWER   0xa5c

Definition at line 1098 of file reg.h.

#define RCCK0_FACOUNTERUPPER   0xa58

Definition at line 1099 of file reg.h.

#define RCCK0_FALSEALARMREPORT   0xa2c

Definition at line 1095 of file reg.h.

#define RCCK0_RXAGC1   0xa0c

Definition at line 1084 of file reg.h.

#define RCCK0_RXAGC2   0xa10

Definition at line 1085 of file reg.h.

#define RCCK0_RXHP   0xa14

Definition at line 1087 of file reg.h.

#define RCCK0_RXREPORT   0xa54

Definition at line 1097 of file reg.h.

#define RCCK0_SYSTEM   0xa00

Definition at line 1079 of file reg.h.

#define RCCK0_TRSSIREPORT   0xa50

Definition at line 1096 of file reg.h.

#define RCCK0_TXFILTER1   0xa20

Definition at line 1092 of file reg.h.

#define RCCK0_TXFILTER2   0xa24

Definition at line 1093 of file reg.h.

#define RCR_AAP   BIT(0)

Definition at line 725 of file reg.h.

#define RCR_AB   BIT(3)

Definition at line 722 of file reg.h.

#define RCR_ACF   BIT(12)

Definition at line 714 of file reg.h.

#define RCR_ACRC32   BIT(8)

Definition at line 717 of file reg.h.

#define RCR_ADD3   BIT(4)

Definition at line 721 of file reg.h.

#define RCR_ADF   BIT(11)

Definition at line 715 of file reg.h.

#define RCR_AICV   BIT(9)

Definition at line 716 of file reg.h.

#define RCR_AM   BIT(2)

Definition at line 723 of file reg.h.

#define RCR_AMF   BIT(13)

Definition at line 713 of file reg.h.

#define RCR_APM   BIT(1)

Definition at line 724 of file reg.h.

#define RCR_APP_BA_SSN   BIT(27)

Definition at line 708 of file reg.h.

#define RCR_APP_ICV   BIT(29)

Definition at line 706 of file reg.h.

#define RCR_APP_MIC   BIT(30)

Definition at line 705 of file reg.h.

#define RCR_APP_PHYST_RXFF   BIT(28)

Definition at line 707 of file reg.h.

#define RCR_APPFCS   BIT(31)

Definition at line 704 of file reg.h.

#define RCR_APWRMGT   BIT(5)

Definition at line 720 of file reg.h.

#define RCR_CBSSID_BCN   BIT(7)

Definition at line 718 of file reg.h.

#define RCR_CBSSID_DATA   BIT(6)

Definition at line 719 of file reg.h.

#define RCR_ENMBID   BIT(24)

Definition at line 709 of file reg.h.

#define RCR_FIFO_OFFSET   13

Definition at line 727 of file reg.h.

#define RCR_HTC_LOC_CTRL   BIT(14)

Definition at line 712 of file reg.h.

#define RCR_LSIGEN   BIT(23)

Definition at line 710 of file reg.h.

#define RCR_MFBEN   BIT(22)

Definition at line 711 of file reg.h.

#define RCR_MXDMA_OFFSET   8

Definition at line 726 of file reg.h.

#define RDY_MACON   BIT(16)

Definition at line 789 of file reg.h.

#define REG_9346CR   0x000A

Definition at line 40 of file reg.h.

#define REG_ACKTO   0x0640

Definition at line 310 of file reg.h.

#define REG_ACLK_MON   0x003E

Definition at line 60 of file reg.h.

#define REG_ACMAVG   0x05C2

Definition at line 280 of file reg.h.

#define REG_ACMHWCTRL   0x05C0

Definition at line 278 of file reg.h.

#define REG_ACMRSTCTRL   0x05C1

Definition at line 279 of file reg.h.

#define REG_AFE_MISC   0x0010

Definition at line 42 of file reg.h.

#define REG_AFE_PLL_CTRL   0x0028

Definition at line 53 of file reg.h.

#define REG_AFE_XTAL_CTRL   0x0024

Definition at line 52 of file reg.h.

#define REG_AGGLEN_LMT   0x0458

Definition at line 215 of file reg.h.

#define REG_AGGR_BREAK_TIME   0x051A

Definition at line 252 of file reg.h.

#define REG_AMPDU_MIN_SPACE   0x045C

Definition at line 216 of file reg.h.

#define REG_APS_FSMCO   0x0004

Definition at line 38 of file reg.h.

#define REG_APSD_CTRL   0x0600

Definition at line 293 of file reg.h.

#define REG_ARFR0   0x0444

Definition at line 211 of file reg.h.

#define REG_ARFR1   0x0448

Definition at line 212 of file reg.h.

#define REG_ARFR2   0x044C

Definition at line 213 of file reg.h.

#define REG_ARFR3   0x0450

Definition at line 214 of file reg.h.

#define REG_ATIMWND   0x055A

Definition at line 269 of file reg.h.

#define REG_BACAMCMD   0x0654

Definition at line 317 of file reg.h.

#define REG_BACAMCONTENT   0x0658

Definition at line 318 of file reg.h.

#define REG_BAR_MODE_CTRL   0x04CC

Definition at line 230 of file reg.h.

#define REG_BB_ACCEESS_CTRL   0x01E8

Definition at line 140 of file reg.h.

#define REG_BB_ACCESS_DATA   0x01EC

Definition at line 141 of file reg.h.

#define REG_BCN_CTRL   0x0550

Definition at line 261 of file reg.h.

#define REG_BCN_INTERVAL   0x0554

Definition at line 265 of file reg.h.

#define REG_BCN_MAX_ERR   0x055D

Definition at line 270 of file reg.h.

#define REG_BCN_PSR_RPT   0x06A8

Definition at line 342 of file reg.h.

#define REG_BCNDMATIM   0x0559

Definition at line 268 of file reg.h.

#define REG_BCNQ_DESA   0x0308

Definition at line 166 of file reg.h.

#define REG_BCNQ_INFORMATION   0x0418

Definition at line 196 of file reg.h.

#define REG_BCNTCFG   0x0510

Definition at line 247 of file reg.h.

#define REG_BE_ADMTIME   0x05C8

Definition at line 283 of file reg.h.

#define REG_BEQ_DESA   0x0330

Definition at line 171 of file reg.h.

#define REG_BEQ_INFORMATION   0x0408

Definition at line 192 of file reg.h.

#define REG_BIST_ROM_RPT   0x00D8

Definition at line 82 of file reg.h.

#define REG_BIST_RPT   0x00D4

Definition at line 81 of file reg.h.

#define REG_BIST_SCAN   0x00D0

Definition at line 80 of file reg.h.

#define REG_BKQ_DESA   0x0338

Definition at line 172 of file reg.h.

#define REG_BKQ_INFORMATION   0x040C

Definition at line 193 of file reg.h.

#define REG_BSSID   0x0618

Definition at line 302 of file reg.h.

#define REG_BT_COEX_TABLE   0x06C0

Definition at line 345 of file reg.h.

#define REG_BWOPMODE   0x0603

Definition at line 294 of file reg.h.

#define REG_C2HEVT_CLEAR   0x01BF

Definition at line 130 of file reg.h.

#define REG_C2HEVT_MSG_NORMAL   0x01A0

Definition at line 128 of file reg.h.

#define REG_C2HEVT_MSG_TEST   0x01B8

Definition at line 129 of file reg.h.

#define REG_CAL_TIMER   0x003C

Definition at line 59 of file reg.h.

#define REG_CALB32K_CTRL   0x06AC

Definition at line 343 of file reg.h.

#define REG_CAMCMD   0x0670

Definition at line 326 of file reg.h.

#define REG_CAMDBG   0x067C

Definition at line 329 of file reg.h.

#define REG_CAMREAD   0x0678

Definition at line 328 of file reg.h.

#define REG_CAMWRITE   0x0674

Definition at line 327 of file reg.h.

#define REG_CPU_MGQ_INFORMATION   0x041C

Definition at line 199 of file reg.h.

#define REG_CPWM   0x012F

Definition at line 112 of file reg.h.

#define REG_CR   0x0100

Definition at line 102 of file reg.h.

#define REG_CTS2TO   0x0641

Definition at line 311 of file reg.h.

#define REG_DARFRC   0x0430

Definition at line 208 of file reg.h.

#define REG_DBG_SEL   0x0360

Definition at line 180 of file reg.h.

#define REG_DBI   0x0348

Definition at line 174 of file reg.h.

#define REG_DBI_CTRL   0x0350

Definition at line 177 of file reg.h.

#define REG_DBI_FLAG   0x0352

Definition at line 178 of file reg.h.

#define REG_DBI_RDATA   0x034C

Definition at line 176 of file reg.h.

#define REG_DBI_WDATA   0x0348

Definition at line 175 of file reg.h.

#define REG_DIS_TXREQ_CLR   0x0523

Definition at line 256 of file reg.h.

#define REG_DMC   0x05F0

Definition at line 288 of file reg.h.

#define REG_DRVERLYINT   0x0558

Definition at line 267 of file reg.h.

#define REG_DUAL_TSF_RST   0x0553

Definition at line 264 of file reg.h.

#define REG_DUMMY   0x04FC

Definition at line 238 of file reg.h.

#define REG_EARLY_MODE_CONTROL   0x4D0

Definition at line 232 of file reg.h.

#define REG_EDCA_BE_PARAM   0x0508

Definition at line 245 of file reg.h.

#define REG_EDCA_BK_PARAM   0x050C

Definition at line 246 of file reg.h.

#define REG_EDCA_RANDOM_GEN   0x05CC

Definition at line 284 of file reg.h.

#define REG_EDCA_VI_PARAM   0x0504

Definition at line 244 of file reg.h.

#define REG_EDCA_VO_PARAM   0x0500

Definition at line 243 of file reg.h.

#define REG_EE_VPD   0x000C

Definition at line 41 of file reg.h.

#define REG_EFUSE_CTRL   0x0030

Definition at line 56 of file reg.h.

#define REG_EFUSE_TEST   0x0034

Definition at line 57 of file reg.h.

#define REG_EIFS   0x0642

Definition at line 312 of file reg.h.

#define REG_FAST_EDCA_CTRL   0x0460

Definition at line 218 of file reg.h.

#define REG_FIFOPAGE   0x0204

Definition at line 148 of file reg.h.

#define REG_FMETHR   0x01C8

Definition at line 132 of file reg.h.

#define REG_FSIMR   0x0050

Definition at line 70 of file reg.h.

#define REG_FSISR   0x0054

Definition at line 71 of file reg.h.

#define REG_FWDLY   0x0661

Definition at line 320 of file reg.h.

#define REG_FWHW_TXQ_CTRL   0x0420

Definition at line 200 of file reg.h.

#define REG_FWIMR   0x0130

Definition at line 113 of file reg.h.

#define REG_FWISR   0x0134

Definition at line 114 of file reg.h.

#define REG_GPIO_INTM   0x0048

Definition at line 65 of file reg.h.

#define REG_GPIO_IO_SEL   0x0042

Definition at line 62 of file reg.h.

#define REG_GPIO_MUXCFG   0x0040

Definition at line 61 of file reg.h.

#define REG_GPIO_PIN_CTRL   0x0044

Definition at line 64 of file reg.h.

#define REG_HGQ_INFORMATION   0x0414

Definition at line 195 of file reg.h.

#define REG_HIMR   0x0120

Definition at line 108 of file reg.h.

#define REG_HIMRE   0x0128

Definition at line 110 of file reg.h.

#define REG_HISR   0x0124

Definition at line 109 of file reg.h.

#define REG_HISRE   0x012C

Definition at line 111 of file reg.h.

#define REG_HMEBOX_0   0x01D0

Definition at line 134 of file reg.h.

#define REG_HMEBOX_1   0x01D4

Definition at line 135 of file reg.h.

#define REG_HMEBOX_2   0x01D8

Definition at line 136 of file reg.h.

#define REG_HMEBOX_3   0x01DC

Definition at line 137 of file reg.h.

#define REG_HMEBOX_EXT_0   0x0088

Definition at line 75 of file reg.h.

#define REG_HMEBOX_EXT_1   0x008A

Definition at line 76 of file reg.h.

#define REG_HMEBOX_EXT_2   0x008C

Definition at line 77 of file reg.h.

#define REG_HMEBOX_EXT_3   0x008E

Definition at line 78 of file reg.h.

#define REG_HMETFR   0x01CC

Definition at line 133 of file reg.h.

#define REG_HPON_FSM   0x00EC

Definition at line 86 of file reg.h.

#define REG_HQ_DESA   0x0310

Definition at line 167 of file reg.h.

#define REG_HWSEQ_CTRL   0x0423

Definition at line 201 of file reg.h.

#define REG_INIDATA_RATE_SEL   0x0484

Definition at line 221 of file reg.h.

#define REG_INIRTS_RATE_SEL   0x0480

Definition at line 220 of file reg.h.

#define REG_INIT_TSFTR   0x0564

Definition at line 274 of file reg.h.

#define REG_INT_MIG   0x0304

Definition at line 165 of file reg.h.

#define REG_LBDLY   0x0660

Definition at line 319 of file reg.h.

#define REG_LDOA15_CTRL   0x0020

Definition at line 48 of file reg.h.

#define REG_LDOHCI12_CTRL   0x0022

Definition at line 50 of file reg.h.

#define REG_LDOV12D_CTRL   0x0021

Definition at line 49 of file reg.h.

#define REG_LEDCFG0   0x004C

Definition at line 66 of file reg.h.

#define REG_LEDCFG1   0x004D

Definition at line 67 of file reg.h.

#define REG_LEDCFG2   0x004E

Definition at line 68 of file reg.h.

#define REG_LEDCFG3   0x004F

Definition at line 69 of file reg.h.

#define REG_LLT_INIT   0x01E0

Definition at line 139 of file reg.h.

#define REG_LPLDO_CTRL   0x0023

Definition at line 51 of file reg.h.

#define REG_LPNAV_CTRL   0x0694

Definition at line 336 of file reg.h.

#define REG_MAC0   0x0081

Definition at line 90 of file reg.h.

#define REG_MAC1   0x0053

Definition at line 91 of file reg.h.

#define REG_MAC_PHY_CTRL   0x002c

Definition at line 55 of file reg.h.

#define REG_MAC_PHY_CTRL_NORMAL   0x00f8

Definition at line 88 of file reg.h.

#define REG_MAC_PINMUX_CFG   0x0043

Definition at line 63 of file reg.h.

#define REG_MAC_SPEC_SIFS   0x063A

Definition at line 307 of file reg.h.

#define REG_MACID   0x0610

Definition at line 301 of file reg.h.

#define REG_MAR   0x0620

Definition at line 303 of file reg.h.

#define REG_MAX_AGGR_NUM   0x04CA

Definition at line 228 of file reg.h.

#define REG_MBID_NUM   0x0552

Definition at line 263 of file reg.h.

#define REG_MBIDCAMCFG   0x0628

Definition at line 304 of file reg.h.

#define REG_MBIST_DONE   0x0178

Definition at line 126 of file reg.h.

#define REG_MBIST_FAIL   0x017C

Definition at line 127 of file reg.h.

#define REG_MBIST_START   0x0174

Definition at line 125 of file reg.h.

#define REG_MBSSID_BCN_SPACE   0x0554

Definition at line 266 of file reg.h.

#define REG_MCUFWDL   0x0080

Definition at line 73 of file reg.h.

#define REG_MCUTST_1   0x01c0

Definition at line 131 of file reg.h.

#define REG_MDIO   0x0354

Definition at line 179 of file reg.h.

#define REG_MGQ_DESA   0x0318

Definition at line 168 of file reg.h.

#define REG_MGQ_INFORMATION   0x0410

Definition at line 194 of file reg.h.

#define REG_MULTI_BCNQ_EN   0x0426

Definition at line 204 of file reg.h.

#define REG_MULTI_BCNQ_OFFSET   0x0427

Definition at line 205 of file reg.h.

#define REG_NAV_CTRL   0x0650

Definition at line 316 of file reg.h.

#define REG_NAV_PROT_LEN   0x0546

Definition at line 260 of file reg.h.

#define REG_NEED_CPU_HANDLE   0x04E0

Definition at line 235 of file reg.h.

#define REG_NQOS_SEQ   0x04DC

Definition at line 233 of file reg.h.

#define REG_PBP   0x0104

Definition at line 103 of file reg.h.

#define REG_PCIE_CTRL_REG   0x0300

Definition at line 164 of file reg.h.

#define REG_PCIE_HCPWM   0x0363

Definition at line 182 of file reg.h.

#define REG_PCIE_HRPWM   0x0361

Definition at line 181 of file reg.h.

#define REG_PCIE_MIO_INTD   0x00E8

Definition at line 85 of file reg.h.

#define REG_PCIE_MIO_INTF   0x00E4

Definition at line 84 of file reg.h.

#define REG_PIFS   0x0512

Definition at line 248 of file reg.h.

#define REG_PKT_LIFE_TIME   0x04C0

Definition at line 225 of file reg.h.

#define REG_PKT_LOSE_RPT   0x04E1

Definition at line 236 of file reg.h.

#define REG_PKT_MON_CTRL   0x06B4

Definition at line 344 of file reg.h.

#define REG_PKTBUF_DBG_CTRL   0x0140

Definition at line 115 of file reg.h.

#define REG_PKTBUF_DBG_DATA_H   0x0148

Definition at line 117 of file reg.h.

#define REG_PKTBUF_DBG_DATA_L   0x0144

Definition at line 116 of file reg.h.

#define REG_POWER_OFF_IN_PROCESS   0x0017

Definition at line 44 of file reg.h.

#define REG_POWER_STAGE1   0x04B4

Definition at line 223 of file reg.h.

#define REG_POWER_STAGE2   0x04B8

Definition at line 224 of file reg.h.

#define REG_POWER_STATUS   0x04A4

Definition at line 222 of file reg.h.

#define REG_PROT_MODE_CTRL   0x04C8

Definition at line 227 of file reg.h.

#define REG_PS_RX_INFO   0x0692

Definition at line 335 of file reg.h.

#define REG_PSSTATUS   0x0691

Definition at line 334 of file reg.h.

#define REG_PSTIMER   0x0580

Definition at line 275 of file reg.h.

#define REG_PTCL_ERR_STATUS   0x04E2

Definition at line 237 of file reg.h.

#define REG_PWR_DATA   0x0038

Definition at line 58 of file reg.h.

#define REG_QOS_SEQ   0x04DE

Definition at line 234 of file reg.h.

#define REG_RA_TRY_RATE_AGG_LMT   0x04CF

Definition at line 231 of file reg.h.

#define REG_RARFRC   0x0438

Definition at line 209 of file reg.h.

#define REG_RCR   0x0608

Definition at line 296 of file reg.h.

#define REG_RD_CTRL   0x0524

Definition at line 257 of file reg.h.

#define REG_RD_NAV_NXT   0x0544

Definition at line 259 of file reg.h.

#define REG_RD_RESP_PKT_TH   0x0463

Definition at line 219 of file reg.h.

#define REG_RDG_PIFS   0x0513

Definition at line 249 of file reg.h.

#define REG_RESP_SIFS_CCK   0x063C

Definition at line 308 of file reg.h.

#define REG_RESP_SIFS_OFDM   0x063E

Definition at line 309 of file reg.h.

#define REG_RF_CTRL   0x001F

Definition at line 47 of file reg.h.

#define REG_RL   0x042A

Definition at line 207 of file reg.h.

#define REG_RQPN   0x0200

Definition at line 147 of file reg.h.

#define REG_RQPN_NPQ   0x0214

Definition at line 152 of file reg.h.

#define REG_RRSR   0x0440

Definition at line 210 of file reg.h.

#define REG_RSV_CTRL   0x001C

Definition at line 46 of file reg.h.

#define REG_RTS_MAX_AGGR_NUM   0x04CB

Definition at line 229 of file reg.h.

#define REG_RX_DESA   0x0340

Definition at line 173 of file reg.h.

#define REG_RX_DLK_TIME   0x060D

Definition at line 298 of file reg.h.

#define REG_RX_DRVINFO_SZ   0x060F

Definition at line 299 of file reg.h.

#define REG_RX_PKT_LIMIT   0x060C

Definition at line 297 of file reg.h.

#define REG_RXDMA_AGG_PG_TH   0x0280

Definition at line 157 of file reg.h.

#define REG_RXDMA_STATUS   0x0288

Definition at line 159 of file reg.h.

#define REG_RXERR_RPT   0x0664

Definition at line 321 of file reg.h.

#define REG_RXFF_PTR   0x011C

Definition at line 107 of file reg.h.

#define REG_RXFLTMAP0   0x06A0

Definition at line 339 of file reg.h.

#define REG_RXFLTMAP1   0x06A2

Definition at line 340 of file reg.h.

#define REG_RXFLTMAP2   0x06A4

Definition at line 341 of file reg.h.

#define REG_RXPKT_NUM   0x0284

Definition at line 158 of file reg.h.

#define REG_RXTSF_OFFSET_CCK   0x055E

Definition at line 271 of file reg.h.

#define REG_RXTSF_OFFSET_OFDM   0x055F

Definition at line 272 of file reg.h.

#define REG_SCH_TXCMD   0x05D0

Definition at line 285 of file reg.h.

#define REG_SECCFG   0x0680

Definition at line 330 of file reg.h.

#define REG_SIFS_CTX   0x0514

Definition at line 250 of file reg.h.

#define REG_SIFS_TRX   0x0516

Definition at line 251 of file reg.h.

#define REG_SLOT   0x051B

Definition at line 253 of file reg.h.

#define REG_SPEC_SIFS   0x0428

Definition at line 206 of file reg.h.

#define REG_SPS0_CTRL   0x0011

Definition at line 43 of file reg.h.

#define REG_SPS_OCP_CFG   0x0018

Definition at line 45 of file reg.h.

#define REG_STBC_SETTING   0x04C4

Definition at line 226 of file reg.h.

#define REG_SYS_CFG   0x00F0

Definition at line 87 of file reg.h.

#define REG_SYS_CLKR   0x0008

Definition at line 39 of file reg.h.

#define REG_SYS_FUNC_EN   0x0002

Definition at line 37 of file reg.h.

#define REG_SYS_ISO_CTRL   0x0000

Definition at line 36 of file reg.h.

#define REG_TBTT_PROHIBIT   0x0540

Definition at line 258 of file reg.h.

#define REG_TC0_CTRL   0x0150

Definition at line 119 of file reg.h.

#define REG_TC1_CTRL   0x0154

Definition at line 120 of file reg.h.

#define REG_TC2_CTRL   0x0158

Definition at line 121 of file reg.h.

#define REG_TC3_CTRL   0x015C

Definition at line 122 of file reg.h.

#define REG_TC4_CTRL   0x0160

Definition at line 123 of file reg.h.

#define REG_TCR   0x0604

Definition at line 295 of file reg.h.

#define REG_TCUNIT_BASE   0x0164

Definition at line 124 of file reg.h.

#define REG_TDECTRL   0x0208

Definition at line 149 of file reg.h.

#define REG_TIMER0   0x0584

Definition at line 276 of file reg.h.

#define REG_TIMER1   0x0588

Definition at line 277 of file reg.h.

#define REG_TRXDMA_CTRL   0x010C

Definition at line 104 of file reg.h.

#define REG_TRXFF_BNDY   0x0114

Definition at line 105 of file reg.h.

#define REG_TRXFF_STATUS   0x0118

Definition at line 106 of file reg.h.

#define REG_TSFTR   0x0560

Definition at line 273 of file reg.h.

#define REG_TX_PTCL_CTRL   0x0520

Definition at line 254 of file reg.h.

#define REG_TXDMA_OFFSET_CHK   0x020C

Definition at line 150 of file reg.h.

#define REG_TXDMA_STATUS   0x0210

Definition at line 151 of file reg.h.

#define REG_TXPAUSE   0x0522

Definition at line 255 of file reg.h.

#define REG_TXPKTBUF_BCNQ_BDNY   0x0424

Definition at line 202 of file reg.h.

#define REG_TXPKTBUF_MGQ_BDNY   0x0425

Definition at line 203 of file reg.h.

#define REG_TXPKTBUF_WMAC_LBK_BF_HD   0x045D

Definition at line 217 of file reg.h.

#define REG_UART_CTRL   0x0364

Definition at line 183 of file reg.h.

#define REG_UART_RX_DESA   0x0378

Definition at line 185 of file reg.h.

#define REG_UART_TX_DESA   0x0370

Definition at line 184 of file reg.h.

#define REG_USB_SIE_INTF   0x00E0

Definition at line 83 of file reg.h.

#define REG_USTIME_EDCA   0x0638

Definition at line 306 of file reg.h.

#define REG_USTIME_TSF   0x0551

Definition at line 262 of file reg.h.

#define REG_VI_ADMTIME   0x05C6

Definition at line 282 of file reg.h.

#define REG_VIQ_DESA   0x0328

Definition at line 170 of file reg.h.

#define REG_VIQ_INFORMATION   0x0404

Definition at line 191 of file reg.h.

#define REG_VO_ADMTIME   0x05C4

Definition at line 281 of file reg.h.

#define REG_VOQ_DESA   0x0320

Definition at line 169 of file reg.h.

#define REG_VOQ_INFORMATION   0x0400

Definition at line 190 of file reg.h.

#define REG_WKFMCAM_CMD   0x0698

Definition at line 337 of file reg.h.

#define REG_WKFMCAM_RWD   0x069C

Definition at line 338 of file reg.h.

#define REG_WMAC_RESP_TXINFO   0x06D8

Definition at line 346 of file reg.h.

#define REG_WMAC_TRXPTCL_CTL   0x0668

Definition at line 322 of file reg.h.

#define REG_WOW_CTRL   0x0690

Definition at line 333 of file reg.h.

#define RETRY_LIMIT_LONG_SHIFT   0

Definition at line 958 of file reg.h.

#define RETRY_LIMIT_SHORT_SHIFT   8

Definition at line 957 of file reg.h.

#define RF_AC   0x00

Definition at line 1213 of file reg.h.

#define RF_BIAS   0x14

Definition at line 1230 of file reg.h.

#define RF_BS_IQGEN   0x0F

Definition at line 1223 of file reg.h.

#define RF_CHNLBW   0x18

Definition at line 1235 of file reg.h.

#define RF_EN   BIT(0)

Definition at line 836 of file reg.h.

#define RF_GAIN_RX   0x06

Definition at line 1219 of file reg.h.

#define RF_GAIN_TX   0x07

Definition at line 1220 of file reg.h.

#define RF_IPA   0x15

Definition at line 1231 of file reg.h.

#define RF_IQADJ_G1   0x01

Definition at line 1215 of file reg.h.

#define RF_IQADJ_G2   0x02

Definition at line 1216 of file reg.h.

#define RF_MODE1   0x10

Definition at line 1225 of file reg.h.

#define RF_MODE2   0x11

Definition at line 1226 of file reg.h.

#define RF_MODE_AG   0x18

Definition at line 1233 of file reg.h.

#define RF_POW_ABILITY   0x17

Definition at line 1232 of file reg.h.

#define RF_POW_TRSW   0x05

Definition at line 1217 of file reg.h.

#define RF_RCK1   0x1E

Definition at line 1244 of file reg.h.

#define RF_RCK2   0x1F

Definition at line 1245 of file reg.h.

#define RF_RCK_OS   0x30

Definition at line 1264 of file reg.h.

#define RF_RSTB   BIT(1)

Definition at line 837 of file reg.h.

#define RF_RX_AGC_HP   0x12

Definition at line 1228 of file reg.h.

#define RF_RX_BB1   0x1D

Definition at line 1242 of file reg.h.

#define RF_RX_BB2   0x1C

Definition at line 1241 of file reg.h.

#define RF_RX_G1   0x1A

Definition at line 1238 of file reg.h.

#define RF_RX_G2   0x1B

Definition at line 1239 of file reg.h.

#define RF_SDMRSTB   BIT(2)

Definition at line 838 of file reg.h.

#define RF_SYN_G1   0x25

Definition at line 1255 of file reg.h.

#define RF_SYN_G2   0x26

Definition at line 1256 of file reg.h.

#define RF_SYN_G3   0x27

Definition at line 1257 of file reg.h.

#define RF_SYN_G4   0x28

Definition at line 1258 of file reg.h.

#define RF_SYN_G5   0x29

Definition at line 1259 of file reg.h.

#define RF_SYN_G6   0x2A

Definition at line 1260 of file reg.h.

#define RF_SYN_G7   0x2B

Definition at line 1261 of file reg.h.

#define RF_SYN_G8   0x2C

Definition at line 1262 of file reg.h.

#define RF_T_METER   0x42

Definition at line 1253 of file reg.h.

#define RF_TOP   0x19

Definition at line 1236 of file reg.h.

#define RF_TX_AGC   0x13

Definition at line 1229 of file reg.h.

#define RF_TX_BB1   0x23

Definition at line 1251 of file reg.h.

#define RF_TX_G1   0x20

Definition at line 1247 of file reg.h.

#define RF_TX_G2   0x21

Definition at line 1248 of file reg.h.

#define RF_TX_G3   0x22

Definition at line 1249 of file reg.h.

#define RF_TXM_IDAC   0x08

Definition at line 1222 of file reg.h.

#define RF_TXPA_G1   0x31

Definition at line 1266 of file reg.h.

#define RF_TXPA_G2   0x32

Definition at line 1267 of file reg.h.

#define RF_TXPA_G3   0x33

Definition at line 1268 of file reg.h.

#define RFINI_RDY   BIT(5)

Definition at line 919 of file reg.h.

#define RFPGA0_ADDALLOCKEN   0x888

Definition at line 1057 of file reg.h.

#define RFPGA0_ANALOGPARAMETER1   0x880

Definition at line 1054 of file reg.h.

#define RFPGA0_ANALOGPARAMETER2   0x884

Definition at line 1055 of file reg.h.

#define RFPGA0_ANALOGPARAMETER3   0x888

Definition at line 1056 of file reg.h.

#define RFPGA0_ANALOGPARAMETER4   0x88c

Definition at line 1058 of file reg.h.

#define RFPGA0_PSDFUNCTION   0x808

Definition at line 1024 of file reg.h.

#define RFPGA0_PSDREPORT   0x8b4

Definition at line 1065 of file reg.h.

#define RFPGA0_RFMOD   0x800

Definition at line 1021 of file reg.h.

#define RFPGA0_RFSLEEPUPPARAMETER   0x854

Definition at line 1040 of file reg.h.

#define RFPGA0_RFTIMING1   0x810

Definition at line 1028 of file reg.h.

#define RFPGA0_RFTIMING2   0x814

Definition at line 1029 of file reg.h.

#define RFPGA0_RFWAkEUPPARAMETER   0x850

Definition at line 1039 of file reg.h.

#define RFPGA0_TXGAINSTAGE   0x80c

Definition at line 1026 of file reg.h.

#define RFPGA0_TXINFO   0x804

Definition at line 1023 of file reg.h.

#define RFPGA0_XA_HSSIPARAMETER1   0x820

Definition at line 1031 of file reg.h.

#define RFPGA0_XA_HSSIPARAMETER2   0x824

Definition at line 1032 of file reg.h.

#define RFPGA0_XA_LSSIPARAMETER   0x840

Definition at line 1036 of file reg.h.

#define RFPGA0_XA_LSSIREADBACK   0x8a0

Definition at line 1060 of file reg.h.

#define RFPGA0_XA_RFINTERFACEOE   0x860

Definition at line 1045 of file reg.h.

#define RFPGA0_XAB_RFINTERFACERB   0x8e0

Definition at line 1068 of file reg.h.

#define RFPGA0_XAB_RFINTERFACESW   0x870

Definition at line 1048 of file reg.h.

#define RFPGA0_XAB_RFPARAMETER   0x878

Definition at line 1051 of file reg.h.

#define RFPGA0_XAB_SWITCHCONTROL   0x858

Definition at line 1042 of file reg.h.

#define RFPGA0_XB_HSSIPARAMETER1   0x828

Definition at line 1033 of file reg.h.

#define RFPGA0_XB_HSSIPARAMETER2   0x82c

Definition at line 1034 of file reg.h.

#define RFPGA0_XB_LSSIPARAMETER   0x844

Definition at line 1037 of file reg.h.

#define RFPGA0_XB_LSSIREADBACK   0x8a4

Definition at line 1061 of file reg.h.

#define RFPGA0_XB_RFINTERFACEOE   0x864

Definition at line 1046 of file reg.h.

#define RFPGA0_XC_LSSIREADBACK   0x8a8

Definition at line 1062 of file reg.h.

#define RFPGA0_XCD_RFINTERFACERB   0x8e4

Definition at line 1069 of file reg.h.

#define RFPGA0_XCD_RFINTERFACESW   0x874

Definition at line 1049 of file reg.h.

#define RFPGA0_XCD_RFPARAMETER   0x87c

Definition at line 1052 of file reg.h.

#define RFPGA0_XCD_SWITCHCONTROL   0x85c

Definition at line 1043 of file reg.h.

#define RFPGA0_XD_LSSIREADBACK   0x8ac

Definition at line 1063 of file reg.h.

#define RFPGA1_DEBUGSELECT   0x908

Definition at line 1075 of file reg.h.

#define RFPGA1_RFMOD   0x900

Definition at line 1072 of file reg.h.

#define RFPGA1_TXBLOCK   0x904

Definition at line 1074 of file reg.h.

#define RFPGA1_TXINFO   0x90c

Definition at line 1076 of file reg.h.

#define RING_CLK_EN   BIT(13)

Definition at line 813 of file reg.h.

#define ROFDM0_AGCPARAMETER1   0xc70

Definition at line 1136 of file reg.h.

#define ROFDM0_AGCPARAMETER2   0xc74

Definition at line 1137 of file reg.h.

#define ROFDM0_AGCRSSITABLE   0xc78

Definition at line 1138 of file reg.h.

#define ROFDM0_CCADROPTHRESHOLD   0xc48

Definition at line 1124 of file reg.h.

#define ROFDM0_CFOANDDAGC   0xc44

Definition at line 1123 of file reg.h.

#define ROFDM0_DFSREPORT   0xcf4

Definition at line 1153 of file reg.h.

#define ROFDM0_ECCATHRESHOLD   0xc4c

Definition at line 1125 of file reg.h.

#define ROFDM0_FRAMESYNC   0xcf0

Definition at line 1152 of file reg.h.

#define ROFDM0_HTSTFAGC   0xc7c

Definition at line 1139 of file reg.h.

#define ROFDM0_LSTF   0xc00

Definition at line 1102 of file reg.h.

#define ROFDM0_RXDETECTOR1   0xc30

Definition at line 1117 of file reg.h.

#define ROFDM0_RXDETECTOR2   0xc34

Definition at line 1118 of file reg.h.

#define ROFDM0_RXDETECTOR3   0xc38

Definition at line 1119 of file reg.h.

#define ROFDM0_RXDETECTOR4   0xc3c

Definition at line 1120 of file reg.h.

#define ROFDM0_RXDSP   0xc40

Definition at line 1122 of file reg.h.

#define ROFDM0_RXHPPARAMETER   0xce0

Definition at line 1150 of file reg.h.

#define ROFDM0_TRMUXPAR   0xc08

Definition at line 1105 of file reg.h.

#define ROFDM0_TRSWISOLATION   0xc0c

Definition at line 1106 of file reg.h.

#define ROFDM0_TRXPATHENABLE   0xc04

Definition at line 1104 of file reg.h.

#define ROFDM0_TXCOEFF1   0xca4

Definition at line 1154 of file reg.h.

#define ROFDM0_TXCOEFF2   0xca8

Definition at line 1155 of file reg.h.

#define ROFDM0_TXCOEFF3   0xcac

Definition at line 1156 of file reg.h.

#define ROFDM0_TXCOEFF4   0xcb0

Definition at line 1157 of file reg.h.

#define ROFDM0_TXCOEFF5   0xcb4

Definition at line 1158 of file reg.h.

#define ROFDM0_TXCOEFF6   0xcb8

Definition at line 1159 of file reg.h.

#define ROFDM0_TXPSEUDONOISEWGT   0xce4

Definition at line 1151 of file reg.h.

#define ROFDM0_XAAGCCORE1   0xc50

Definition at line 1127 of file reg.h.

#define ROFDM0_XAAGCCORE2   0xc54

Definition at line 1128 of file reg.h.

#define ROFDM0_XARXAFE   0xc10

Definition at line 1108 of file reg.h.

#define ROFDM0_XARXIQIMBALANCE   0xc14

Definition at line 1109 of file reg.h.

#define ROFDM0_XATxAFE   0xc84

Definition at line 1142 of file reg.h.

#define ROFDM0_XATxIQIMBALANCE   0xc80

Definition at line 1141 of file reg.h.

#define ROFDM0_XBAGCCORE1   0xc58

Definition at line 1129 of file reg.h.

#define ROFDM0_XBAGCCORE2   0xc5c

Definition at line 1130 of file reg.h.

#define ROFDM0_XBRXAFE   0xc18

Definition at line 1110 of file reg.h.

#define ROFDM0_XBRXIQIMBALANCE   0xc1c

Definition at line 1111 of file reg.h.

#define ROFDM0_XBTxAFE   0xc8c

Definition at line 1144 of file reg.h.

#define ROFDM0_XBTxIQIMBALANCE   0xc88

Definition at line 1143 of file reg.h.

#define ROFDM0_XCAGCCORE1   0xc60

Definition at line 1131 of file reg.h.

#define ROFDM0_XCAGCCORE2   0xc64

Definition at line 1132 of file reg.h.

#define ROFDM0_XCRXAFE   0xc20

Definition at line 1112 of file reg.h.

#define ROFDM0_XCRXIQIMBALANCE   0xc24

Definition at line 1113 of file reg.h.

#define ROFDM0_XCTxAFE   0xc94

Definition at line 1146 of file reg.h.

#define ROFDM0_XCTxIQIMBALANCE   0xc90

Definition at line 1145 of file reg.h.

#define ROFDM0_XDAGCCORE1   0xc68

Definition at line 1133 of file reg.h.

#define ROFDM0_XDAGCCORE2   0xc6c

Definition at line 1134 of file reg.h.

#define ROFDM0_XDRXAFE   0xc28

Definition at line 1114 of file reg.h.

#define ROFDM0_XDRXIQIMBALANCE   0xc2c

Definition at line 1115 of file reg.h.

#define ROFDM0_XDTxAFE   0xc9c

Definition at line 1148 of file reg.h.

#define ROFDM0_XDTxIQIMBALANCE   0xc98

Definition at line 1147 of file reg.h.

#define ROFDM1_CFO   0xd08

Definition at line 1165 of file reg.h.

#define ROFDM1_CFOTRACKING   0xd2c

Definition at line 1169 of file reg.h.

#define ROFDM1_CSI1   0xd10

Definition at line 1166 of file reg.h.

#define ROFDM1_CSI2   0xd18

Definition at line 1168 of file reg.h.

#define ROFDM1_INTFDET   0xd3c

Definition at line 1171 of file reg.h.

#define ROFDM1_LSTF   0xd00

Definition at line 1162 of file reg.h.

#define ROFDM1_PSEUDONOISESTATEAB   0xd50

Definition at line 1172 of file reg.h.

#define ROFDM1_PSEUDONOISESTATECD   0xd54

Definition at line 1173 of file reg.h.

#define ROFDM1_RXPSEUDONOISEWGT   0xd58

Definition at line 1174 of file reg.h.

#define ROFDM1_SBD   0xd14

Definition at line 1167 of file reg.h.

#define ROFDM1_TRXMESAURE1   0xd34

Definition at line 1170 of file reg.h.

#define ROFDM1_TRXPATHENABLE   0xd04

Definition at line 1163 of file reg.h.

#define ROFDM_AGCREPORT   0xdd0

Definition at line 1189 of file reg.h.

#define ROFDM_BWREPORT   0xdcc

Definition at line 1188 of file reg.h.

#define ROFDM_LONGCFOAB   0xdb4

Definition at line 1182 of file reg.h.

#define ROFDM_LONGCFOCD   0xdb8

Definition at line 1183 of file reg.h.

#define ROFDM_PHYCOUNTER1   0xda0

Definition at line 1176 of file reg.h.

#define ROFDM_PHYCOUNTER2   0xda4

Definition at line 1177 of file reg.h.

#define ROFDM_PHYCOUNTER3   0xda8

Definition at line 1178 of file reg.h.

#define ROFDM_PWMEASURE1   0xdc4

Definition at line 1186 of file reg.h.

#define ROFDM_PWMEASURE2   0xdc8

Definition at line 1187 of file reg.h.

#define ROFDM_RXEVMCSI   0xdd8

Definition at line 1191 of file reg.h.

#define ROFDM_RXSNR   0xdd4

Definition at line 1190 of file reg.h.

#define ROFDM_SHORTCFOAB   0xdac

Definition at line 1180 of file reg.h.

#define ROFDM_SHORTCFOCD   0xdb0

Definition at line 1181 of file reg.h.

#define ROFDM_SIGReport   0xddc

Definition at line 1192 of file reg.h.

#define ROFDM_TAILCFOAB   0xdbc

Definition at line 1184 of file reg.h.

#define ROFDM_TAILCFOCD   0xdc0

Definition at line 1185 of file reg.h.

#define ROP_ALD   BIT(20)

Definition at line 791 of file reg.h.

#define ROP_PWR   BIT(21)

Definition at line 792 of file reg.h.

#define ROP_SPS   BIT(22)

Definition at line 793 of file reg.h.

#define rRfChannel   0x18

Definition at line 1234 of file reg.h.

#define RRSR_11M   BIT3

Definition at line 386 of file reg.h.

#define RRSR_12M   BIT6

Definition at line 389 of file reg.h.

#define RRSR_18M   BIT7

Definition at line 390 of file reg.h.

#define RRSR_1M   BIT0

Definition at line 383 of file reg.h.

#define RRSR_24M   BIT8

Definition at line 391 of file reg.h.

#define RRSR_2M   BIT1

Definition at line 384 of file reg.h.

#define RRSR_36M   BIT9

Definition at line 392 of file reg.h.

#define RRSR_48M   BIT10

Definition at line 393 of file reg.h.

#define RRSR_54M   BIT11

Definition at line 394 of file reg.h.

#define RRSR_5_5M   BIT2

Definition at line 385 of file reg.h.

#define RRSR_6M   BIT4

Definition at line 387 of file reg.h.

#define RRSR_9M   BIT5

Definition at line 388 of file reg.h.

#define RRSR_MCS0   BIT12

Definition at line 395 of file reg.h.

#define RRSR_MCS1   BIT13

Definition at line 396 of file reg.h.

#define RRSR_MCS2   BIT14

Definition at line 397 of file reg.h.

#define RRSR_MCS3   BIT15

Definition at line 398 of file reg.h.

#define RRSR_MCS4   BIT16

Definition at line 399 of file reg.h.

#define RRSR_MCS5   BIT17

Definition at line 400 of file reg.h.

#define RRSR_MCS6   BIT18

Definition at line 401 of file reg.h.

#define RRSR_MCS7   BIT19

Definition at line 402 of file reg.h.

#define RRSR_RSC_BW_40M   0x600000

Definition at line 379 of file reg.h.

#define RRSR_RSC_LOWSUBCHNL   0x200000

Definition at line 381 of file reg.h.

#define RRSR_RSC_OFFSET   21

Definition at line 377 of file reg.h.

#define RRSR_RSC_UPSUBCHNL   0x400000

Definition at line 380 of file reg.h.

#define RRSR_SHORT   0x800000

Definition at line 382 of file reg.h.

#define RRSR_SHORT_OFFSET   23

Definition at line 378 of file reg.h.

#define RTL8190_EEPROM_ID   0x8129 /* 0-1 */

Definition at line 618 of file reg.h.

#define RTL8192_EEPROM_ID   0x8129

Definition at line 614 of file reg.h.

#define RTXAGC_A_CCK1_MCS32   0xe08

Definition at line 1197 of file reg.h.

#define RTXAGC_A_MCS03_MCS00   0xe10

Definition at line 1198 of file reg.h.

#define RTXAGC_A_MCS07_MCS04   0xe14

Definition at line 1199 of file reg.h.

#define RTXAGC_A_MCS11_MCS08   0xe18

Definition at line 1200 of file reg.h.

#define RTXAGC_A_MCS15_MCS12   0xe1c

Definition at line 1201 of file reg.h.

#define RTXAGC_A_RATE18_06   0xe00

Definition at line 1195 of file reg.h.

#define RTXAGC_A_RATE54_24   0xe04

Definition at line 1196 of file reg.h.

#define RTXAGC_B_CCK11_A_CCK2_11   0x86c

Definition at line 1210 of file reg.h.

#define RTXAGC_B_CCK1_55_MCS32   0x838

Definition at line 1205 of file reg.h.

#define RTXAGC_B_MCS03_MCS00   0x83c

Definition at line 1206 of file reg.h.

#define RTXAGC_B_MCS07_MCS04   0x848

Definition at line 1207 of file reg.h.

#define RTXAGC_B_MCS11_MCS08   0x84c

Definition at line 1208 of file reg.h.

#define RTXAGC_B_MCS15_MCS12   0x868

Definition at line 1209 of file reg.h.

#define RTXAGC_B_RATE18_06   0x830

Definition at line 1203 of file reg.h.

#define RTXAGC_B_RATE54_24   0x834

Definition at line 1204 of file reg.h.

#define SCR_NOSKMC   BIT(5)

Definition at line 996 of file reg.h.

#define SCR_RXBCUSEDK   BIT(7)

Definition at line 998 of file reg.h.

#define SCR_RXENCENABLE   BIT(3)

Definition at line 994 of file reg.h.

#define SCR_RXUSEDK   BIT(1)

Definition at line 992 of file reg.h.

#define SCR_SKBYA2   BIT(4)

Definition at line 995 of file reg.h.

#define SCR_TXBCUSEDK   BIT(6)

Definition at line 997 of file reg.h.

#define SCR_TXENCENABLE   BIT(2)

Definition at line 993 of file reg.h.

#define SCR_TXUSEDK   BIT(0)

Definition at line 991 of file reg.h.

#define SEC_CLK_EN   BIT(10)

Definition at line 810 of file reg.h.

#define SIC_IDLE   BIT(8)

Definition at line 932 of file reg.h.

#define SOP_A8M   BIT(30)

Definition at line 799 of file reg.h.

#define SOP_ABG   BIT(27)

Definition at line 796 of file reg.h.

#define SOP_AMB   BIT(28)

Definition at line 797 of file reg.h.

#define SOP_FUSE   BIT(26)

Definition at line 795 of file reg.h.

#define SOP_MRST   BIT(25)

Definition at line 794 of file reg.h.

#define SOP_RCK   BIT(29)

Definition at line 798 of file reg.h.

#define SUS_HOST   BIT(17)

Definition at line 790 of file reg.h.

#define SW18_FPWM   BIT(3)

Definition at line 737 of file reg.h.

#define SYS_CLK_EN   BIT(12)

Definition at line 812 of file reg.h.

#define TOTAL_CAM_ENTRY   32

Definition at line 510 of file reg.h.

#define TRANSCEIVERA_HSPI_READBACK   0x8b8

Definition at line 1066 of file reg.h.

#define TRANSCEIVERB_HSPI_READBACK   0x8bc

Definition at line 1067 of file reg.h.

#define TRP_B15V_EN   BIT(7)

Definition at line 931 of file reg.h.

#define TRP_BT_EN   BIT(24)

Definition at line 938 of file reg.h.

#define TRP_VAUX_EN   BIT(23)

Definition at line 937 of file reg.h.

#define TSFR   REG_TSFTR

Definition at line 355 of file reg.h.

#define TSFRST   BIT(0)

Definition at line 981 of file reg.h.

#define TYPE_ID   BIT(27)

Definition at line 941 of file reg.h.

#define UCLK_VLD   BIT(2)

Definition at line 927 of file reg.h.

#define V15_VLD   BIT(5)

Definition at line 930 of file reg.h.

#define WINTINI_RDY   BIT(6)

Definition at line 920 of file reg.h.

#define WLOCK_00   BIT(1)

Definition at line 827 of file reg.h.

#define WLOCK_04   BIT(2)

Definition at line 828 of file reg.h.

#define WLOCK_08   BIT(3)

Definition at line 829 of file reg.h.

#define WLOCK_40   BIT(4)

Definition at line 830 of file reg.h.

#define WLOCK_ALL   BIT(0)

Definition at line 826 of file reg.h.

#define WOW_MAGIC   BIT2 /* Magic packet */

Definition at line 520 of file reg.h.

#define WOW_PMEN   BIT0 /* Power management Enable. */

Definition at line 518 of file reg.h.

#define WOW_UWF   BIT3 /* Unicast Wakeup frame. */

Definition at line 521 of file reg.h.

#define WOW_WOMEN   BIT1 /* WoW function on or off. */

Definition at line 519 of file reg.h.

#define XCLK_VLD   BIT(0)

Definition at line 925 of file reg.h.

#define XOP_BTCK   BIT(31)

Definition at line 800 of file reg.h.

#define XTAL_BSEL   BIT(1)

Definition at line 861 of file reg.h.

#define XTAL_BT_GATE   BIT(20)

Definition at line 872 of file reg.h.

#define XTAL_EN   BIT(0)

Definition at line 860 of file reg.h.

#define XTAL_GATE_AFE   BIT(11)

Definition at line 866 of file reg.h.

#define XTAL_GATE_DIG   BIT(17)

Definition at line 870 of file reg.h.

#define XTAL_GATE_USB   BIT(8)

Definition at line 864 of file reg.h.

#define XTAL_RF_GATE   BIT(14)

Definition at line 868 of file reg.h.

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