#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/rtnetlink.h>
#include <linux/if_vlan.h>

Data Structures
struct	mbox_params

struct	flash_params_8012

struct	flash_params_8000

union	flash_params

struct	rx_doorbell_context

struct	tx_doorbell_context

struct	tx_buf_desc

struct	ob_mac_iocb_req

struct	ob_mac_iocb_rsp

struct	ob_mac_tso_iocb_req

struct	ob_mac_tso_iocb_rsp

struct	ib_mac_iocb_rsp

struct	ib_ae_iocb_rsp

struct	ql_net_rsp_iocb

struct	net_req_iocb

struct	wqicb

struct	cqicb

struct	ricb

struct	oal

struct	map_list

struct	tx_ring_desc

struct	page_chunk

struct	bq_desc

struct	tx_ring

struct	rx_ring

struct	hash_id

struct	nic_stats

struct	mpi_coredump_global_header

struct	mpi_coredump_segment_header

struct	ql_nic_misc

struct	ql_reg_dump

struct	ql_mpi_coredump

struct	intr_context

struct	nic_operations

struct	ql_adapter

Macros
#define	DRV_NAME "qlge"

#define	DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "

#define	DRV_VERSION "v1.00.00.31"

#define	WQ_ADDR_ALIGN 0x3 /* 4 byte alignment */

#define	QLGE_VENDOR_ID 0x1077

#define	QLGE_DEVICE_ID_8012 0x8012

#define	QLGE_DEVICE_ID_8000 0x8000

#define	QLGE_MEZZ_SSYS_ID_068 0x0068

#define	QLGE_MEZZ_SSYS_ID_180 0x0180

#define	MAX_CPUS 8

#define	MAX_TX_RINGS MAX_CPUS

#define	MAX_RX_RINGS ((MAX_CPUS * 2) + 1)

#define	NUM_TX_RING_ENTRIES 256

#define	NUM_RX_RING_ENTRIES 256

#define	NUM_SMALL_BUFFERS 512

#define	NUM_LARGE_BUFFERS 512

#define	DB_PAGE_SIZE 4096

#define	MAX_DB_PAGES_PER_BQ(x)

#define	RX_RING_SHADOW_SPACE

#define	LARGE_BUFFER_MAX_SIZE 8192

#define	LARGE_BUFFER_MIN_SIZE 2048

#define	MAX_CQ 128

#define	DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */

#define	MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */

#define	DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2)

#define	UDELAY_COUNT 3

#define	UDELAY_DELAY 100

#define	TX_DESC_PER_IOCB 8

#define	TX_DESC_PER_OAL 0

#define	LSW(x) ((u16)(x))

#define	MSW(x) ((u16)((u32)(x) >> 16))

#define	LSD(x) ((u32)((u64)(x)))

#define	MSD(x) ((u32)((((u64)(x)) >> 32)))

#define	SMALL_BUFFER_SIZE 512

#define	SMALL_BUF_MAP_SIZE (SMALL_BUFFER_SIZE / 2)

#define	SPLT_SETTING FSC_SH

#define	SPLT_LEN

#define	QLGE_SB_PAD 32

#define	FUNC0_FLASH_OFFSET 0x140200

#define	FUNC1_FLASH_OFFSET 0x140600

#define	TX_DESC_LEN_MASK 0x000fffff

#define	TX_DESC_C 0x40000000

#define	TX_DESC_E 0x80000000

#define	OPCODE_OB_MAC_IOCB 0x01

#define	OPCODE_OB_MAC_TSO_IOCB 0x02

#define	OPCODE_IB_MAC_IOCB 0x20

#define	OPCODE_IB_MPI_IOCB 0x21

#define	OPCODE_IB_AE_IOCB 0x3f

#define	OB_MAC_IOCB_REQ_OI 0x01

#define	OB_MAC_IOCB_REQ_I 0x02

#define	OB_MAC_IOCB_REQ_D 0x08

#define	OB_MAC_IOCB_REQ_F 0x10

#define	OB_MAC_IOCB_DFP 0x02

#define	OB_MAC_IOCB_V 0x04

#define	OB_MAC_IOCB_LEN_MASK 0x3ffff

#define	OB_MAC_IOCB_RSP_OI 0x01 /* */

#define	OB_MAC_IOCB_RSP_I 0x02 /* */

#define	OB_MAC_IOCB_RSP_E 0x08 /* */

#define	OB_MAC_IOCB_RSP_S 0x10 /* too Short */

#define	OB_MAC_IOCB_RSP_L 0x20 /* too Large */

#define	OB_MAC_IOCB_RSP_P 0x40 /* Padded */

#define	OB_MAC_IOCB_RSP_B 0x80 /* */

#define	OB_MAC_TSO_IOCB_OI 0x01

#define	OB_MAC_TSO_IOCB_I 0x02

#define	OB_MAC_TSO_IOCB_D 0x08

#define	OB_MAC_TSO_IOCB_IP4 0x40

#define	OB_MAC_TSO_IOCB_IP6 0x80

#define	OB_MAC_TSO_IOCB_LSO 0x20

#define	OB_MAC_TSO_IOCB_UC 0x40

#define	OB_MAC_TSO_IOCB_TC 0x80

#define	OB_MAC_TSO_IOCB_IC 0x01

#define	OB_MAC_TSO_IOCB_DFP 0x02

#define	OB_MAC_TSO_IOCB_V 0x04

#define	OB_MAC_TRANSPORT_HDR_SHIFT 6

#define	OB_MAC_TSO_IOCB_RSP_OI 0x01

#define	OB_MAC_TSO_IOCB_RSP_I 0x02

#define	OB_MAC_TSO_IOCB_RSP_E 0x08

#define	OB_MAC_TSO_IOCB_RSP_S 0x10

#define	OB_MAC_TSO_IOCB_RSP_L 0x20

#define	OB_MAC_TSO_IOCB_RSP_P 0x40

#define	OB_MAC_TSO_IOCB_RSP_B 0x8000

#define	IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */

#define	IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */

#define	IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */

#define	IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */

#define	IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */

#define	IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */

#define	IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */

#define	IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */

#define	IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */

#define	IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */

#define	IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */

#define	IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */

#define	IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */

#define	IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */

#define	IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */

#define	IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04

#define	IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08

#define	IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10

#define	IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14

#define	IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18

#define	IB_MAC_IOCB_RSP_ERR_CRC 0x1c

#define	IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */

#define	IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */

#define	IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */

#define	IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */

#define	IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */

#define	IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */

#define	IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */

#define	IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */

#define	IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */

#define	IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */

#define	IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */

#define	IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */

#define	IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */

#define	IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */

#define	IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */

#define	IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */

#define	IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff

#define	IB_MAC_IOCB_RSP_HV 0x20

#define	IB_MAC_IOCB_RSP_HS 0x40

#define	IB_MAC_IOCB_RSP_HL 0x80

#define	IB_AE_IOCB_RSP_OI 0x01

#define	IB_AE_IOCB_RSP_I 0x02

#define	LINK_UP_EVENT 0x00

#define	LINK_DOWN_EVENT 0x01

#define	CAM_LOOKUP_ERR_EVENT 0x06

#define	SOFT_ECC_ERROR_EVENT 0x07

#define	MGMT_ERR_EVENT 0x08

#define	TEN_GIG_MAC_EVENT 0x09

#define	GPI0_H2L_EVENT 0x10

#define	GPI0_L2H_EVENT 0x20

#define	GPI1_H2L_EVENT 0x11

#define	GPI1_L2H_EVENT 0x21

#define	PCI_ERR_ANON_BUF_RD 0x40

#define	Q_LEN_V (1 << 4)

#define	Q_LEN_CPP_CONT 0x0000

#define	Q_LEN_CPP_16 0x0001

#define	Q_LEN_CPP_32 0x0002

#define	Q_LEN_CPP_64 0x0003

#define	Q_LEN_CPP_512 0x0006

#define	Q_PRI_SHIFT 1

#define	Q_FLAGS_LC 0x1000

#define	Q_FLAGS_LB 0x2000

#define	Q_FLAGS_LI 0x4000

#define	Q_FLAGS_LO 0x8000

#define	Q_CQ_ID_RSS_RV 0x8000

#define	FLAGS_LV 0x08

#define	FLAGS_LS 0x10

#define	FLAGS_LL 0x20

#define	FLAGS_LI 0x40

#define	FLAGS_LC 0x80

#define	LEN_V (1 << 4)

#define	LEN_CPP_CONT 0x0000

#define	LEN_CPP_32 0x0001

#define	LEN_CPP_64 0x0002

#define	LEN_CPP_128 0x0003

#define	RSS_L4K 0x80

#define	RSS_L6K 0x01

#define	RSS_LI 0x02

#define	RSS_LB 0x04

#define	RSS_LM 0x08

#define	RSS_RI4 0x10

#define	RSS_RT4 0x20

#define	RSS_RI6 0x40

#define	RSS_RT6 0x80

#define	QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count))

#define	MPI_COREDUMP_COOKIE 0x5555aaaa

#define	NIC_REGS_DUMP_WORD_COUNT 64

#define	XGMAC_DUMP_WORD_COUNT (XGMAC_REGISTER_END / 4)

#define	XG_SERDES_XAUI_AN_COUNT 14

#define	XG_SERDES_XAUI_HSS_PCS_COUNT 33

#define	XG_SERDES_XFI_AN_COUNT 14

#define	XG_SERDES_XFI_TRAIN_COUNT 12

#define	XG_SERDES_XFI_HSS_PCS_COUNT 15

#define	XG_SERDES_XFI_HSS_TX_COUNT 32

#define	XG_SERDES_XFI_HSS_RX_COUNT 32

#define	XG_SERDES_XFI_HSS_PLL_COUNT 32

#define	ETS_REGS_DUMP_WORD_COUNT 10

#define	PRB_MX_ADDR_PRB_WORD_COUNT (1 + (PRB_MX_ADDR_MAX_MUX * 2))

#define	PRB_MX_DUMP_TOT_COUNT

#define	RT_IDX_DUMP_ENTRIES 48

#define	RT_IDX_DUMP_WORDS_PER_ENTRY 4

#define	RT_IDX_DUMP_TOT_WORDS

#define	MAC_ADDR_DUMP_ENTRIES

#define	MAC_ADDR_DUMP_WORDS_PER_ENTRY 2

#define	MAC_ADDR_DUMP_TOT_WORDS

#define	MAX_SEMAPHORE_FUNCTIONS 4

#define	RISC_124 0x0003007c

#define	RISC_127 0x0003007f

#define	SHADOW_OFFSET 0xb0000000

#define	SHADOW_REG_SHIFT 20

#define	QL_DUMP_REGS(qdev)

#define	QL_DUMP_ROUTE(qdev)

#define	QL_DUMP_XGMAC_CONTROL_REGS(qdev)

#define	QL_DUMP_STAT(qdev)

#define	QL_DUMP_QDEV(qdev)

#define	QL_DUMP_RICB(ricb)

#define	QL_DUMP_WQICB(wqicb)

#define	QL_DUMP_TX_RING(tx_ring)

#define	QL_DUMP_CQICB(cqicb)

#define	QL_DUMP_RX_RING(rx_ring)

#define	QL_DUMP_HW_CB(qdev, size, bit, q_id)

#define	QL_DUMP_OB_MAC_IOCB(ob_mac_iocb)

#define	QL_DUMP_OB_MAC_RSP(ob_mac_rsp)

#define	QL_DUMP_IB_MAC_RSP(ib_mac_rsp)

#define	QL_DUMP_ALL(qdev)

Enumerations
enum	{ MPI_TEST_FUNC_PORT_CFG = 0x1002, MPI_TEST_FUNC_PRB_CTL = 0x100e, MPI_TEST_FUNC_PRB_EN = 0x18a20000, MPI_TEST_FUNC_RST_STS = 0x100a, MPI_TEST_FUNC_RST_FRC = 0x00000003, MPI_TEST_NIC_FUNC_MASK = 0x00000007, MPI_TEST_NIC1_FUNCTION_ENABLE = (1 << 0), MPI_TEST_NIC1_FUNCTION_MASK = 0x0000000e, MPI_TEST_NIC1_FUNC_SHIFT = 1, MPI_TEST_NIC2_FUNCTION_ENABLE = (1 << 4), MPI_TEST_NIC2_FUNCTION_MASK = 0x000000e0, MPI_TEST_NIC2_FUNC_SHIFT = 5, MPI_TEST_FC1_FUNCTION_ENABLE = (1 << 8), MPI_TEST_FC1_FUNCTION_MASK = 0x00000e00, MPI_TEST_FC1_FUNCTION_SHIFT = 9, MPI_TEST_FC2_FUNCTION_ENABLE = (1 << 12), MPI_TEST_FC2_FUNCTION_MASK = 0x0000e000, MPI_TEST_FC2_FUNCTION_SHIFT = 13, MPI_NIC_READ = 0x00000000, MPI_NIC_REG_BLOCK = 0x00020000, MPI_NIC_FUNCTION_SHIFT = 6 }

enum	{ MAILBOX_COUNT = 16, MAILBOX_TIMEOUT = 5, PROC_ADDR_RDY = (1 << 31), PROC_ADDR_R = (1 << 30), PROC_ADDR_ERR = (1 << 29), PROC_ADDR_DA = (1 << 28), PROC_ADDR_FUNC0_MBI = 0x00001180, PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT), PROC_ADDR_FUNC0_CTL = 0x000011a1, PROC_ADDR_FUNC2_MBI = 0x00001280, PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT), PROC_ADDR_FUNC2_CTL = 0x000012a1, PROC_ADDR_MPI_RISC = 0x00000000, PROC_ADDR_MDE = 0x00010000, PROC_ADDR_REGBLOCK = 0x00020000, PROC_ADDR_RISC_REG = 0x00030000 }

enum	{ SYS_EFE = (1 << 0), SYS_FAE = (1 << 1), SYS_MDC = (1 << 2), SYS_DST = (1 << 3), SYS_DWC = (1 << 4), SYS_EVW = (1 << 5), SYS_OMP_DLY_MASK = 0x3f000000, SYS_ODI = (1 << 14) }

enum	{ RST_FO_TFO = (1 << 0), RST_FO_RR_MASK = 0x00060000, RST_FO_RR_CQ_CAM = 0x00000000, RST_FO_RR_DROP = 0x00000002, RST_FO_RR_DQ = 0x00000004, RST_FO_RR_RCV_FUNC_CQ = 0x00000006, RST_FO_FRB = (1 << 12), RST_FO_MOP = (1 << 13), RST_FO_REG = (1 << 14), RST_FO_FR = (1 << 15) }

enum	{ FSC_DBRST_MASK = 0x00070000, FSC_DBRST_256 = 0x00000000, FSC_DBRST_512 = 0x00000001, FSC_DBRST_768 = 0x00000002, FSC_DBRST_1024 = 0x00000003, FSC_DBL_MASK = 0x00180000, FSC_DBL_DBRST = 0x00000000, FSC_DBL_MAX_PLD = 0x00000008, FSC_DBL_MAX_BRST = 0x00000010, FSC_DBL_128_BYTES = 0x00000018, FSC_EC = (1 << 5), FSC_EPC_MASK = 0x00c00000, FSC_EPC_INBOUND = (1 << 6), FSC_EPC_OUTBOUND = (1 << 7), FSC_VM_PAGESIZE_MASK = 0x07000000, FSC_VM_PAGE_2K = 0x00000100, FSC_VM_PAGE_4K = 0x00000200, FSC_VM_PAGE_8K = 0x00000300, FSC_VM_PAGE_64K = 0x00000600, FSC_SH = (1 << 11), FSC_DSB = (1 << 12), FSC_STE = (1 << 13), FSC_FE = (1 << 15) }

enum	{ CSR_ERR_STS_MASK = 0x0000003f, CSR_RR = (1 << 8), CSR_HRI = (1 << 9), CSR_RP = (1 << 10), CSR_CMD_PARM_SHIFT = 22, CSR_CMD_NOP = 0x00000000, CSR_CMD_SET_RST = 0x10000000, CSR_CMD_CLR_RST = 0x20000000, CSR_CMD_SET_PAUSE = 0x30000000, CSR_CMD_CLR_PAUSE = 0x40000000, CSR_CMD_SET_H2R_INT = 0x50000000, CSR_CMD_CLR_H2R_INT = 0x60000000, CSR_CMD_PAR_EN = 0x70000000, CSR_CMD_SET_BAD_PAR = 0x80000000, CSR_CMD_CLR_BAD_PAR = 0x90000000, CSR_CMD_CLR_R2PCI_INT = 0xa0000000 }

enum	{ CFG_LRQ = (1 << 0), CFG_DRQ = (1 << 1), CFG_LR = (1 << 2), CFG_DR = (1 << 3), CFG_LE = (1 << 5), CFG_LCQ = (1 << 6), CFG_DCQ = (1 << 7), CFG_Q_SHIFT = 8, CFG_Q_MASK = 0x7f000000 }

enum	{ STS_FE = (1 << 0), STS_PI = (1 << 1), STS_PL0 = (1 << 2), STS_PL1 = (1 << 3), STS_PI0 = (1 << 4), STS_PI1 = (1 << 5), STS_FUNC_ID_MASK = 0x000000c0, STS_FUNC_ID_SHIFT = 6, STS_F0E = (1 << 8), STS_F1E = (1 << 9), STS_F2E = (1 << 10), STS_F3E = (1 << 11), STS_NFE = (1 << 12) }

enum	{ INTR_EN_INTR_MASK = 0x007f0000, INTR_EN_TYPE_MASK = 0x03000000, INTR_EN_TYPE_ENABLE = 0x00000100, INTR_EN_TYPE_DISABLE = 0x00000200, INTR_EN_TYPE_READ = 0x00000300, INTR_EN_IHD = (1 << 13), INTR_EN_IHD_MASK = (INTR_EN_IHD << 16), INTR_EN_EI = (1 << 14), INTR_EN_EN = (1 << 15) }

enum	{ INTR_MASK_PI = (1 << 0), INTR_MASK_HL0 = (1 << 1), INTR_MASK_LH0 = (1 << 2), INTR_MASK_HL1 = (1 << 3), INTR_MASK_LH1 = (1 << 4), INTR_MASK_SE = (1 << 5), INTR_MASK_LSC = (1 << 6), INTR_MASK_MC = (1 << 7), INTR_MASK_LINK_IRQS = INTR_MASK_LSC \| INTR_MASK_SE \| INTR_MASK_MC }

enum	{ REV_ID_MASK = 0x0000000f, REV_ID_NICROLL_SHIFT = 0, REV_ID_NICREV_SHIFT = 4, REV_ID_XGROLL_SHIFT = 8, REV_ID_XGREV_SHIFT = 12, REV_ID_CHIPREV_SHIFT = 28 }

enum	{ FRC_ECC_ERR_VW = (1 << 12), FRC_ECC_ERR_VB = (1 << 13), FRC_ECC_ERR_NI = (1 << 14), FRC_ECC_ERR_NO = (1 << 15), FRC_ECC_PFE_SHIFT = 16, FRC_ECC_ERR_DO = (1 << 18), FRC_ECC_P14 = (1 << 19) }

enum	{ ERR_STS_NOF = (1 << 0), ERR_STS_NIF = (1 << 1), ERR_STS_DRP = (1 << 2), ERR_STS_XGP = (1 << 3), ERR_STS_FOU = (1 << 4), ERR_STS_FOC = (1 << 5), ERR_STS_FOF = (1 << 6), ERR_STS_FIU = (1 << 7), ERR_STS_FIC = (1 << 8), ERR_STS_FIF = (1 << 9), ERR_STS_MOF = (1 << 10), ERR_STS_TA = (1 << 11), ERR_STS_MA = (1 << 12), ERR_STS_MPE = (1 << 13), ERR_STS_SCE = (1 << 14), ERR_STS_STE = (1 << 15), ERR_STS_FOW = (1 << 16), ERR_STS_UE = (1 << 17), ERR_STS_MCH = (1 << 26), ERR_STS_LOC_SHIFT = 27 }

enum	{ RAM_DBG_ADDR_FW = (1 << 30), RAM_DBG_ADDR_FR = (1 << 31) }

enum	{ SEM_CLEAR = 0, SEM_SET = 1, SEM_FORCE = 3, SEM_XGMAC0_SHIFT = 0, SEM_XGMAC1_SHIFT = 2, SEM_ICB_SHIFT = 4, SEM_MAC_ADDR_SHIFT = 6, SEM_FLASH_SHIFT = 8, SEM_PROBE_SHIFT = 10, SEM_RT_IDX_SHIFT = 12, SEM_PROC_REG_SHIFT = 14, SEM_XGMAC0_MASK = 0x00030000, SEM_XGMAC1_MASK = 0x000c0000, SEM_ICB_MASK = 0x00300000, SEM_MAC_ADDR_MASK = 0x00c00000, SEM_FLASH_MASK = 0x03000000, SEM_PROBE_MASK = 0x0c000000, SEM_RT_IDX_MASK = 0x30000000, SEM_PROC_REG_MASK = 0xc0000000 }

enum	{ XGMAC_ADDR_RDY = (1 << 31), XGMAC_ADDR_R = (1 << 30), XGMAC_ADDR_XME = (1 << 29), PAUSE_SRC_LO = 0x00000100, PAUSE_SRC_HI = 0x00000104, GLOBAL_CFG = 0x00000108, GLOBAL_CFG_RESET = (1 << 0), GLOBAL_CFG_JUMBO = (1 << 6), GLOBAL_CFG_TX_STAT_EN = (1 << 10), GLOBAL_CFG_RX_STAT_EN = (1 << 11), TX_CFG = 0x0000010c, TX_CFG_RESET = (1 << 0), TX_CFG_EN = (1 << 1), TX_CFG_PREAM = (1 << 2), RX_CFG = 0x00000110, RX_CFG_RESET = (1 << 0), RX_CFG_EN = (1 << 1), RX_CFG_PREAM = (1 << 2), FLOW_CTL = 0x0000011c, PAUSE_OPCODE = 0x00000120, PAUSE_TIMER = 0x00000124, PAUSE_FRM_DEST_LO = 0x00000128, PAUSE_FRM_DEST_HI = 0x0000012c, MAC_TX_PARAMS = 0x00000134, MAC_TX_PARAMS_JUMBO = (1 << 31), MAC_TX_PARAMS_SIZE_SHIFT = 16, MAC_RX_PARAMS = 0x00000138, MAC_SYS_INT = 0x00000144, MAC_SYS_INT_MASK = 0x00000148, MAC_MGMT_INT = 0x0000014c, MAC_MGMT_IN_MASK = 0x00000150, EXT_ARB_MODE = 0x000001fc, TX_PKTS = 0x00000200, TX_BYTES = 0x00000208, TX_MCAST_PKTS = 0x00000210, TX_BCAST_PKTS = 0x00000218, TX_UCAST_PKTS = 0x00000220, TX_CTL_PKTS = 0x00000228, TX_PAUSE_PKTS = 0x00000230, TX_64_PKT = 0x00000238, TX_65_TO_127_PKT = 0x00000240, TX_128_TO_255_PKT = 0x00000248, TX_256_511_PKT = 0x00000250, TX_512_TO_1023_PKT = 0x00000258, TX_1024_TO_1518_PKT = 0x00000260, TX_1519_TO_MAX_PKT = 0x00000268, TX_UNDERSIZE_PKT = 0x00000270, TX_OVERSIZE_PKT = 0x00000278, RX_HALF_FULL_DET = 0x000002a0, TX_HALF_FULL_DET = 0x000002a4, RX_OVERFLOW_DET = 0x000002a8, TX_OVERFLOW_DET = 0x000002ac, RX_HALF_FULL_MASK = 0x000002b0, TX_HALF_FULL_MASK = 0x000002b4, RX_OVERFLOW_MASK = 0x000002b8, TX_OVERFLOW_MASK = 0x000002bc, STAT_CNT_CTL = 0x000002c0, STAT_CNT_CTL_CLEAR_TX = (1 << 0), STAT_CNT_CTL_CLEAR_RX = (1 << 1), AUX_RX_HALF_FULL_DET = 0x000002d0, AUX_TX_HALF_FULL_DET = 0x000002d4, AUX_RX_OVERFLOW_DET = 0x000002d8, AUX_TX_OVERFLOW_DET = 0x000002dc, AUX_RX_HALF_FULL_MASK = 0x000002f0, AUX_TX_HALF_FULL_MASK = 0x000002f4, AUX_RX_OVERFLOW_MASK = 0x000002f8, AUX_TX_OVERFLOW_MASK = 0x000002fc, RX_BYTES = 0x00000300, RX_BYTES_OK = 0x00000308, RX_PKTS = 0x00000310, RX_PKTS_OK = 0x00000318, RX_BCAST_PKTS = 0x00000320, RX_MCAST_PKTS = 0x00000328, RX_UCAST_PKTS = 0x00000330, RX_UNDERSIZE_PKTS = 0x00000338, RX_OVERSIZE_PKTS = 0x00000340, RX_JABBER_PKTS = 0x00000348, RX_UNDERSIZE_FCERR_PKTS = 0x00000350, RX_DROP_EVENTS = 0x00000358, RX_FCERR_PKTS = 0x00000360, RX_ALIGN_ERR = 0x00000368, RX_SYMBOL_ERR = 0x00000370, RX_MAC_ERR = 0x00000378, RX_CTL_PKTS = 0x00000380, RX_PAUSE_PKTS = 0x00000388, RX_64_PKTS = 0x00000390, RX_65_TO_127_PKTS = 0x00000398, RX_128_255_PKTS = 0x000003a0, RX_256_511_PKTS = 0x000003a8, RX_512_TO_1023_PKTS = 0x000003b0, RX_1024_TO_1518_PKTS = 0x000003b8, RX_1519_TO_MAX_PKTS = 0x000003c0, RX_LEN_ERR_PKTS = 0x000003c8, MDIO_TX_DATA = 0x00000400, MDIO_RX_DATA = 0x00000410, MDIO_CMD = 0x00000420, MDIO_PHY_ADDR = 0x00000430, MDIO_PORT = 0x00000440, MDIO_STATUS = 0x00000450, XGMAC_REGISTER_END = 0x00000740 }

enum	{ ETS_QUEUE_SHIFT = 29, ETS_REF = (1 << 26), ETS_RS = (1 << 27), ETS_P = (1 << 28), ETS_FC_COS_SHIFT = 23 }

enum	{ FLASH_ADDR_RDY = (1 << 31), FLASH_ADDR_R = (1 << 30), FLASH_ADDR_ERR = (1 << 29) }

enum	{ CQ_STOP_QUEUE_MASK = (0x007f0000), CQ_STOP_TYPE_MASK = (0x03000000), CQ_STOP_TYPE_START = 0x00000100, CQ_STOP_TYPE_STOP = 0x00000200, CQ_STOP_TYPE_READ = 0x00000300, CQ_STOP_EN = (1 << 15) }

enum	{ MAC_ADDR_IDX_SHIFT = 4, MAC_ADDR_TYPE_SHIFT = 16, MAC_ADDR_TYPE_COUNT = 10, MAC_ADDR_TYPE_MASK = 0x000f0000, MAC_ADDR_TYPE_CAM_MAC = 0x00000000, MAC_ADDR_TYPE_MULTI_MAC = 0x00010000, MAC_ADDR_TYPE_VLAN = 0x00020000, MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000, MAC_ADDR_TYPE_FC_MAC = 0x00040000, MAC_ADDR_TYPE_MGMT_MAC = 0x00050000, MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000, MAC_ADDR_TYPE_MGMT_V4 = 0x00070000, MAC_ADDR_TYPE_MGMT_V6 = 0x00080000, MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000, MAC_ADDR_ADR = (1 << 25), MAC_ADDR_RS = (1 << 26), MAC_ADDR_E = (1 << 27), MAC_ADDR_MR = (1 << 30), MAC_ADDR_MW = (1 << 31), MAX_MULTICAST_ENTRIES = 32, MAC_ADDR_MAX_CAM_ENTRIES = 512, MAC_ADDR_MAX_CAM_WCOUNT = 3, MAC_ADDR_MAX_MULTICAST_ENTRIES = 32, MAC_ADDR_MAX_MULTICAST_WCOUNT = 2, MAC_ADDR_MAX_VLAN_ENTRIES = 4096, MAC_ADDR_MAX_VLAN_WCOUNT = 1, MAC_ADDR_MAX_MCAST_FLTR_ENTRIES = 4096, MAC_ADDR_MAX_MCAST_FLTR_WCOUNT = 1, MAC_ADDR_MAX_FC_MAC_ENTRIES = 4, MAC_ADDR_MAX_FC_MAC_WCOUNT = 2, MAC_ADDR_MAX_MGMT_MAC_ENTRIES = 8, MAC_ADDR_MAX_MGMT_MAC_WCOUNT = 2, MAC_ADDR_MAX_MGMT_VLAN_ENTRIES = 16, MAC_ADDR_MAX_MGMT_VLAN_WCOUNT = 1, MAC_ADDR_MAX_MGMT_V4_ENTRIES = 4, MAC_ADDR_MAX_MGMT_V4_WCOUNT = 1, MAC_ADDR_MAX_MGMT_V6_ENTRIES = 4, MAC_ADDR_MAX_MGMT_V6_WCOUNT = 4, MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES = 4, MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT = 1 }

enum	{ SPLT_HDR_EP = (1 << 31) }

enum	{ FC_RCV_CFG_ECT = (1 << 15), FC_RCV_CFG_DFH = (1 << 20), FC_RCV_CFG_DVF = (1 << 21), FC_RCV_CFG_RCE = (1 << 27), FC_RCV_CFG_RFE = (1 << 28), FC_RCV_CFG_TEE = (1 << 29), FC_RCV_CFG_TCE = (1 << 30), FC_RCV_CFG_TFE = (1 << 31) }

enum	{ NIC_RCV_CFG_PPE = (1 << 0), NIC_RCV_CFG_VLAN_MASK = 0x00060000, NIC_RCV_CFG_VLAN_ALL = 0x00000000, NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002, NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004, NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006, NIC_RCV_CFG_RV = (1 << 3), NIC_RCV_CFG_DFQ_MASK = (0x7f000000), NIC_RCV_CFG_DFQ_SHIFT = 8, NIC_RCV_CFG_DFQ = 0 }

enum	{ MGMT_RCV_CFG_ARP = (1 << 0), MGMT_RCV_CFG_DHC = (1 << 1), MGMT_RCV_CFG_DHS = (1 << 2), MGMT_RCV_CFG_NP = (1 << 3), MGMT_RCV_CFG_I6N = (1 << 4), MGMT_RCV_CFG_I6R = (1 << 5), MGMT_RCV_CFG_DH6 = (1 << 6), MGMT_RCV_CFG_UD1 = (1 << 7), MGMT_RCV_CFG_UD0 = (1 << 8), MGMT_RCV_CFG_BCT = (1 << 9), MGMT_RCV_CFG_MCT = (1 << 10), MGMT_RCV_CFG_DM = (1 << 11), MGMT_RCV_CFG_RM = (1 << 12), MGMT_RCV_CFG_STL = (1 << 13), MGMT_RCV_CFG_VLAN_MASK = 0xc0000000, MGMT_RCV_CFG_VLAN_ALL = 0x00000000, MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000, MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000, MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000 }

enum	{ RT_IDX_IDX_SHIFT = 8, RT_IDX_TYPE_MASK = 0x000f0000, RT_IDX_TYPE_SHIFT = 16, RT_IDX_TYPE_RT = 0x00000000, RT_IDX_TYPE_RT_INV = 0x00010000, RT_IDX_TYPE_NICQ = 0x00020000, RT_IDX_TYPE_NICQ_INV = 0x00030000, RT_IDX_DST_MASK = 0x00700000, RT_IDX_DST_RSS = 0x00000000, RT_IDX_DST_CAM_Q = 0x00100000, RT_IDX_DST_COS_Q = 0x00200000, RT_IDX_DST_DFLT_Q = 0x00300000, RT_IDX_DST_DEST_Q = 0x00400000, RT_IDX_RS = (1 << 26), RT_IDX_E = (1 << 27), RT_IDX_MR = (1 << 30), RT_IDX_MW = (1 << 31), RT_IDX_BCAST = (1 << 0), RT_IDX_MCAST = (1 << 1), RT_IDX_MCAST_MATCH = (1 << 2), RT_IDX_MCAST_REG_MATCH = (1 << 3), RT_IDX_MCAST_HASH_MATCH = (1 << 4), RT_IDX_FC_MACH = (1 << 5), RT_IDX_ETH_FCOE = (1 << 6), RT_IDX_CAM_HIT = (1 << 7), RT_IDX_CAM_BIT0 = (1 << 8), RT_IDX_CAM_BIT1 = (1 << 9), RT_IDX_VLAN_TAG = (1 << 10), RT_IDX_VLAN_MATCH = (1 << 11), RT_IDX_VLAN_FILTER = (1 << 12), RT_IDX_ETH_SKIP1 = (1 << 13), RT_IDX_ETH_SKIP2 = (1 << 14), RT_IDX_BCAST_MCAST_MATCH = (1 << 15), RT_IDX_802_3 = (1 << 16), RT_IDX_LLDP = (1 << 17), RT_IDX_UNUSED018 = (1 << 18), RT_IDX_UNUSED019 = (1 << 19), RT_IDX_UNUSED20 = (1 << 20), RT_IDX_UNUSED21 = (1 << 21), RT_IDX_ERR = (1 << 22), RT_IDX_VALID = (1 << 23), RT_IDX_TU_CSUM_ERR = (1 << 24), RT_IDX_IP_CSUM_ERR = (1 << 25), RT_IDX_MAC_ERR = (1 << 26), RT_IDX_RSS_TCP6 = (1 << 27), RT_IDX_RSS_TCP4 = (1 << 28), RT_IDX_RSS_IPV6 = (1 << 29), RT_IDX_RSS_IPV4 = (1 << 30), RT_IDX_RSS_MATCH = (1 << 31), RT_IDX_ALL_ERR_SLOT = 0, RT_IDX_MAC_ERR_SLOT = 0, RT_IDX_IP_CSUM_ERR_SLOT = 1, RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2, RT_IDX_BCAST_SLOT = 3, RT_IDX_MCAST_MATCH_SLOT = 4, RT_IDX_ALLMULTI_SLOT = 5, RT_IDX_UNUSED6_SLOT = 6, RT_IDX_UNUSED7_SLOT = 7, RT_IDX_RSS_MATCH_SLOT = 8, RT_IDX_RSS_IPV4_SLOT = 8, RT_IDX_RSS_IPV6_SLOT = 9, RT_IDX_RSS_TCP4_SLOT = 10, RT_IDX_RSS_TCP6_SLOT = 11, RT_IDX_CAM_HIT_SLOT = 12, RT_IDX_UNUSED013 = 13, RT_IDX_UNUSED014 = 14, RT_IDX_PROMISCUOUS_SLOT = 15, RT_IDX_MAX_RT_SLOTS = 8, RT_IDX_MAX_NIC_SLOTS = 16 }

enum	{ XG_SERDES_ADDR_RDY = (1 << 31), XG_SERDES_ADDR_R = (1 << 30), XG_SERDES_ADDR_STS = 0x00001E06, XG_SERDES_ADDR_XFI1_PWR_UP = 0x00000005, XG_SERDES_ADDR_XFI2_PWR_UP = 0x0000000a, XG_SERDES_ADDR_XAUI_PWR_DOWN = 0x00000001, XG_SERDES_XAUI_AN_START = 0x00000000, XG_SERDES_XAUI_AN_END = 0x00000034, XG_SERDES_XAUI_HSS_PCS_START = 0x00000800, XG_SERDES_XAUI_HSS_PCS_END = 0x0000880, XG_SERDES_XFI_AN_START = 0x00001000, XG_SERDES_XFI_AN_END = 0x00001034, XG_SERDES_XFI_TRAIN_START = 0x10001050, XG_SERDES_XFI_TRAIN_END = 0x1000107C, XG_SERDES_XFI_HSS_PCS_START = 0x00001800, XG_SERDES_XFI_HSS_PCS_END = 0x00001838, XG_SERDES_XFI_HSS_TX_START = 0x00001c00, XG_SERDES_XFI_HSS_TX_END = 0x00001c1f, XG_SERDES_XFI_HSS_RX_START = 0x00001c40, XG_SERDES_XFI_HSS_RX_END = 0x00001c5f, XG_SERDES_XFI_HSS_PLL_START = 0x00001e00, XG_SERDES_XFI_HSS_PLL_END = 0x00001e1f }

enum	{ PRB_MX_ADDR_ARE = (1 << 16), PRB_MX_ADDR_UP = (1 << 15), PRB_MX_ADDR_SWP = (1 << 14), PRB_MX_ADDR_MAX_MODS = 21, PRB_MX_ADDR_MOD_SEL_SHIFT = 9, PRB_MX_ADDR_MOD_SEL_TBD = 0, PRB_MX_ADDR_MOD_SEL_IDE1 = 1, PRB_MX_ADDR_MOD_SEL_IDE2 = 2, PRB_MX_ADDR_MOD_SEL_FRB = 3, PRB_MX_ADDR_MOD_SEL_ODE1 = 4, PRB_MX_ADDR_MOD_SEL_ODE2 = 5, PRB_MX_ADDR_MOD_SEL_DA1 = 6, PRB_MX_ADDR_MOD_SEL_DA2 = 7, PRB_MX_ADDR_MOD_SEL_IMP1 = 8, PRB_MX_ADDR_MOD_SEL_IMP2 = 9, PRB_MX_ADDR_MOD_SEL_OMP1 = 10, PRB_MX_ADDR_MOD_SEL_OMP2 = 11, PRB_MX_ADDR_MOD_SEL_ORS1 = 12, PRB_MX_ADDR_MOD_SEL_ORS2 = 13, PRB_MX_ADDR_MOD_SEL_REG = 14, PRB_MX_ADDR_MOD_SEL_MAC1 = 16, PRB_MX_ADDR_MOD_SEL_MAC2 = 17, PRB_MX_ADDR_MOD_SEL_VQM1 = 18, PRB_MX_ADDR_MOD_SEL_VQM2 = 19, PRB_MX_ADDR_MOD_SEL_MOP = 20, PRB_MX_ADDR_VALID_SYS_MOD = 0x000f7ff7, PRB_MX_ADDR_VALID_PCI_MOD = 0x000040c1, PRB_MX_ADDR_VALID_XGM_MOD = 0x00037309, PRB_MX_ADDR_VALID_FC_MOD = 0x00003001, PRB_MX_ADDR_VALID_TOTAL = 34, PRB_MX_ADDR_CLOCK_SHIFT = 6, PRB_MX_ADDR_SYS_CLOCK = 0, PRB_MX_ADDR_PCI_CLOCK = 2, PRB_MX_ADDR_FC_CLOCK = 5, PRB_MX_ADDR_XGM_CLOCK = 6, PRB_MX_ADDR_MAX_MUX = 64 }

enum	{ PROC_ADDR = 0, PROC_DATA = 0x04, SYS = 0x08, RST_FO = 0x0c, FSC = 0x10, CSR = 0x14, LED = 0x18, ICB_RID = 0x1c, ICB_L = 0x20, ICB_H = 0x24, CFG = 0x28, BIOS_ADDR = 0x2c, STS = 0x30, INTR_EN = 0x34, INTR_MASK = 0x38, ISR1 = 0x3c, ISR2 = 0x40, ISR3 = 0x44, ISR4 = 0x48, REV_ID = 0x4c, FRC_ECC_ERR = 0x50, ERR_STS = 0x54, RAM_DBG_ADDR = 0x58, RAM_DBG_DATA = 0x5c, ECC_ERR_CNT = 0x60, SEM = 0x64, GPIO_1 = 0x68, GPIO_2 = 0x6c, GPIO_3 = 0x70, RSVD2 = 0x74, XGMAC_ADDR = 0x78, XGMAC_DATA = 0x7c, NIC_ETS = 0x80, CNA_ETS = 0x84, FLASH_ADDR = 0x88, FLASH_DATA = 0x8c, CQ_STOP = 0x90, PAGE_TBL_RID = 0x94, WQ_PAGE_TBL_LO = 0x98, WQ_PAGE_TBL_HI = 0x9c, CQ_PAGE_TBL_LO = 0xa0, CQ_PAGE_TBL_HI = 0xa4, MAC_ADDR_IDX = 0xa8, MAC_ADDR_DATA = 0xac, COS_DFLT_CQ1 = 0xb0, COS_DFLT_CQ2 = 0xb4, ETYPE_SKIP1 = 0xb8, ETYPE_SKIP2 = 0xbc, SPLT_HDR = 0xc0, FC_PAUSE_THRES = 0xc4, NIC_PAUSE_THRES = 0xc8, FC_ETHERTYPE = 0xcc, FC_RCV_CFG = 0xd0, NIC_RCV_CFG = 0xd4, FC_COS_TAGS = 0xd8, NIC_COS_TAGS = 0xdc, MGMT_RCV_CFG = 0xe0, RT_IDX = 0xe4, RT_DATA = 0xe8, RSVD7 = 0xec, XG_SERDES_ADDR = 0xf0, XG_SERDES_DATA = 0xf4, PRB_MX_ADDR = 0xf8, PRB_MX_DATA = 0xfc }

enum	{ CAM_OUT_ROUTE_FC = 0, CAM_OUT_ROUTE_NIC = 1, CAM_OUT_FUNC_SHIFT = 2, CAM_OUT_RV = (1 << 4), CAM_OUT_SH = (1 << 15), CAM_OUT_CQ_ID_SHIFT = 5 }

enum	{ AEN_SYS_ERR = 0x00008002, AEN_LINK_UP = 0x00008011, AEN_LINK_DOWN = 0x00008012, AEN_IDC_CMPLT = 0x00008100, AEN_IDC_REQ = 0x00008101, AEN_IDC_EXT = 0x00008102, AEN_DCBX_CHG = 0x00008110, AEN_AEN_LOST = 0x00008120, AEN_AEN_SFP_IN = 0x00008130, AEN_AEN_SFP_OUT = 0x00008131, AEN_FW_INIT_DONE = 0x00008400, AEN_FW_INIT_FAIL = 0x00008401, MB_CMD_NOP = 0x00000000, MB_CMD_EX_FW = 0x00000002, MB_CMD_MB_TEST = 0x00000006, MB_CMD_CSUM_TEST = 0x00000007, MB_CMD_ABOUT_FW = 0x00000008, MB_CMD_COPY_RISC_RAM = 0x0000000a, MB_CMD_LOAD_RISC_RAM = 0x0000000b, MB_CMD_DUMP_RISC_RAM = 0x0000000c, MB_CMD_WRITE_RAM = 0x0000000d, MB_CMD_INIT_RISC_RAM = 0x0000000e, MB_CMD_READ_RAM = 0x0000000f, MB_CMD_STOP_FW = 0x00000014, MB_CMD_MAKE_SYS_ERR = 0x0000002a, MB_CMD_WRITE_SFP = 0x00000030, MB_CMD_READ_SFP = 0x00000031, MB_CMD_INIT_FW = 0x00000060, MB_CMD_GET_IFCB = 0x00000061, MB_CMD_GET_FW_STATE = 0x00000069, MB_CMD_IDC_REQ = 0x00000100, MB_CMD_IDC_ACK = 0x00000101, MB_CMD_SET_WOL_MODE = 0x00000110, MB_WOL_DISABLE = 0, MB_WOL_MAGIC_PKT = (1 << 1), MB_WOL_FLTR = (1 << 2), MB_WOL_UCAST = (1 << 3), MB_WOL_MCAST = (1 << 4), MB_WOL_BCAST = (1 << 5), MB_WOL_LINK_UP = (1 << 6), MB_WOL_LINK_DOWN = (1 << 7), MB_WOL_MODE_ON = (1 << 16), MB_CMD_SET_WOL_FLTR = 0x00000111, MB_CMD_CLEAR_WOL_FLTR = 0x00000112, MB_CMD_SET_WOL_MAGIC = 0x00000113, MB_CMD_CLEAR_WOL_MAGIC = 0x00000114, MB_CMD_SET_WOL_IMMED = 0x00000115, MB_CMD_PORT_RESET = 0x00000120, MB_CMD_SET_PORT_CFG = 0x00000122, MB_CMD_GET_PORT_CFG = 0x00000123, MB_CMD_GET_LINK_STS = 0x00000124, MB_CMD_SET_LED_CFG = 0x00000125, QL_LED_BLINK = 0x03e803e8, MB_CMD_GET_LED_CFG = 0x00000126, MB_CMD_SET_MGMNT_TFK_CTL = 0x00000160, MB_SET_MPI_TFK_STOP = (1 << 0), MB_SET_MPI_TFK_RESUME = (1 << 1), MB_CMD_GET_MGMNT_TFK_CTL = 0x00000161, MB_GET_MPI_TFK_STOPPED = (1 << 0), MB_GET_MPI_TFK_FIFO_EMPTY = (1 << 1), MB_CMD_IOP_NONE = 0x0000, MB_CMD_IOP_PREP_UPDATE_MPI = 0x0001, MB_CMD_IOP_COMP_UPDATE_MPI = 0x0002, MB_CMD_IOP_PREP_LINK_DOWN = 0x0010, MB_CMD_IOP_DVR_START = 0x0100, MB_CMD_IOP_FLASH_ACC = 0x0101, MB_CMD_IOP_RESTART_MPI = 0x0102, MB_CMD_IOP_CORE_DUMP_MPI = 0x0103, MB_CMD_STS_GOOD = 0x00004000, MB_CMD_STS_INTRMDT = 0x00001000, MB_CMD_STS_INVLD_CMD = 0x00004001, MB_CMD_STS_XFC_ERR = 0x00004002, MB_CMD_STS_CSUM_ERR = 0x00004003, MB_CMD_STS_ERR = 0x00004005, MB_CMD_STS_PARAM_ERR = 0x00004006 }

enum	{ DEFAULT_Q = 2, TX_Q = 3, RX_Q = 4 }

enum	{ MPI_CORE_REGS_ADDR = 0x00030000, MPI_CORE_REGS_CNT = 127, MPI_CORE_SH_REGS_CNT = 16, TEST_REGS_ADDR = 0x00001000, TEST_REGS_CNT = 23, RMII_REGS_ADDR = 0x00001040, RMII_REGS_CNT = 64, FCMAC1_REGS_ADDR = 0x00001080, FCMAC2_REGS_ADDR = 0x000010c0, FCMAC_REGS_CNT = 64, FC1_MBX_REGS_ADDR = 0x00001100, FC2_MBX_REGS_ADDR = 0x00001240, FC_MBX_REGS_CNT = 64, IDE_REGS_ADDR = 0x00001140, IDE_REGS_CNT = 64, NIC1_MBX_REGS_ADDR = 0x00001180, NIC2_MBX_REGS_ADDR = 0x00001280, NIC_MBX_REGS_CNT = 64, SMBUS_REGS_ADDR = 0x00001200, SMBUS_REGS_CNT = 64, I2C_REGS_ADDR = 0x00001fc0, I2C_REGS_CNT = 64, MEMC_REGS_ADDR = 0x00003000, MEMC_REGS_CNT = 256, PBUS_REGS_ADDR = 0x00007c00, PBUS_REGS_CNT = 256, MDE_REGS_ADDR = 0x00010000, MDE_REGS_CNT = 6, CODE_RAM_ADDR = 0x00020000, CODE_RAM_CNT = 0x2000, MEMC_RAM_ADDR = 0x00100000, MEMC_RAM_CNT = 0x2000 }

enum	{ CORE_SEG_NUM = 1, TEST_LOGIC_SEG_NUM = 2, RMII_SEG_NUM = 3, FCMAC1_SEG_NUM = 4, FCMAC2_SEG_NUM = 5, FC1_MBOX_SEG_NUM = 6, IDE_SEG_NUM = 7, NIC1_MBOX_SEG_NUM = 8, SMBUS_SEG_NUM = 9, FC2_MBOX_SEG_NUM = 10, NIC2_MBOX_SEG_NUM = 11, I2C_SEG_NUM = 12, MEMC_SEG_NUM = 13, PBUS_SEG_NUM = 14, MDE_SEG_NUM = 15, NIC1_CONTROL_SEG_NUM = 16, NIC2_CONTROL_SEG_NUM = 17, NIC1_XGMAC_SEG_NUM = 18, NIC2_XGMAC_SEG_NUM = 19, WCS_RAM_SEG_NUM = 20, MEMC_RAM_SEG_NUM = 21, XAUI_AN_SEG_NUM = 22, XAUI_HSS_PCS_SEG_NUM = 23, XFI_AN_SEG_NUM = 24, XFI_TRAIN_SEG_NUM = 25, XFI_HSS_PCS_SEG_NUM = 26, XFI_HSS_TX_SEG_NUM = 27, XFI_HSS_RX_SEG_NUM = 28, XFI_HSS_PLL_SEG_NUM = 29, MISC_NIC_INFO_SEG_NUM = 30, INTR_STATES_SEG_NUM = 31, CAM_ENTRIES_SEG_NUM = 32, ROUTING_WORDS_SEG_NUM = 33, ETS_SEG_NUM = 34, PROBE_DUMP_SEG_NUM = 35, ROUTING_INDEX_SEG_NUM = 36, MAC_PROTOCOL_SEG_NUM = 37, XAUI2_AN_SEG_NUM = 38, XAUI2_HSS_PCS_SEG_NUM = 39, XFI2_AN_SEG_NUM = 40, XFI2_TRAIN_SEG_NUM = 41, XFI2_HSS_PCS_SEG_NUM = 42, XFI2_HSS_TX_SEG_NUM = 43, XFI2_HSS_RX_SEG_NUM = 44, XFI2_HSS_PLL_SEG_NUM = 45, SEM_REGS_SEG_NUM = 50 }

enum	{ QL_ADAPTER_UP = 0, QL_LEGACY_ENABLED = 1, QL_MSI_ENABLED = 2, QL_MSIX_ENABLED = 3, QL_DMA64 = 4, QL_PROMISCUOUS = 5, QL_ALLMULTI = 6, QL_PORT_CFG = 7, QL_CAM_RT_SET = 8, QL_SELFTEST = 9, QL_LB_LINK_UP = 10, QL_FRC_COREDUMP = 11, QL_EEH_FATAL = 12, QL_ASIC_RECOVERY = 14 }

enum	{ STS_LOOPBACK_MASK = 0x00000700, STS_LOOPBACK_PCS = 0x00000100, STS_LOOPBACK_HSS = 0x00000200, STS_LOOPBACK_EXT = 0x00000300, STS_PAUSE_MASK = 0x000000c0, STS_PAUSE_STD = 0x00000040, STS_PAUSE_PRI = 0x00000080, STS_SPEED_MASK = 0x00000038, STS_SPEED_100Mb = 0x00000000, STS_SPEED_1Gb = 0x00000008, STS_SPEED_10Gb = 0x00000010, STS_LINK_TYPE_MASK = 0x00000007, STS_LINK_TYPE_XFI = 0x00000001, STS_LINK_TYPE_XAUI = 0x00000002, STS_LINK_TYPE_XFI_BP = 0x00000003, STS_LINK_TYPE_XAUI_BP = 0x00000004, STS_LINK_TYPE_10GBASET = 0x00000005 }

enum	{ CFG_JUMBO_FRAME_SIZE = 0x00010000, CFG_PAUSE_MASK = 0x00000060, CFG_PAUSE_STD = 0x00000020, CFG_PAUSE_PRI = 0x00000040, CFG_DCBX = 0x00000010, CFG_LOOPBACK_MASK = 0x00000007, CFG_LOOPBACK_PCS = 0x00000002, CFG_LOOPBACK_HSS = 0x00000004, CFG_LOOPBACK_EXT = 0x00000006, CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580 }

Functions
int	ql_sem_spinlock (struct ql_adapter *qdev, u32 sem_mask)

void	ql_sem_unlock (struct ql_adapter *qdev, u32 sem_mask)

int	ql_read_xgmac_reg (struct ql_adapter qdev, u32 reg, u32 data)

int	ql_get_mac_addr_reg (struct ql_adapter qdev, u32 type, u16 index, u32 value)

int	ql_get_routing_reg (struct ql_adapter qdev, u32 index, u32 value)

int	ql_write_cfg (struct ql_adapter qdev, void ptr, int size, u32 bit, u16 q_id)

void	ql_queue_fw_error (struct ql_adapter *qdev)

void	ql_mpi_work (struct work_struct *work)

void	ql_mpi_reset_work (struct work_struct *work)

void	ql_mpi_core_to_log (struct work_struct *work)

int	ql_wait_reg_rdy (struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit)

void	ql_queue_asic_error (struct ql_adapter *qdev)

u32	ql_enable_completion_interrupt (struct ql_adapter *qdev, u32 intr)

void	ql_set_ethtool_ops (struct net_device *ndev)

int	ql_read_xgmac_reg64 (struct ql_adapter qdev, u32 reg, u64 data)

void	ql_mpi_idc_work (struct work_struct *work)

void	ql_mpi_port_cfg_work (struct work_struct *work)

int	ql_mb_get_fw_state (struct ql_adapter *qdev)

int	ql_cam_route_initialize (struct ql_adapter *qdev)

int	ql_read_mpi_reg (struct ql_adapter qdev, u32 reg, u32 data)

int	ql_write_mpi_reg (struct ql_adapter *qdev, u32 reg, u32 data)

int	ql_unpause_mpi_risc (struct ql_adapter *qdev)

int	ql_pause_mpi_risc (struct ql_adapter *qdev)

int	ql_hard_reset_mpi_risc (struct ql_adapter *qdev)

int	ql_soft_reset_mpi_risc (struct ql_adapter *qdev)

int	ql_dump_risc_ram_area (struct ql_adapter qdev, void buf, u32 ram_addr, int word_count)

int	ql_core_dump (struct ql_adapter qdev, struct ql_mpi_coredump mpi_coredump)

int	ql_mb_about_fw (struct ql_adapter *qdev)

int	ql_mb_wol_set_magic (struct ql_adapter *qdev, u32 enable_wol)

int	ql_mb_wol_mode (struct ql_adapter *qdev, u32 wol)

int	ql_mb_set_led_cfg (struct ql_adapter *qdev, u32 led_config)

int	ql_mb_get_led_cfg (struct ql_adapter *qdev)

void	ql_link_on (struct ql_adapter *qdev)

void	ql_link_off (struct ql_adapter *qdev)

int	ql_mb_set_mgmnt_traffic_ctl (struct ql_adapter *qdev, u32 control)

int	ql_mb_get_port_cfg (struct ql_adapter *qdev)

int	ql_mb_set_port_cfg (struct ql_adapter *qdev)

int	ql_wait_fifo_empty (struct ql_adapter *qdev)

void	ql_get_dump (struct ql_adapter qdev, void buff)

void	ql_gen_reg_dump (struct ql_adapter qdev, struct ql_reg_dump mpi_coredump)

netdev_tx_t	ql_lb_send (struct sk_buff skb, struct net_device ndev)

void	ql_check_lb_frame (struct ql_adapter , struct sk_buff )

int	ql_own_firmware (struct ql_adapter *qdev)

int	ql_clean_lb_rx_ring (struct rx_ring *rx_ring, int budget)

Variables
struct tx_buf_desc	__packed

char	qlge_driver_name []

const char	qlge_driver_version []

struct ethtool_ops	qlge_ethtool_ops

Macro Definition Documentation

#define CAM_LOOKUP_ERR_EVENT 0x06

Definition at line 1229 of file qlge.h.

#define DB_PAGE_SIZE 4096

Definition at line 39 of file qlge.h.

#define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */

Definition at line 55 of file qlge.h.

#define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2)

Definition at line 57 of file qlge.h.

#define DRV_NAME "qlge"

Definition at line 19 of file qlge.h.

#define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "

Definition at line 20 of file qlge.h.

#define DRV_VERSION "v1.00.00.31"

Definition at line 21 of file qlge.h.

#define ETS_REGS_DUMP_WORD_COUNT 10

Definition at line 1691 of file qlge.h.

#define FLAGS_LC 0x80

Definition at line 1302 of file qlge.h.

#define FLAGS_LI 0x40

Definition at line 1301 of file qlge.h.

#define FLAGS_LL 0x20

Definition at line 1300 of file qlge.h.

#define FLAGS_LS 0x10

Definition at line 1299 of file qlge.h.

#define FLAGS_LV 0x08

Definition at line 1298 of file qlge.h.

#define FUNC0_FLASH_OFFSET 0x140200

Definition at line 1001 of file qlge.h.

#define FUNC1_FLASH_OFFSET 0x140600

Definition at line 1002 of file qlge.h.

#define GPI0_H2L_EVENT 0x10

Definition at line 1233 of file qlge.h.

#define GPI0_L2H_EVENT 0x20

Definition at line 1234 of file qlge.h.

#define GPI1_H2L_EVENT 0x11

Definition at line 1235 of file qlge.h.

#define GPI1_L2H_EVENT 0x21

Definition at line 1236 of file qlge.h.

#define IB_AE_IOCB_RSP_I 0x02

Definition at line 1225 of file qlge.h.

#define IB_AE_IOCB_RSP_OI 0x01

Definition at line 1224 of file qlge.h.

#define IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */

Definition at line 1167 of file qlge.h.

#define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */

Definition at line 1176 of file qlge.h.

#define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */

Definition at line 1206 of file qlge.h.

#define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */

Definition at line 1207 of file qlge.h.

#define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */

Definition at line 1201 of file qlge.h.

#define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */

Definition at line 1200 of file qlge.h.

#define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04

Definition at line 1181 of file qlge.h.

#define IB_MAC_IOCB_RSP_ERR_CRC 0x1c

Definition at line 1186 of file qlge.h.

#define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18

Definition at line 1185 of file qlge.h.

#define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */

Definition at line 1180 of file qlge.h.

#define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08

Definition at line 1182 of file qlge.h.

#define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14

Definition at line 1184 of file qlge.h.

#define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10

Definition at line 1183 of file qlge.h.

#define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */

Definition at line 1189 of file qlge.h.

#define IB_MAC_IOCB_RSP_HL 0x80

Definition at line 1216 of file qlge.h.

#define IB_MAC_IOCB_RSP_HS 0x40

Definition at line 1215 of file qlge.h.

#define IB_MAC_IOCB_RSP_HV 0x20

Definition at line 1214 of file qlge.h.

#define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */

Definition at line 1166 of file qlge.h.

#define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */

Definition at line 1170 of file qlge.h.

#define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */

Definition at line 1199 of file qlge.h.

#define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */

Definition at line 1173 of file qlge.h.

#define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */

Definition at line 1193 of file qlge.h.

#define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */

Definition at line 1194 of file qlge.h.

#define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */

Definition at line 1171 of file qlge.h.

#define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */

Definition at line 1192 of file qlge.h.

#define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */

Definition at line 1192 of file qlge.h.

#define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */

Definition at line 1175 of file qlge.h.

#define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */

Definition at line 1174 of file qlge.h.

#define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */

Definition at line 1195 of file qlge.h.

#define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */

Definition at line 1196 of file qlge.h.

#define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */

Definition at line 1169 of file qlge.h.

#define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */

Definition at line 1165 of file qlge.h.

#define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */

Definition at line 1178 of file qlge.h.

#define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */

Definition at line 1191 of file qlge.h.

#define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */

Definition at line 1188 of file qlge.h.

#define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */

Definition at line 1168 of file qlge.h.

#define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */

Definition at line 1187 of file qlge.h.

#define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */

Definition at line 1179 of file qlge.h.

#define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */

Definition at line 1197 of file qlge.h.

#define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */

Definition at line 1198 of file qlge.h.

#define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff

Definition at line 1208 of file qlge.h.

#define LARGE_BUFFER_MAX_SIZE 8192

Definition at line 51 of file qlge.h.

#define LARGE_BUFFER_MIN_SIZE 2048

Definition at line 52 of file qlge.h.

#define LEN_CPP_128 0x0003

Definition at line 1308 of file qlge.h.

#define LEN_CPP_32 0x0001

Definition at line 1306 of file qlge.h.

#define LEN_CPP_64 0x0002

Definition at line 1307 of file qlge.h.

#define LEN_CPP_CONT 0x0000

Definition at line 1305 of file qlge.h.

#define LEN_V (1 << 4)

Definition at line 1304 of file qlge.h.

#define LINK_DOWN_EVENT 0x01

Definition at line 1228 of file qlge.h.

#define LINK_UP_EVENT 0x00

Definition at line 1227 of file qlge.h.

#define LSD ( x ) ((u32)((u64)(x)))

Definition at line 77 of file qlge.h.

#define LSW ( x ) ((u16)(x))

Definition at line 75 of file qlge.h.

#define MAC_ADDR_DUMP_ENTRIES

Value:

Definition at line 1713 of file qlge.h.

#define MAC_ADDR_DUMP_TOT_WORDS

Value:

(MAC_ADDR_DUMP_ENTRIES * \

MAC_ADDR_DUMP_WORDS_PER_ENTRY)

Definition at line 1725 of file qlge.h.

#define MAC_ADDR_DUMP_WORDS_PER_ENTRY 2

Definition at line 1724 of file qlge.h.

#define MAX_CPUS 8

Definition at line 30 of file qlge.h.

#define MAX_CQ 128

Definition at line 54 of file qlge.h.

#define MAX_DB_PAGES_PER_BQ ( x )

Value:

(((x * sizeof(u64)) / DB_PAGE_SIZE) + \

(((x * sizeof(u64)) % DB_PAGE_SIZE) ? 1 : 0))

Definition at line 44 of file qlge.h.

#define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */

Definition at line 56 of file qlge.h.

#define MAX_RX_RINGS ((MAX_CPUS * 2) + 1)

Definition at line 32 of file qlge.h.

#define MAX_SEMAPHORE_FUNCTIONS 4

Definition at line 1730 of file qlge.h.

#define MAX_TX_RINGS MAX_CPUS

Definition at line 31 of file qlge.h.

#define MGMT_ERR_EVENT 0x08

Definition at line 1231 of file qlge.h.

#define MPI_COREDUMP_COOKIE 0x5555aaaa

Definition at line 1606 of file qlge.h.

#define MSD ( x ) ((u32)((((u64)(x)) >> 32)))

Definition at line 78 of file qlge.h.

#define MSW ( x ) ((u16)((u32)(x) >> 16))

Definition at line 76 of file qlge.h.

#define NIC_REGS_DUMP_WORD_COUNT 64

Definition at line 1677 of file qlge.h.

#define NUM_LARGE_BUFFERS 512

Definition at line 38 of file qlge.h.

#define NUM_RX_RING_ENTRIES 256

Definition at line 35 of file qlge.h.

#define NUM_SMALL_BUFFERS 512

Definition at line 37 of file qlge.h.

#define NUM_TX_RING_ENTRIES 256

Definition at line 34 of file qlge.h.

#define OB_MAC_IOCB_DFP 0x02

Definition at line 1086 of file qlge.h.

#define OB_MAC_IOCB_LEN_MASK 0x3ffff

Definition at line 1090 of file qlge.h.

#define OB_MAC_IOCB_REQ_D 0x08

Definition at line 1082 of file qlge.h.

#define OB_MAC_IOCB_REQ_F 0x10

Definition at line 1083 of file qlge.h.

#define OB_MAC_IOCB_REQ_I 0x02

Definition at line 1081 of file qlge.h.

#define OB_MAC_IOCB_REQ_OI 0x01

Definition at line 1080 of file qlge.h.

#define OB_MAC_IOCB_RSP_B 0x80 /* */

Definition at line 1111 of file qlge.h.

#define OB_MAC_IOCB_RSP_E 0x08 /* */

Definition at line 1105 of file qlge.h.

#define OB_MAC_IOCB_RSP_I 0x02 /* */

Definition at line 1104 of file qlge.h.

#define OB_MAC_IOCB_RSP_L 0x20 /* too Large */

Definition at line 1107 of file qlge.h.

#define OB_MAC_IOCB_RSP_OI 0x01 /* */

Definition at line 1103 of file qlge.h.

#define OB_MAC_IOCB_RSP_P 0x40 /* Padded */

Definition at line 1108 of file qlge.h.

#define OB_MAC_IOCB_RSP_S 0x10 /* too Short */

Definition at line 1106 of file qlge.h.

#define OB_MAC_IOCB_V 0x04

Definition at line 1087 of file qlge.h.

#define OB_MAC_TRANSPORT_HDR_SHIFT 6

Definition at line 1139 of file qlge.h.

#define OB_MAC_TSO_IOCB_D 0x08

Definition at line 1122 of file qlge.h.

#define OB_MAC_TSO_IOCB_DFP 0x02

Definition at line 1131 of file qlge.h.

#define OB_MAC_TSO_IOCB_I 0x02

Definition at line 1121 of file qlge.h.

#define OB_MAC_TSO_IOCB_IC 0x01

Definition at line 1130 of file qlge.h.

#define OB_MAC_TSO_IOCB_IP4 0x40

Definition at line 1123 of file qlge.h.

#define OB_MAC_TSO_IOCB_IP6 0x80

Definition at line 1124 of file qlge.h.

#define OB_MAC_TSO_IOCB_LSO 0x20

Definition at line 1126 of file qlge.h.

#define OB_MAC_TSO_IOCB_OI 0x01

Definition at line 1120 of file qlge.h.

#define OB_MAC_TSO_IOCB_RSP_B 0x8000

Definition at line 1156 of file qlge.h.

#define OB_MAC_TSO_IOCB_RSP_E 0x08

Definition at line 1150 of file qlge.h.

#define OB_MAC_TSO_IOCB_RSP_I 0x02

Definition at line 1149 of file qlge.h.

#define OB_MAC_TSO_IOCB_RSP_L 0x20

Definition at line 1152 of file qlge.h.

#define OB_MAC_TSO_IOCB_RSP_OI 0x01

Definition at line 1148 of file qlge.h.

#define OB_MAC_TSO_IOCB_RSP_P 0x40

Definition at line 1153 of file qlge.h.

#define OB_MAC_TSO_IOCB_RSP_S 0x10

Definition at line 1151 of file qlge.h.

#define OB_MAC_TSO_IOCB_TC 0x80

Definition at line 1128 of file qlge.h.

#define OB_MAC_TSO_IOCB_UC 0x40

Definition at line 1127 of file qlge.h.

#define OB_MAC_TSO_IOCB_V 0x04

Definition at line 1132 of file qlge.h.

#define OPCODE_IB_AE_IOCB 0x3f

Definition at line 1075 of file qlge.h.

#define OPCODE_IB_MAC_IOCB 0x20

Definition at line 1073 of file qlge.h.

#define OPCODE_IB_MPI_IOCB 0x21

Definition at line 1074 of file qlge.h.

#define OPCODE_OB_MAC_IOCB 0x01

Definition at line 1071 of file qlge.h.

#define OPCODE_OB_MAC_TSO_IOCB 0x02

Definition at line 1072 of file qlge.h.

#define PCI_ERR_ANON_BUF_RD 0x40

Definition at line 1237 of file qlge.h.

#define PRB_MX_ADDR_PRB_WORD_COUNT (1 + (PRB_MX_ADDR_MAX_MUX * 2))

Definition at line 1697 of file qlge.h.

#define PRB_MX_DUMP_TOT_COUNT

Value:

(PRB_MX_ADDR_PRB_WORD_COUNT * \

PRB_MX_ADDR_VALID_TOTAL)

Definition at line 1698 of file qlge.h.

#define Q_CQ_ID_RSS_RV 0x8000

Definition at line 1282 of file qlge.h.

#define Q_FLAGS_LB 0x2000

Definition at line 1278 of file qlge.h.

#define Q_FLAGS_LC 0x1000

Definition at line 1277 of file qlge.h.

#define Q_FLAGS_LI 0x4000

Definition at line 1279 of file qlge.h.

#define Q_FLAGS_LO 0x8000

Definition at line 1280 of file qlge.h.

#define Q_LEN_CPP_16 0x0001

Definition at line 1271 of file qlge.h.

#define Q_LEN_CPP_32 0x0002

Definition at line 1272 of file qlge.h.

#define Q_LEN_CPP_512 0x0006

Definition at line 1274 of file qlge.h.

#define Q_LEN_CPP_64 0x0003

Definition at line 1273 of file qlge.h.

#define Q_LEN_CPP_CONT 0x0000

Definition at line 1270 of file qlge.h.

#define Q_LEN_V (1 << 4)

Definition at line 1269 of file qlge.h.

#define Q_PRI_SHIFT 1

Definition at line 1276 of file qlge.h.

#define QL_DUMP_ALL ( qdev )

Definition at line 2338 of file qlge.h.

#define QL_DUMP_CQICB ( cqicb )

Definition at line 2311 of file qlge.h.

#define QL_DUMP_HW_CB	(	qdev,
		size,
		bit,
		q_id
	)

Definition at line 2313 of file qlge.h.

#define QL_DUMP_IB_MAC_RSP ( ib_mac_rsp )

Definition at line 2331 of file qlge.h.

#define QL_DUMP_OB_MAC_IOCB ( ob_mac_iocb )

Definition at line 2323 of file qlge.h.

#define QL_DUMP_OB_MAC_RSP ( ob_mac_rsp )

Definition at line 2324 of file qlge.h.

#define QL_DUMP_QDEV ( qdev )

Definition at line 2290 of file qlge.h.

#define QL_DUMP_REGS ( qdev )

Definition at line 2274 of file qlge.h.

#define QL_DUMP_RICB ( ricb )

Definition at line 2308 of file qlge.h.

#define QL_DUMP_ROUTE ( qdev )

Definition at line 2275 of file qlge.h.

#define QL_DUMP_RX_RING ( rx_ring )

Definition at line 2312 of file qlge.h.

#define QL_DUMP_STAT ( qdev )

Definition at line 2283 of file qlge.h.

#define QL_DUMP_TX_RING ( tx_ring )

Definition at line 2310 of file qlge.h.

#define QL_DUMP_WQICB ( wqicb )

Definition at line 2309 of file qlge.h.

#define QL_DUMP_XGMAC_CONTROL_REGS ( qdev )

Definition at line 2276 of file qlge.h.

#define QL_TXQ_IDX	(	qdev,
		skb
	)	(smp_processor_id()%(qdev->tx_ring_count))

Definition at line 1380 of file qlge.h.

#define QLGE_DEVICE_ID_8000 0x8000

Definition at line 27 of file qlge.h.

#define QLGE_DEVICE_ID_8012 0x8012

Definition at line 26 of file qlge.h.

#define QLGE_MEZZ_SSYS_ID_068 0x0068

Definition at line 28 of file qlge.h.

#define QLGE_MEZZ_SSYS_ID_180 0x0180

Definition at line 29 of file qlge.h.

#define QLGE_SB_PAD 32

Definition at line 876 of file qlge.h.

#define QLGE_VENDOR_ID 0x1077

Definition at line 25 of file qlge.h.

#define RISC_124 0x0003007c

Definition at line 1732 of file qlge.h.

#define RISC_127 0x0003007f

Definition at line 1733 of file qlge.h.

#define RSS_L4K 0x80

Definition at line 1324 of file qlge.h.

#define RSS_L6K 0x01

Definition at line 1326 of file qlge.h.

#define RSS_LB 0x04

Definition at line 1328 of file qlge.h.

#define RSS_LI 0x02

Definition at line 1327 of file qlge.h.

#define RSS_LM 0x08

Definition at line 1329 of file qlge.h.

#define RSS_RI4 0x10

Definition at line 1330 of file qlge.h.

#define RSS_RI6 0x40

Definition at line 1332 of file qlge.h.

#define RSS_RT4 0x20

Definition at line 1331 of file qlge.h.

#define RSS_RT6 0x80

Definition at line 1333 of file qlge.h.

#define RT_IDX_DUMP_ENTRIES 48

Definition at line 1706 of file qlge.h.

#define RT_IDX_DUMP_TOT_WORDS

Value:

(RT_IDX_DUMP_ENTRIES * \

RT_IDX_DUMP_WORDS_PER_ENTRY)

Definition at line 1708 of file qlge.h.

#define RT_IDX_DUMP_WORDS_PER_ENTRY 4

Definition at line 1707 of file qlge.h.

#define RX_RING_SHADOW_SPACE

Value:

(sizeof(u64) + \
        MAX_DB_PAGES_PER_BQ(NUM_SMALL_BUFFERS) * sizeof(u64) + \
        MAX_DB_PAGES_PER_BQ(NUM_LARGE_BUFFERS) * sizeof(u64))

Definition at line 48 of file qlge.h.

#define SHADOW_OFFSET 0xb0000000

Definition at line 1734 of file qlge.h.

#define SHADOW_REG_SHIFT 20

Definition at line 1735 of file qlge.h.

#define SMALL_BUF_MAP_SIZE (SMALL_BUFFER_SIZE / 2)

Definition at line 872 of file qlge.h.

#define SMALL_BUFFER_SIZE 512

Definition at line 871 of file qlge.h.

#define SOFT_ECC_ERROR_EVENT 0x07

Definition at line 1230 of file qlge.h.

#define SPLT_LEN

Value:

(SPLT_HDR_EP | \

min(SMALL_BUF_MAP_SIZE, 1023))

Definition at line 874 of file qlge.h.

#define SPLT_SETTING FSC_SH

Definition at line 873 of file qlge.h.

#define TEN_GIG_MAC_EVENT 0x09

Definition at line 1232 of file qlge.h.

#define TX_DESC_C 0x40000000

Definition at line 1063 of file qlge.h.

#define TX_DESC_E 0x80000000

Definition at line 1064 of file qlge.h.

#define TX_DESC_LEN_MASK 0x000fffff

Definition at line 1062 of file qlge.h.

#define TX_DESC_PER_IOCB 8

Definition at line 62 of file qlge.h.

#define TX_DESC_PER_OAL 0

Definition at line 67 of file qlge.h.

#define UDELAY_COUNT 3

Definition at line 58 of file qlge.h.

#define UDELAY_DELAY 100

Definition at line 59 of file qlge.h.

#define WQ_ADDR_ALIGN 0x3 /* 4 byte alignment */

Definition at line 23 of file qlge.h.

#define XG_SERDES_XAUI_AN_COUNT 14

Definition at line 1681 of file qlge.h.

#define XG_SERDES_XAUI_HSS_PCS_COUNT 33

Definition at line 1682 of file qlge.h.

#define XG_SERDES_XFI_AN_COUNT 14

Definition at line 1683 of file qlge.h.

#define XG_SERDES_XFI_HSS_PCS_COUNT 15

Definition at line 1685 of file qlge.h.

#define XG_SERDES_XFI_HSS_PLL_COUNT 32

Definition at line 1688 of file qlge.h.

#define XG_SERDES_XFI_HSS_RX_COUNT 32

Definition at line 1687 of file qlge.h.

#define XG_SERDES_XFI_HSS_TX_COUNT 32

Definition at line 1686 of file qlge.h.

#define XG_SERDES_XFI_TRAIN_COUNT 12

Definition at line 1684 of file qlge.h.

#define XGMAC_DUMP_WORD_COUNT (XGMAC_REGISTER_END / 4)

Definition at line 1679 of file qlge.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

MPI_TEST_FUNC_PORT_CFG
MPI_TEST_FUNC_PRB_CTL
MPI_TEST_FUNC_PRB_EN
MPI_TEST_FUNC_RST_STS
MPI_TEST_FUNC_RST_FRC
MPI_TEST_NIC_FUNC_MASK
MPI_TEST_NIC1_FUNCTION_ENABLE
MPI_TEST_NIC1_FUNCTION_MASK
MPI_TEST_NIC1_FUNC_SHIFT
MPI_TEST_NIC2_FUNCTION_ENABLE
MPI_TEST_NIC2_FUNCTION_MASK
MPI_TEST_NIC2_FUNC_SHIFT
MPI_TEST_FC1_FUNCTION_ENABLE
MPI_TEST_FC1_FUNCTION_MASK
MPI_TEST_FC1_FUNCTION_SHIFT
MPI_TEST_FC2_FUNCTION_ENABLE
MPI_TEST_FC2_FUNCTION_MASK
MPI_TEST_FC2_FUNCTION_SHIFT
MPI_NIC_READ
MPI_NIC_REG_BLOCK
MPI_NIC_FUNCTION_SHIFT

Definition at line 84 of file qlge.h.

anonymous enum

Enumerator:

MAILBOX_COUNT
MAILBOX_TIMEOUT
PROC_ADDR_RDY
PROC_ADDR_R
PROC_ADDR_ERR
PROC_ADDR_DA
PROC_ADDR_FUNC0_MBI
PROC_ADDR_FUNC0_MBO
PROC_ADDR_FUNC0_CTL
PROC_ADDR_FUNC2_MBI
PROC_ADDR_FUNC2_MBO
PROC_ADDR_FUNC2_CTL
PROC_ADDR_MPI_RISC
PROC_ADDR_MDE
PROC_ADDR_REGBLOCK
PROC_ADDR_RISC_REG

Definition at line 112 of file qlge.h.

anonymous enum

Enumerator:

SYS_EFE
SYS_FAE
SYS_MDC
SYS_DST
SYS_DWC
SYS_EVW
SYS_OMP_DLY_MASK
SYS_ODI

Definition at line 137 of file qlge.h.

anonymous enum

Enumerator:

RST_FO_TFO
RST_FO_RR_MASK
RST_FO_RR_CQ_CAM
RST_FO_RR_DROP
RST_FO_RR_DQ
RST_FO_RR_RCV_FUNC_CQ
RST_FO_FRB
RST_FO_MOP
RST_FO_REG
RST_FO_FR

Definition at line 154 of file qlge.h.

anonymous enum

Enumerator:

FSC_DBRST_MASK
FSC_DBRST_256
FSC_DBRST_512
FSC_DBRST_768
FSC_DBRST_1024
FSC_DBL_MASK
FSC_DBL_DBRST
FSC_DBL_MAX_PLD
FSC_DBL_MAX_BRST
FSC_DBL_128_BYTES
FSC_EC
FSC_EPC_MASK
FSC_EPC_INBOUND
FSC_EPC_OUTBOUND
FSC_VM_PAGESIZE_MASK
FSC_VM_PAGE_2K
FSC_VM_PAGE_4K
FSC_VM_PAGE_8K
FSC_VM_PAGE_64K
FSC_SH
FSC_DSB
FSC_STE
FSC_FE

Definition at line 170 of file qlge.h.

anonymous enum

Enumerator:

CSR_ERR_STS_MASK
CSR_RR
CSR_HRI
CSR_RP
CSR_CMD_PARM_SHIFT
CSR_CMD_NOP
CSR_CMD_SET_RST
CSR_CMD_CLR_RST
CSR_CMD_SET_PAUSE
CSR_CMD_CLR_PAUSE
CSR_CMD_SET_H2R_INT
CSR_CMD_CLR_H2R_INT
CSR_CMD_PAR_EN
CSR_CMD_SET_BAD_PAR
CSR_CMD_CLR_BAD_PAR
CSR_CMD_CLR_R2PCI_INT

Definition at line 199 of file qlge.h.

anonymous enum

Enumerator:

CFG_LRQ
CFG_DRQ
CFG_LR
CFG_DR
CFG_LE
CFG_LCQ
CFG_DCQ
CFG_Q_SHIFT
CFG_Q_MASK

Definition at line 224 of file qlge.h.

anonymous enum

Enumerator:

STS_FE
STS_PI
STS_PL0
STS_PL1
STS_PI0
STS_PI1
STS_FUNC_ID_MASK
STS_FUNC_ID_SHIFT
STS_F0E
STS_F1E
STS_F2E
STS_F3E
STS_NFE

Definition at line 239 of file qlge.h.

anonymous enum

Enumerator:

INTR_EN_INTR_MASK
INTR_EN_TYPE_MASK
INTR_EN_TYPE_ENABLE
INTR_EN_TYPE_DISABLE
INTR_EN_TYPE_READ
INTR_EN_IHD
INTR_EN_IHD_MASK
INTR_EN_EI
INTR_EN_EN

Definition at line 258 of file qlge.h.

anonymous enum

Enumerator:

INTR_MASK_PI
INTR_MASK_HL0
INTR_MASK_LH0
INTR_MASK_HL1
INTR_MASK_LH1
INTR_MASK_SE
INTR_MASK_LSC
INTR_MASK_MC
INTR_MASK_LINK_IRQS

Definition at line 273 of file qlge.h.

anonymous enum

Enumerator:

REV_ID_MASK
REV_ID_NICROLL_SHIFT
REV_ID_NICREV_SHIFT
REV_ID_XGROLL_SHIFT
REV_ID_XGREV_SHIFT
REV_ID_CHIPREV_SHIFT

Definition at line 288 of file qlge.h.

anonymous enum

Enumerator:

FRC_ECC_ERR_VW
FRC_ECC_ERR_VB
FRC_ECC_ERR_NI
FRC_ECC_ERR_NO
FRC_ECC_PFE_SHIFT
FRC_ECC_ERR_DO
FRC_ECC_P14

Definition at line 300 of file qlge.h.

anonymous enum

Enumerator:

ERR_STS_NOF
ERR_STS_NIF
ERR_STS_DRP
ERR_STS_XGP
ERR_STS_FOU
ERR_STS_FOC
ERR_STS_FOF
ERR_STS_FIU
ERR_STS_FIC
ERR_STS_FIF
ERR_STS_MOF
ERR_STS_TA
ERR_STS_MA
ERR_STS_MPE
ERR_STS_SCE
ERR_STS_STE
ERR_STS_FOW
ERR_STS_UE
ERR_STS_MCH
ERR_STS_LOC_SHIFT

Definition at line 313 of file qlge.h.

anonymous enum

Enumerator:

RAM_DBG_ADDR_FW
RAM_DBG_ADDR_FR

Definition at line 339 of file qlge.h.

anonymous enum

Enumerator:

SEM_CLEAR
SEM_SET
SEM_FORCE
SEM_XGMAC0_SHIFT
SEM_XGMAC1_SHIFT
SEM_ICB_SHIFT
SEM_MAC_ADDR_SHIFT
SEM_FLASH_SHIFT
SEM_PROBE_SHIFT
SEM_RT_IDX_SHIFT
SEM_PROC_REG_SHIFT
SEM_XGMAC0_MASK
SEM_XGMAC1_MASK
SEM_ICB_MASK
SEM_MAC_ADDR_MASK
SEM_FLASH_MASK
SEM_PROBE_MASK
SEM_RT_IDX_MASK
SEM_PROC_REG_MASK

Definition at line 347 of file qlge.h.

anonymous enum

Enumerator:

XGMAC_ADDR_RDY
XGMAC_ADDR_R
XGMAC_ADDR_XME
PAUSE_SRC_LO
PAUSE_SRC_HI
GLOBAL_CFG
GLOBAL_CFG_RESET
GLOBAL_CFG_JUMBO
GLOBAL_CFG_TX_STAT_EN
GLOBAL_CFG_RX_STAT_EN
TX_CFG
TX_CFG_RESET
TX_CFG_EN
TX_CFG_PREAM
RX_CFG
RX_CFG_RESET
RX_CFG_EN
RX_CFG_PREAM
FLOW_CTL
PAUSE_OPCODE
PAUSE_TIMER
PAUSE_FRM_DEST_LO
PAUSE_FRM_DEST_HI
MAC_TX_PARAMS
MAC_TX_PARAMS_JUMBO
MAC_TX_PARAMS_SIZE_SHIFT
MAC_RX_PARAMS
MAC_SYS_INT
MAC_SYS_INT_MASK
MAC_MGMT_INT
MAC_MGMT_IN_MASK
EXT_ARB_MODE
TX_PKTS
TX_BYTES
TX_MCAST_PKTS
TX_BCAST_PKTS
TX_UCAST_PKTS
TX_CTL_PKTS
TX_PAUSE_PKTS
TX_64_PKT
TX_65_TO_127_PKT
TX_128_TO_255_PKT
TX_256_511_PKT
TX_512_TO_1023_PKT
TX_1024_TO_1518_PKT
TX_1519_TO_MAX_PKT
TX_UNDERSIZE_PKT
TX_OVERSIZE_PKT
RX_HALF_FULL_DET
TX_HALF_FULL_DET
RX_OVERFLOW_DET
TX_OVERFLOW_DET
RX_HALF_FULL_MASK
TX_HALF_FULL_MASK
RX_OVERFLOW_MASK
TX_OVERFLOW_MASK
STAT_CNT_CTL
STAT_CNT_CTL_CLEAR_TX
STAT_CNT_CTL_CLEAR_RX
AUX_RX_HALF_FULL_DET
AUX_TX_HALF_FULL_DET
AUX_RX_OVERFLOW_DET
AUX_TX_OVERFLOW_DET
AUX_RX_HALF_FULL_MASK
AUX_TX_HALF_FULL_MASK
AUX_RX_OVERFLOW_MASK
AUX_TX_OVERFLOW_MASK
RX_BYTES
RX_BYTES_OK
RX_PKTS
RX_PKTS_OK
RX_BCAST_PKTS
RX_MCAST_PKTS
RX_UCAST_PKTS
RX_UNDERSIZE_PKTS
RX_OVERSIZE_PKTS
RX_JABBER_PKTS
RX_UNDERSIZE_FCERR_PKTS
RX_DROP_EVENTS
RX_FCERR_PKTS
RX_ALIGN_ERR
RX_SYMBOL_ERR
RX_MAC_ERR
RX_CTL_PKTS
RX_PAUSE_PKTS
RX_64_PKTS
RX_65_TO_127_PKTS
RX_128_255_PKTS
RX_256_511_PKTS
RX_512_TO_1023_PKTS
RX_1024_TO_1518_PKTS
RX_1519_TO_MAX_PKTS
RX_LEN_ERR_PKTS
MDIO_TX_DATA
MDIO_RX_DATA
MDIO_CMD
MDIO_PHY_ADDR
MDIO_PORT
MDIO_STATUS
XGMAC_REGISTER_END

Definition at line 376 of file qlge.h.

anonymous enum

Enumerator:

ETS_QUEUE_SHIFT
ETS_REF
ETS_RS
ETS_P
ETS_FC_COS_SHIFT

Definition at line 493 of file qlge.h.

anonymous enum

Enumerator:

FLASH_ADDR_RDY
FLASH_ADDR_R
FLASH_ADDR_ERR

Definition at line 504 of file qlge.h.

anonymous enum

Enumerator:

CQ_STOP_QUEUE_MASK
CQ_STOP_TYPE_MASK
CQ_STOP_TYPE_START
CQ_STOP_TYPE_STOP
CQ_STOP_TYPE_READ
CQ_STOP_EN

Definition at line 513 of file qlge.h.

anonymous enum

Enumerator:

MAC_ADDR_IDX_SHIFT
MAC_ADDR_TYPE_SHIFT
MAC_ADDR_TYPE_COUNT
MAC_ADDR_TYPE_MASK
MAC_ADDR_TYPE_CAM_MAC
MAC_ADDR_TYPE_MULTI_MAC
MAC_ADDR_TYPE_VLAN
MAC_ADDR_TYPE_MULTI_FLTR
MAC_ADDR_TYPE_FC_MAC
MAC_ADDR_TYPE_MGMT_MAC
MAC_ADDR_TYPE_MGMT_VLAN
MAC_ADDR_TYPE_MGMT_V4
MAC_ADDR_TYPE_MGMT_V6
MAC_ADDR_TYPE_MGMT_TU_DP
MAC_ADDR_ADR
MAC_ADDR_RS
MAC_ADDR_E
MAC_ADDR_MR
MAC_ADDR_MW
MAX_MULTICAST_ENTRIES
MAC_ADDR_MAX_CAM_ENTRIES
MAC_ADDR_MAX_CAM_WCOUNT
MAC_ADDR_MAX_MULTICAST_ENTRIES
MAC_ADDR_MAX_MULTICAST_WCOUNT
MAC_ADDR_MAX_VLAN_ENTRIES
MAC_ADDR_MAX_VLAN_WCOUNT
MAC_ADDR_MAX_MCAST_FLTR_ENTRIES
MAC_ADDR_MAX_MCAST_FLTR_WCOUNT
MAC_ADDR_MAX_FC_MAC_ENTRIES
MAC_ADDR_MAX_FC_MAC_WCOUNT
MAC_ADDR_MAX_MGMT_MAC_ENTRIES
MAC_ADDR_MAX_MGMT_MAC_WCOUNT
MAC_ADDR_MAX_MGMT_VLAN_ENTRIES
MAC_ADDR_MAX_MGMT_VLAN_WCOUNT
MAC_ADDR_MAX_MGMT_V4_ENTRIES
MAC_ADDR_MAX_MGMT_V4_WCOUNT
MAC_ADDR_MAX_MGMT_V6_ENTRIES
MAC_ADDR_MAX_MGMT_V6_WCOUNT
MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES
MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT

Definition at line 525 of file qlge.h.

anonymous enum

Enumerator:

SPLT_HDR_EP

Definition at line 575 of file qlge.h.

anonymous enum

Enumerator:

FC_RCV_CFG_ECT
FC_RCV_CFG_DFH
FC_RCV_CFG_DVF
FC_RCV_CFG_RCE
FC_RCV_CFG_RFE
FC_RCV_CFG_TEE
FC_RCV_CFG_TCE
FC_RCV_CFG_TFE

Definition at line 582 of file qlge.h.

anonymous enum

Enumerator:

NIC_RCV_CFG_PPE
NIC_RCV_CFG_VLAN_MASK
NIC_RCV_CFG_VLAN_ALL
NIC_RCV_CFG_VLAN_MATCH_ONLY
NIC_RCV_CFG_VLAN_MATCH_AND_NON
NIC_RCV_CFG_VLAN_NONE_AND_NON
NIC_RCV_CFG_RV
NIC_RCV_CFG_DFQ_MASK
NIC_RCV_CFG_DFQ_SHIFT
NIC_RCV_CFG_DFQ

Definition at line 596 of file qlge.h.

anonymous enum

Enumerator:

MGMT_RCV_CFG_ARP
MGMT_RCV_CFG_DHC
MGMT_RCV_CFG_DHS
MGMT_RCV_CFG_NP
MGMT_RCV_CFG_I6N
MGMT_RCV_CFG_I6R
MGMT_RCV_CFG_DH6
MGMT_RCV_CFG_UD1
MGMT_RCV_CFG_UD0
MGMT_RCV_CFG_BCT
MGMT_RCV_CFG_MCT
MGMT_RCV_CFG_DM
MGMT_RCV_CFG_RM
MGMT_RCV_CFG_STL
MGMT_RCV_CFG_VLAN_MASK
MGMT_RCV_CFG_VLAN_ALL
MGMT_RCV_CFG_VLAN_MATCH_ONLY
MGMT_RCV_CFG_VLAN_MATCH_AND_NON
MGMT_RCV_CFG_VLAN_NONE_AND_NON

Definition at line 612 of file qlge.h.

anonymous enum

Enumerator:

RT_IDX_IDX_SHIFT
RT_IDX_TYPE_MASK
RT_IDX_TYPE_SHIFT
RT_IDX_TYPE_RT
RT_IDX_TYPE_RT_INV
RT_IDX_TYPE_NICQ
RT_IDX_TYPE_NICQ_INV
RT_IDX_DST_MASK
RT_IDX_DST_RSS
RT_IDX_DST_CAM_Q
RT_IDX_DST_COS_Q
RT_IDX_DST_DFLT_Q
RT_IDX_DST_DEST_Q
RT_IDX_RS
RT_IDX_E
RT_IDX_MR
RT_IDX_MW
RT_IDX_BCAST
RT_IDX_MCAST
RT_IDX_MCAST_MATCH
RT_IDX_MCAST_REG_MATCH
RT_IDX_MCAST_HASH_MATCH
RT_IDX_FC_MACH
RT_IDX_ETH_FCOE
RT_IDX_CAM_HIT
RT_IDX_CAM_BIT0
RT_IDX_CAM_BIT1
RT_IDX_VLAN_TAG
RT_IDX_VLAN_MATCH
RT_IDX_VLAN_FILTER
RT_IDX_ETH_SKIP1
RT_IDX_ETH_SKIP2
RT_IDX_BCAST_MCAST_MATCH
RT_IDX_802_3
RT_IDX_LLDP
RT_IDX_UNUSED018
RT_IDX_UNUSED019
RT_IDX_UNUSED20
RT_IDX_UNUSED21
RT_IDX_ERR
RT_IDX_VALID
RT_IDX_TU_CSUM_ERR
RT_IDX_IP_CSUM_ERR
RT_IDX_MAC_ERR
RT_IDX_RSS_TCP6
RT_IDX_RSS_TCP4
RT_IDX_RSS_IPV6
RT_IDX_RSS_IPV4
RT_IDX_RSS_MATCH
RT_IDX_ALL_ERR_SLOT
RT_IDX_MAC_ERR_SLOT
RT_IDX_IP_CSUM_ERR_SLOT
RT_IDX_TCP_UDP_CSUM_ERR_SLOT
RT_IDX_BCAST_SLOT
RT_IDX_MCAST_MATCH_SLOT
RT_IDX_ALLMULTI_SLOT
RT_IDX_UNUSED6_SLOT
RT_IDX_UNUSED7_SLOT
RT_IDX_RSS_MATCH_SLOT
RT_IDX_RSS_IPV4_SLOT
RT_IDX_RSS_IPV6_SLOT
RT_IDX_RSS_TCP4_SLOT
RT_IDX_RSS_TCP6_SLOT
RT_IDX_CAM_HIT_SLOT
RT_IDX_UNUSED013
RT_IDX_UNUSED014
RT_IDX_PROMISCUOUS_SLOT
RT_IDX_MAX_RT_SLOTS
RT_IDX_MAX_NIC_SLOTS

Definition at line 637 of file qlge.h.

anonymous enum

Enumerator:

XG_SERDES_ADDR_RDY
XG_SERDES_ADDR_R
XG_SERDES_ADDR_STS
XG_SERDES_ADDR_XFI1_PWR_UP
XG_SERDES_ADDR_XFI2_PWR_UP
XG_SERDES_ADDR_XAUI_PWR_DOWN
XG_SERDES_XAUI_AN_START
XG_SERDES_XAUI_AN_END
XG_SERDES_XAUI_HSS_PCS_START
XG_SERDES_XAUI_HSS_PCS_END
XG_SERDES_XFI_AN_START
XG_SERDES_XFI_AN_END
XG_SERDES_XFI_TRAIN_START
XG_SERDES_XFI_TRAIN_END
XG_SERDES_XFI_HSS_PCS_START
XG_SERDES_XFI_HSS_PCS_END
XG_SERDES_XFI_HSS_TX_START
XG_SERDES_XFI_HSS_TX_END
XG_SERDES_XFI_HSS_RX_START
XG_SERDES_XFI_HSS_RX_END
XG_SERDES_XFI_HSS_PLL_START
XG_SERDES_XFI_HSS_PLL_END

Definition at line 716 of file qlge.h.

anonymous enum

Enumerator:

PRB_MX_ADDR_ARE
PRB_MX_ADDR_UP
PRB_MX_ADDR_SWP
PRB_MX_ADDR_MAX_MODS
PRB_MX_ADDR_MOD_SEL_SHIFT
PRB_MX_ADDR_MOD_SEL_TBD
PRB_MX_ADDR_MOD_SEL_IDE1
PRB_MX_ADDR_MOD_SEL_IDE2
PRB_MX_ADDR_MOD_SEL_FRB
PRB_MX_ADDR_MOD_SEL_ODE1
PRB_MX_ADDR_MOD_SEL_ODE2
PRB_MX_ADDR_MOD_SEL_DA1
PRB_MX_ADDR_MOD_SEL_DA2
PRB_MX_ADDR_MOD_SEL_IMP1
PRB_MX_ADDR_MOD_SEL_IMP2
PRB_MX_ADDR_MOD_SEL_OMP1
PRB_MX_ADDR_MOD_SEL_OMP2
PRB_MX_ADDR_MOD_SEL_ORS1
PRB_MX_ADDR_MOD_SEL_ORS2
PRB_MX_ADDR_MOD_SEL_REG
PRB_MX_ADDR_MOD_SEL_MAC1
PRB_MX_ADDR_MOD_SEL_MAC2
PRB_MX_ADDR_MOD_SEL_VQM1
PRB_MX_ADDR_MOD_SEL_VQM2
PRB_MX_ADDR_MOD_SEL_MOP
PRB_MX_ADDR_VALID_SYS_MOD
PRB_MX_ADDR_VALID_PCI_MOD
PRB_MX_ADDR_VALID_XGM_MOD
PRB_MX_ADDR_VALID_FC_MOD
PRB_MX_ADDR_VALID_TOTAL
PRB_MX_ADDR_CLOCK_SHIFT
PRB_MX_ADDR_SYS_CLOCK
PRB_MX_ADDR_PCI_CLOCK
PRB_MX_ADDR_FC_CLOCK
PRB_MX_ADDR_XGM_CLOCK
PRB_MX_ADDR_MAX_MUX

Definition at line 747 of file qlge.h.

anonymous enum

Enumerator:

PROC_ADDR
PROC_DATA
SYS
RST_FO
FSC
CSR
LED
ICB_RID
ICB_L
ICB_H
CFG
BIOS_ADDR
STS
INTR_EN
INTR_MASK
ISR1
ISR2
ISR3
ISR4
REV_ID
FRC_ECC_ERR
ERR_STS
RAM_DBG_ADDR
RAM_DBG_DATA
ECC_ERR_CNT
SEM
GPIO_1
GPIO_2
GPIO_3
RSVD2
XGMAC_ADDR
XGMAC_DATA
NIC_ETS
CNA_ETS
FLASH_ADDR
FLASH_DATA
CQ_STOP
PAGE_TBL_RID
WQ_PAGE_TBL_LO
WQ_PAGE_TBL_HI
CQ_PAGE_TBL_LO
CQ_PAGE_TBL_HI
MAC_ADDR_IDX
MAC_ADDR_DATA
COS_DFLT_CQ1
COS_DFLT_CQ2
ETYPE_SKIP1
ETYPE_SKIP2
SPLT_HDR
FC_PAUSE_THRES
NIC_PAUSE_THRES
FC_ETHERTYPE
FC_RCV_CFG
NIC_RCV_CFG
FC_COS_TAGS
NIC_COS_TAGS
MGMT_RCV_CFG
RT_IDX
RT_DATA
RSVD7
XG_SERDES_ADDR
XG_SERDES_DATA
PRB_MX_ADDR
PRB_MX_DATA

Definition at line 797 of file qlge.h.

anonymous enum

Enumerator:

CAM_OUT_ROUTE_FC
CAM_OUT_ROUTE_NIC
CAM_OUT_FUNC_SHIFT
CAM_OUT_RV
CAM_OUT_SH
CAM_OUT_CQ_ID_SHIFT

Definition at line 882 of file qlge.h.

anonymous enum

Enumerator:

AEN_SYS_ERR
AEN_LINK_UP
AEN_LINK_DOWN
AEN_IDC_CMPLT
AEN_IDC_REQ
AEN_IDC_EXT
AEN_DCBX_CHG
AEN_AEN_LOST
AEN_AEN_SFP_IN
AEN_AEN_SFP_OUT
AEN_FW_INIT_DONE
AEN_FW_INIT_FAIL
MB_CMD_NOP
MB_CMD_EX_FW
MB_CMD_MB_TEST
MB_CMD_CSUM_TEST
MB_CMD_ABOUT_FW
MB_CMD_COPY_RISC_RAM
MB_CMD_LOAD_RISC_RAM
MB_CMD_DUMP_RISC_RAM
MB_CMD_WRITE_RAM
MB_CMD_INIT_RISC_RAM
MB_CMD_READ_RAM
MB_CMD_STOP_FW
MB_CMD_MAKE_SYS_ERR
MB_CMD_WRITE_SFP
MB_CMD_READ_SFP
MB_CMD_INIT_FW
MB_CMD_GET_IFCB
MB_CMD_GET_FW_STATE
MB_CMD_IDC_REQ
MB_CMD_IDC_ACK
MB_CMD_SET_WOL_MODE
MB_WOL_DISABLE
MB_WOL_MAGIC_PKT
MB_WOL_FLTR
MB_WOL_UCAST
MB_WOL_MCAST
MB_WOL_BCAST
MB_WOL_LINK_UP
MB_WOL_LINK_DOWN
MB_WOL_MODE_ON
MB_CMD_SET_WOL_FLTR
MB_CMD_CLEAR_WOL_FLTR
MB_CMD_SET_WOL_MAGIC
MB_CMD_CLEAR_WOL_MAGIC
MB_CMD_SET_WOL_IMMED
MB_CMD_PORT_RESET
MB_CMD_SET_PORT_CFG
MB_CMD_GET_PORT_CFG
MB_CMD_GET_LINK_STS
MB_CMD_SET_LED_CFG
QL_LED_BLINK
MB_CMD_GET_LED_CFG
MB_CMD_SET_MGMNT_TFK_CTL
MB_SET_MPI_TFK_STOP
MB_SET_MPI_TFK_RESUME
MB_CMD_GET_MGMNT_TFK_CTL
MB_GET_MPI_TFK_STOPPED
MB_GET_MPI_TFK_FIFO_EMPTY
MB_CMD_IOP_NONE
MB_CMD_IOP_PREP_UPDATE_MPI
MB_CMD_IOP_COMP_UPDATE_MPI
MB_CMD_IOP_PREP_LINK_DOWN
MB_CMD_IOP_DVR_START
MB_CMD_IOP_FLASH_ACC
MB_CMD_IOP_RESTART_MPI
MB_CMD_IOP_CORE_DUMP_MPI
MB_CMD_STS_GOOD
MB_CMD_STS_INTRMDT
MB_CMD_STS_INVLD_CMD
MB_CMD_STS_XFC_ERR
MB_CMD_STS_CSUM_ERR
MB_CMD_STS_ERR
MB_CMD_STS_PARAM_ERR

Definition at line 894 of file qlge.h.

anonymous enum

Enumerator:

DEFAULT_Q
TX_Q
RX_Q

Definition at line 1412 of file qlge.h.

anonymous enum

Enumerator:

MPI_CORE_REGS_ADDR
MPI_CORE_REGS_CNT
MPI_CORE_SH_REGS_CNT
TEST_REGS_ADDR
TEST_REGS_CNT
RMII_REGS_ADDR
RMII_REGS_CNT
FCMAC1_REGS_ADDR
FCMAC2_REGS_ADDR
FCMAC_REGS_CNT
FC1_MBX_REGS_ADDR
FC2_MBX_REGS_ADDR
FC_MBX_REGS_CNT
IDE_REGS_ADDR
IDE_REGS_CNT
NIC1_MBX_REGS_ADDR
NIC2_MBX_REGS_ADDR
NIC_MBX_REGS_CNT
SMBUS_REGS_ADDR
SMBUS_REGS_CNT
I2C_REGS_ADDR
I2C_REGS_CNT
MEMC_REGS_ADDR
MEMC_REGS_CNT
PBUS_REGS_ADDR
PBUS_REGS_CNT
MDE_REGS_ADDR
MDE_REGS_CNT
CODE_RAM_ADDR
CODE_RAM_CNT
MEMC_RAM_ADDR
MEMC_RAM_CNT

Definition at line 1571 of file qlge.h.

anonymous enum

Enumerator:

CORE_SEG_NUM
TEST_LOGIC_SEG_NUM
RMII_SEG_NUM
FCMAC1_SEG_NUM
FCMAC2_SEG_NUM
FC1_MBOX_SEG_NUM
IDE_SEG_NUM
NIC1_MBOX_SEG_NUM
SMBUS_SEG_NUM
FC2_MBOX_SEG_NUM
NIC2_MBOX_SEG_NUM
I2C_SEG_NUM
MEMC_SEG_NUM
PBUS_SEG_NUM
MDE_SEG_NUM
NIC1_CONTROL_SEG_NUM
NIC2_CONTROL_SEG_NUM
NIC1_XGMAC_SEG_NUM
NIC2_XGMAC_SEG_NUM
WCS_RAM_SEG_NUM
MEMC_RAM_SEG_NUM
XAUI_AN_SEG_NUM
XAUI_HSS_PCS_SEG_NUM
XFI_AN_SEG_NUM
XFI_TRAIN_SEG_NUM
XFI_HSS_PCS_SEG_NUM
XFI_HSS_TX_SEG_NUM
XFI_HSS_RX_SEG_NUM
XFI_HSS_PLL_SEG_NUM
MISC_NIC_INFO_SEG_NUM
INTR_STATES_SEG_NUM
CAM_ENTRIES_SEG_NUM
ROUTING_WORDS_SEG_NUM
ETS_SEG_NUM
PROBE_DUMP_SEG_NUM
ROUTING_INDEX_SEG_NUM
MAC_PROTOCOL_SEG_NUM
XAUI2_AN_SEG_NUM
XAUI2_HSS_PCS_SEG_NUM
XFI2_AN_SEG_NUM
XFI2_TRAIN_SEG_NUM
XFI2_HSS_PCS_SEG_NUM
XFI2_HSS_TX_SEG_NUM
XFI2_HSS_RX_SEG_NUM
XFI2_HSS_PLL_SEG_NUM
SEM_REGS_SEG_NUM

Definition at line 1626 of file qlge.h.

anonymous enum

Enumerator:

QL_ADAPTER_UP
QL_LEGACY_ENABLED
QL_MSI_ENABLED
QL_MSIX_ENABLED
QL_DMA64
QL_PROMISCUOUS
QL_ALLMULTI
QL_PORT_CFG
QL_CAM_RT_SET
QL_SELFTEST
QL_LB_LINK_UP
QL_FRC_COREDUMP
QL_EEH_FATAL
QL_ASIC_RECOVERY

Definition at line 1994 of file qlge.h.

anonymous enum

Enumerator:

STS_LOOPBACK_MASK
STS_LOOPBACK_PCS
STS_LOOPBACK_HSS
STS_LOOPBACK_EXT
STS_PAUSE_MASK
STS_PAUSE_STD
STS_PAUSE_PRI
STS_SPEED_MASK
STS_SPEED_100Mb
STS_SPEED_1Gb
STS_SPEED_10Gb
STS_LINK_TYPE_MASK
STS_LINK_TYPE_XFI
STS_LINK_TYPE_XAUI
STS_LINK_TYPE_XFI_BP
STS_LINK_TYPE_XAUI_BP
STS_LINK_TYPE_10GBASET

Definition at line 2012 of file qlge.h.

anonymous enum

Enumerator:

CFG_JUMBO_FRAME_SIZE
CFG_PAUSE_MASK
CFG_PAUSE_STD
CFG_PAUSE_PRI
CFG_DCBX
CFG_LOOPBACK_MASK
CFG_LOOPBACK_PCS
CFG_LOOPBACK_HSS
CFG_LOOPBACK_EXT
CFG_DEFAULT_MAX_FRAME_SIZE

Definition at line 2033 of file qlge.h.

Function Documentation

int ql_cam_route_initialize ( struct ql_adapter * qdev )

Definition at line 3653 of file qlge_main.c.

void ql_check_lb_frame	(	struct ql_adapter *	,
		struct sk_buff *
	)

Definition at line 515 of file qlge_ethtool.c.

int ql_clean_lb_rx_ring	(	struct rx_ring *	rx_ring,
		int	budget
	)

Definition at line 4727 of file qlge_main.c.

int ql_core_dump	(	struct ql_adapter *	qdev,
		struct ql_mpi_coredump *	mpi_coredump
	)

Definition at line 737 of file qlge_dbg.c.

int ql_dump_risc_ram_area	(	struct ql_adapter *	qdev,
		void *	buf,
		u32	ram_addr,
		int	word_count
	)

Definition at line 784 of file qlge_mpi.c.

u32 ql_enable_completion_interrupt	(	struct ql_adapter *	qdev,
		u32	intr
	)

Definition at line 633 of file qlge_main.c.

void ql_gen_reg_dump	(	struct ql_adapter *	qdev,
		struct ql_reg_dump *	mpi_coredump
	)

Definition at line 1245 of file qlge_dbg.c.

void ql_get_dump	(	struct ql_adapter *	qdev,
		void *	buff
	)

Definition at line 1322 of file qlge_dbg.c.

int ql_get_mac_addr_reg	(	struct ql_adapter *	qdev,
		u32	type,
		u16	index,
		u32 *	value
	)

Definition at line 262 of file qlge_main.c.

int ql_get_routing_reg	(	struct ql_adapter *	qdev,
		u32	index,
		u32 *	value
	)

Definition at line 496 of file qlge_main.c.

int ql_hard_reset_mpi_risc ( struct ql_adapter * qdev )

Definition at line 33 of file qlge_mpi.c.

netdev_tx_t ql_lb_send	(	struct sk_buff *	skb,
		struct net_device *	ndev
	)

Definition at line 4722 of file qlge_main.c.

void ql_link_off ( struct ql_adapter * qdev )

Definition at line 486 of file qlge_main.c.

void ql_link_on ( struct ql_adapter * qdev )

Definition at line 479 of file qlge_main.c.

int ql_mb_about_fw ( struct ql_adapter * qdev )

Definition at line 615 of file qlge_mpi.c.

int ql_mb_get_fw_state ( struct ql_adapter * qdev )

Definition at line 647 of file qlge_mpi.c.

int ql_mb_get_led_cfg ( struct ql_adapter * qdev )

Definition at line 982 of file qlge_mpi.c.

int ql_mb_get_port_cfg ( struct ql_adapter * qdev )

Definition at line 809 of file qlge_mpi.c.

int ql_mb_set_led_cfg	(	struct ql_adapter *	qdev,
		u32	led_config
	)

Definition at line 954 of file qlge_mpi.c.

int ql_mb_set_mgmnt_traffic_ctl	(	struct ql_adapter *	qdev,
		u32	control
	)

Definition at line 1009 of file qlge_mpi.c.

int ql_mb_set_port_cfg ( struct ql_adapter * qdev )

Definition at line 718 of file qlge_mpi.c.

int ql_mb_wol_mode	(	struct ql_adapter *	qdev,
		u32	wol
	)

Definition at line 839 of file qlge_mpi.c.

int ql_mb_wol_set_magic	(	struct ql_adapter *	qdev,
		u32	enable_wol
	)

Definition at line 865 of file qlge_mpi.c.

void ql_mpi_core_to_log ( struct work_struct * work )

Definition at line 1345 of file qlge_dbg.c.

void ql_mpi_idc_work ( struct work_struct * work )

Definition at line 1159 of file qlge_mpi.c.

void ql_mpi_port_cfg_work ( struct work_struct * work )

Definition at line 1119 of file qlge_mpi.c.

void ql_mpi_reset_work ( struct work_struct * work )

Definition at line 1262 of file qlge_mpi.c.

void ql_mpi_work ( struct work_struct * work )

Definition at line 1233 of file qlge_mpi.c.

int ql_own_firmware ( struct ql_adapter * qdev )

Definition at line 102 of file qlge_mpi.c.

int ql_pause_mpi_risc ( struct ql_adapter * qdev )

Definition at line 16 of file qlge_mpi.c.

void ql_queue_asic_error ( struct ql_adapter * qdev )

Definition at line 2094 of file qlge_main.c.

void ql_queue_fw_error ( struct ql_adapter * qdev )

Definition at line 2088 of file qlge_main.c.

int ql_read_mpi_reg	(	struct ql_adapter *	qdev,
		u32	reg,
		u32 *	data
	)

Definition at line 52 of file qlge_mpi.c.

int ql_read_xgmac_reg	(	struct ql_adapter *	qdev,
		u32	reg,
		u32 *	data
	)

Definition at line 882 of file qlge_main.c.

int ql_read_xgmac_reg64	(	struct ql_adapter *	qdev,
		u32	reg,
		u64 *	data
	)

Definition at line 904 of file qlge_main.c.

int ql_sem_spinlock	(	struct ql_adapter *	qdev,
		u32	sem_mask
	)

Definition at line 144 of file qlge_main.c.

void ql_sem_unlock	(	struct ql_adapter *	qdev,
		u32	sem_mask
	)

Definition at line 155 of file qlge_main.c.

void ql_set_ethtool_ops ( struct net_device * ndev )

int ql_soft_reset_mpi_risc ( struct ql_adapter * qdev )

Definition at line 90 of file qlge_mpi.c.

int ql_unpause_mpi_risc ( struct ql_adapter * qdev )

Definition at line 3 of file qlge_mpi.c.

int ql_wait_fifo_empty ( struct ql_adapter * qdev )

Definition at line 1081 of file qlge_mpi.c.

int ql_wait_reg_rdy	(	struct ql_adapter *	qdev,
		u32	reg,
		u32	bit,
		u32	ebit
	)

Definition at line 166 of file qlge_main.c.

int ql_write_cfg	(	struct ql_adapter *	qdev,
		void *	ptr,
		int	size,
		u32	bit,
		u16	q_id
	)

Definition at line 214 of file qlge_main.c.

int ql_write_mpi_reg	(	struct ql_adapter *	qdev,
		u32	reg,
		u32	data
	)

Definition at line 71 of file qlge_mpi.c.

Variable Documentation

struct ricb __packed

char qlge_driver_name[]

Definition at line 47 of file qlge_main.c.

const char qlge_driver_version[]

Definition at line 48 of file qlge_main.c.

struct ethtool_ops qlge_ethtool_ops

Definition at line 712 of file qlge_ethtool.c.

Data Structures

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation