dtc.c File Reference

#include <linux/module.h>
#include <linux/signal.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/stat.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include "scsi.h"
#include <scsi/scsi_host.h>
#include "dtc.h"
#include "NCR5380.h"
#include "NCR5380.c"
#include "scsi_module.c"

Go to the source code of this file.

Data Structures
struct	override
struct	base
struct	signature

Macros
#define	AUTOSENSE
#define	PSEUDO_DMA
#define	DONT_USE_INTR
#define	UNSAFE   /* Leave interrupts enabled during pseudo-dma I/O */
#define	xNDEBUG
#define	DMA_WORKS_RIGHT
#define	rtrc(i)   {}
#define	AUTOPROBE_IRQ
#define	DTC_PUBLIC_RELEASE   2
#define	DTC_CONTROL_REG   0x100 /* rw */
#define	D_CR_ACCESS   0x80 /* ro set=can access 3280 registers */
#define	CSR_DIR_READ   0x40 /* rw direction, 1 = read 0 = write */
#define	CSR_RESET   0x80 /* wo Resets 53c400 */
#define	CSR_5380_REG   0x80 /* ro 5380 registers can be accessed */
#define	CSR_TRANS_DIR   0x40 /* rw Data transfer direction */
#define	CSR_SCSI_BUFF_INTR   0x20 /* rw Enable int on transfer ready */
#define	CSR_5380_INTR   0x10 /* rw Enable 5380 interrupts */
#define	CSR_SHARED_INTR   0x08 /* rw Interrupt sharing */
#define	CSR_HOST_BUF_NOT_RDY   0x04 /* ro Host buffer not ready */
#define	CSR_SCSI_BUF_RDY   0x02 /* ro SCSI buffer ready */
#define	CSR_GATED_5380_IRQ   0x01 /* ro Last block xferred */
#define	CSR_INT_BASE   (CSR_SCSI_BUFF_INTR | CSR_5380_INTR)
#define	DTC_BLK_CNT
#define	D_CR_ACCESS   0x80 /* ro set=can access 3280 registers */
#define	DTC_SWITCH_REG   0x3982 /* ro - DIP switches */
#define	DTC_RESUME_XFER
#define	DTC_5380_OFFSET   0x3880 /* 8 registers here, see NCR5380.h */
#define	DTC_DATA_BUF   0x3900 /* rw 128 bytes long */
#define	NO_OVERRIDES   ARRAY_SIZE(overrides)
#define	NO_BASES   ARRAY_SIZE(bases)
#define	NO_SIGNATURES   ARRAY_SIZE(signatures)

Functions
	MODULE_LICENSE ("GPL")

Macro Definition Documentation

#define AUTOPROBE_IRQ

Definition at line 87 of file dtc.c.

#define AUTOSENSE

Definition at line 2 of file dtc.c.

#define CSR_5380_INTR   0x10 /* rw Enable 5380 interrupts */

Definition at line 109 of file dtc.c.

#define CSR_5380_REG   0x80 /* ro 5380 registers can be accessed */

Definition at line 106 of file dtc.c.

#define CSR_DIR_READ   0x40 /* rw direction, 1 = read 0 = write */

Definition at line 103 of file dtc.c.

#define CSR_GATED_5380_IRQ   0x01 /* ro Last block xferred */

Definition at line 113 of file dtc.c.

#define CSR_HOST_BUF_NOT_RDY   0x04 /* ro Host buffer not ready */

Definition at line 111 of file dtc.c.

#define CSR_INT_BASE   (CSR_SCSI_BUFF_INTR | CSR_5380_INTR)

Definition at line 114 of file dtc.c.

#define CSR_RESET   0x80 /* wo Resets 53c400 */

Definition at line 105 of file dtc.c.

#define CSR_SCSI_BUF_RDY   0x02 /* ro SCSI buffer ready */

Definition at line 112 of file dtc.c.

#define CSR_SCSI_BUFF_INTR   0x20 /* rw Enable int on transfer ready */

Definition at line 108 of file dtc.c.

#define CSR_SHARED_INTR   0x08 /* rw Interrupt sharing */

Definition at line 110 of file dtc.c.

#define CSR_TRANS_DIR   0x40 /* rw Data transfer direction */

Definition at line 107 of file dtc.c.

#define D_CR_ACCESS   0x80 /* ro set=can access 3280 registers */

Definition at line 120 of file dtc.c.

#define D_CR_ACCESS   0x80 /* ro set=can access 3280 registers */

Definition at line 120 of file dtc.c.

#define DMA_WORKS_RIGHT

Definition at line 8 of file dtc.c.

#define DONT_USE_INTR

Definition at line 4 of file dtc.c.

#define DTC_5380_OFFSET   0x3880 /* 8 registers here, see NCR5380.h */

Definition at line 125 of file dtc.c.

#define DTC_BLK_CNT

Value:

0x101   /* rw 
                     * # of 128-byte blocks to transfer */

Definition at line 117 of file dtc.c.

#define DTC_CONTROL_REG   0x100 /* rw */

Definition at line 101 of file dtc.c.

#define DTC_DATA_BUF   0x3900 /* rw 128 bytes long */

!!! for dtc, it's a 128 byte buffer at 3900 !!!

Definition at line 128 of file dtc.c.

#define DTC_PUBLIC_RELEASE   2

Definition at line 91 of file dtc.c.

#define DTC_RESUME_XFER

Value:

0x3982  /* wo - resume data xfer 
                     * after disconnect/reconnect*/

Definition at line 123 of file dtc.c.

#define DTC_SWITCH_REG   0x3982 /* ro - DIP switches */

Definition at line 122 of file dtc.c.

#define NO_BASES   ARRAY_SIZE(bases)

Definition at line 154 of file dtc.c.

#define NO_OVERRIDES   ARRAY_SIZE(overrides)

Definition at line 142 of file dtc.c.

#define NO_SIGNATURES   ARRAY_SIZE(signatures)

Definition at line 163 of file dtc.c.

#define PSEUDO_DMA

Definition at line 3 of file dtc.c.

#define rtrc

(

i

)

{}

Definition at line 71 of file dtc.c.

#define UNSAFE   /* Leave interrupts enabled during pseudo-dma I/O */

Definition at line 5 of file dtc.c.

#define xNDEBUG

Value:

(NDEBUG_INTR+NDEBUG_RESELECTION+\
         NDEBUG_SELECTION+NDEBUG_ARBITRATION)

Definition at line 6 of file dtc.c.

Function Documentation

MODULE_LICENSE

(

"GPL"

)