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Data Structures | Macros
registers.h File Reference

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Data Structures

struct  scu_viit_entry
 
struct  scu_iit_entry
 
struct  smu_registers
 
struct  scu_sdma_registers
 
struct  scu_transport_layer_registers
 
struct  scu_link_layer_registers
 
struct  scu_sgpio_registers
 
struct  scu_viit_registers
 
struct  scu_port_task_scheduler_registers
 
struct  scu_port_task_scheduler_group_registers
 
struct  scu_afe_transceiver
 
struct  scu_afe_registers
 
struct  scu_protocol_engine_group_registers
 
struct  scu_viit_iit
 
struct  scu_zone_partition_table
 
struct  scu_completion_ram
 
struct  scu_frame_buffer_ram
 
struct  scu_scratch_ram
 
struct  noa_protocol_engine_partition
 
struct  noa_hub_partition
 
struct  noa_host_interface_partition
 
struct  transport_link_layer_pair
 
struct  scu_peg_registers
 
struct  scu_registers
 

Macros

#define SCU_VIIT_ENTRY_ID_MASK   (0xC0000000)
 
#define SCU_VIIT_ENTRY_ID_SHIFT   (30)
 
#define SCU_VIIT_ENTRY_FUNCTION_MASK   (0x0FF00000)
 
#define SCU_VIIT_ENTRY_FUNCTION_SHIFT   (20)
 
#define SCU_VIIT_ENTRY_IPPTMODE_MASK   (0x0001F800)
 
#define SCU_VIIT_ENTRY_IPPTMODE_SHIFT   (12)
 
#define SCU_VIIT_ENTRY_LPVIE_MASK   (0x00000F00)
 
#define SCU_VIIT_ENTRY_LPVIE_SHIFT   (8)
 
#define SCU_VIIT_ENTRY_STATUS_MASK   (0x000000FF)
 
#define SCU_VIIT_ENTRY_STATUS_SHIFT   (0)
 
#define SCU_VIIT_ENTRY_ID_INVALID   (0 << SCU_VIIT_ENTRY_ID_SHIFT)
 
#define SCU_VIIT_ENTRY_ID_VIIT   (1 << SCU_VIIT_ENTRY_ID_SHIFT)
 
#define SCU_VIIT_ENTRY_ID_IIT   (2 << SCU_VIIT_ENTRY_ID_SHIFT)
 
#define SCU_VIIT_ENTRY_ID_VIRT_EXP   (3 << SCU_VIIT_ENTRY_ID_SHIFT)
 
#define SCU_VIIT_IPPT_SSP_INITIATOR   (0x01 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
 
#define SCU_VIIT_IPPT_SMP_INITIATOR   (0x02 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
 
#define SCU_VIIT_IPPT_STP_INITIATOR   (0x04 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
 
#define SCU_VIIT_IPPT_INITIATOR
 
#define SCU_VIIT_STATUS_RNC_VALID   (0x01 << SCU_VIIT_ENTRY_STATUS_SHIFT)
 
#define SCU_VIIT_STATUS_ADDRESS_VALID   (0x02 << SCU_VIIT_ENTRY_STATUS_SHIFT)
 
#define SCU_VIIT_STATUS_RNI_VALID   (0x04 << SCU_VIIT_ENTRY_STATUS_SHIFT)
 
#define SCU_VIIT_STATUS_ALL_VALID
 
#define SCU_VIIT_IPPT_SMP_TARGET   (0x10 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
 
#define SCU_IIT_ENTRY_ID_MASK   (0xC0000000)
 
#define SCU_IIT_ENTRY_ID_SHIFT   (30)
 
#define SCU_IIT_ENTRY_STATUS_UPDATE_MASK   (0x20000000)
 
#define SCU_IIT_ENTRY_STATUS_UPDATE_SHIFT   (29)
 
#define SCU_IIT_ENTRY_LPI_MASK   (0x00000F00)
 
#define SCU_IIT_ENTRY_LPI_SHIFT   (8)
 
#define SCU_IIT_ENTRY_STATUS_MASK   (0x000000FF)
 
#define SCU_IIT_ENTRY_STATUS_SHIFT   (0)
 
#define SCU_IIT_ENTRY_REMOTE_TAG_MASK   (0x0000FFFF)
 
#define SCU_IIT_ENTRY_REMOTE_TAG_SHIFT   (0)
 
#define SCU_IIT_ENTRY_REMOTE_RNC_MASK   (0x0FFF0000)
 
#define SCU_IIT_ENTRY_REMOTE_RNC_SHIFT   (16)
 
#define SCU_IIT_ENTRY_ID_INVALID   (0 << SCU_IIT_ENTRY_ID_SHIFT)
 
#define SCU_IIT_ENTRY_ID_VIIT   (1 << SCU_IIT_ENTRY_ID_SHIFT)
 
#define SCU_IIT_ENTRY_ID_IIT   (2 << SCU_IIT_ENTRY_ID_SHIFT)
 
#define SCU_IIT_ENTRY_ID_VIRT_EXP   (3 << SCU_IIT_ENTRY_ID_SHIFT)
 
#define SCU_GEN_VALUE(name, value)   (((value) << name ## _SHIFT) & (name ## _MASK))
 
#define SCU_GEN_BIT(name)   SCU_GEN_VALUE(name, ((u32)1))
 
#define SCU_SET_BIT(name, reg_value)   ((reg_value) | SCU_GEN_BIT(name))
 
#define SCU_CLEAR_BIT(name, reg_value)   ((reg_value)$ ~(SCU_GEN_BIT(name)))
 
#define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT   (0)
 
#define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_MASK   (0x00000FFF)
 
#define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_SHIFT   (12)
 
#define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_MASK   (0x0000F000)
 
#define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_SHIFT   (16)
 
#define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_MASK   (0x00030000)
 
#define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_SHIFT   (18)
 
#define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_MASK   (0x00FC0000)
 
#define SMU_POST_CONTEXT_PORT_RESERVED_MASK   (0xFF000000)
 
#define SMU_PCP_GEN_VAL(name, value)   SCU_GEN_VALUE(SMU_POST_CONTEXT_PORT_ ## name, value)
 
#define SMU_INTERRUPT_STATUS_COMPLETION_SHIFT   (31)
 
#define SMU_INTERRUPT_STATUS_COMPLETION_MASK   (0x80000000)
 
#define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_SHIFT   (1)
 
#define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_MASK   (0x00000002)
 
#define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT   (0)
 
#define SMU_INTERRUPT_STATUS_QUEUE_ERROR_MASK   (0x00000001)
 
#define SMU_INTERRUPT_STATUS_RESERVED_MASK   (0x7FFFFFFC)
 
#define SMU_ISR_GEN_BIT(name)   SCU_GEN_BIT(SMU_INTERRUPT_STATUS_ ## name)
 
#define SMU_ISR_QUEUE_ERROR   SMU_ISR_GEN_BIT(QUEUE_ERROR)
 
#define SMU_ISR_QUEUE_SUSPEND   SMU_ISR_GEN_BIT(QUEUE_SUSPEND)
 
#define SMU_ISR_COMPLETION   SMU_ISR_GEN_BIT(COMPLETION)
 
#define SMU_INTERRUPT_MASK_COMPLETION_SHIFT   (31)
 
#define SMU_INTERRUPT_MASK_COMPLETION_MASK   (0x80000000)
 
#define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_SHIFT   (1)
 
#define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_MASK   (0x00000002)
 
#define SMU_INTERRUPT_MASK_QUEUE_ERROR_SHIFT   (0)
 
#define SMU_INTERRUPT_MASK_QUEUE_ERROR_MASK   (0x00000001)
 
#define SMU_INTERRUPT_MASK_RESERVED_MASK   (0x7FFFFFFC)
 
#define SMU_IMR_GEN_BIT(name)   SCU_GEN_BIT(SMU_INTERRUPT_MASK_ ## name)
 
#define SMU_IMR_QUEUE_ERROR   SMU_IMR_GEN_BIT(QUEUE_ERROR)
 
#define SMU_IMR_QUEUE_SUSPEND   SMU_IMR_GEN_BIT(QUEUE_SUSPEND)
 
#define SMU_IMR_COMPLETION   SMU_IMR_GEN_BIT(COMPLETION)
 
#define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_SHIFT   (0)
 
#define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_MASK   (0x0000001F)
 
#define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_SHIFT   (8)
 
#define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_MASK   (0x0000FF00)
 
#define SMU_INTERRUPT_COALESCING_CONTROL_RESERVED_MASK   (0xFFFF00E0)
 
#define SMU_ICC_GEN_VAL(name, value)   SCU_GEN_VALUE(SMU_INTERRUPT_COALESCING_CONTROL_ ## name, value)
 
#define SMU_TASK_CONTEXT_RANGE_START_SHIFT   (0)
 
#define SMU_TASK_CONTEXT_RANGE_START_MASK   (0x00000FFF)
 
#define SMU_TASK_CONTEXT_RANGE_ENDING_SHIFT   (16)
 
#define SMU_TASK_CONTEXT_RANGE_ENDING_MASK   (0x0FFF0000)
 
#define SMU_TASK_CONTEXT_RANGE_ENABLE_SHIFT   (31)
 
#define SMU_TASK_CONTEXT_RANGE_ENABLE_MASK   (0x80000000)
 
#define SMU_TASK_CONTEXT_RANGE_RESERVED_MASK   (0x7000F000)
 
#define SMU_TCR_GEN_VAL(name, value)   SCU_GEN_VALUE(SMU_TASK_CONTEXT_RANGE_ ## name, value)
 
#define SMU_TCR_GEN_BIT(name, value)   SCU_GEN_BIT(SMU_TASK_CONTEXT_RANGE_ ## name)
 
#define SMU_COMPLETION_QUEUE_PUT_POINTER_SHIFT   (0)
 
#define SMU_COMPLETION_QUEUE_PUT_POINTER_MASK   (0x00003FFF)
 
#define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_SHIFT   (15)
 
#define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_MASK   (0x00008000)
 
#define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_SHIFT   (16)
 
#define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_MASK   (0x03FF0000)
 
#define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_SHIFT   (26)
 
#define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_MASK   (0x04000000)
 
#define SMU_COMPLETION_QUEUE_PUT_RESERVED_MASK   (0xF8004000)
 
#define SMU_CQPR_GEN_VAL(name, value)   SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_PUT_ ## name, value)
 
#define SMU_CQPR_GEN_BIT(name)   SCU_GEN_BIT(SMU_COMPLETION_QUEUE_PUT_ ## name)
 
#define SMU_COMPLETION_QUEUE_GET_POINTER_SHIFT   (0)
 
#define SMU_COMPLETION_QUEUE_GET_POINTER_MASK   (0x00003FFF)
 
#define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT   (15)
 
#define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_MASK   (0x00008000)
 
#define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT   (16)
 
#define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK   (0x03FF0000)
 
#define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT   (26)
 
#define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_MASK   (0x04000000)
 
#define SMU_COMPLETION_QUEUE_GET_ENABLE_SHIFT   (30)
 
#define SMU_COMPLETION_QUEUE_GET_ENABLE_MASK   (0x40000000)
 
#define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_SHIFT   (31)
 
#define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_MASK   (0x80000000)
 
#define SMU_COMPLETION_QUEUE_GET_RESERVED_MASK   (0x38004000)
 
#define SMU_CQGR_GEN_VAL(name, value)   SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_GET_ ## name, value)
 
#define SMU_CQGR_GEN_BIT(name)   SCU_GEN_BIT(SMU_COMPLETION_QUEUE_GET_ ## name)
 
#define SMU_CQGR_CYCLE_BIT   SMU_CQGR_GEN_BIT(CYCLE_BIT)
 
#define SMU_CQGR_EVENT_CYCLE_BIT   SMU_CQGR_GEN_BIT(EVENT_CYCLE_BIT)
 
#define SMU_CQGR_GET_POINTER_SET(value)   SMU_CQGR_GEN_VAL(POINTER, value)
 
#define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_SHIFT   (0)
 
#define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_MASK   (0x00003FFF)
 
#define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_SHIFT   (16)
 
#define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_MASK   (0x03FF0000)
 
#define SMU_COMPLETION_QUEUE_CONTROL_RESERVED_MASK   (0xFC00C000)
 
#define SMU_CQC_GEN_VAL(name, value)   SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_CONTROL_ ## name, value)
 
#define SMU_CQC_QUEUE_LIMIT_SET(value)   SMU_CQC_GEN_VAL(QUEUE_LIMIT, value)
 
#define SMU_CQC_EVENT_LIMIT_SET(value)   SMU_CQC_GEN_VAL(EVENT_LIMIT, value)
 
#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT   (0)
 
#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK   (0x00000FFF)
 
#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT   (12)
 
#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK   (0x00007000)
 
#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT   (15)
 
#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK   (0x07FF8000)
 
#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_SHIFT   (27)
 
#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK   (0x08000000)
 
#define SMU_DEVICE_CONTEXT_CAPACITY_RESERVED_MASK   (0xF0000000)
 
#define SMU_DCC_GEN_VAL(name, value)   SCU_GEN_VALUE(SMU_DEVICE_CONTEXT_CAPACITY_ ## name, value)
 
#define SMU_DCC_GET_MAX_PEG(value)
 
#define SMU_DCC_GET_MAX_LP(value)
 
#define SMU_DCC_GET_MAX_TC(value)
 
#define SMU_DCC_GET_MAX_RNC(value)
 
#define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_SHIFT   (0)
 
#define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_MASK   (0x00000001)
 
#define SMU_CLOCK_GATING_CONTROL_XCLK_ENABLE_SHIFT   (1)
 
#define SMU_CLOCK_GATING_CONTROL_XCLK_ENABLE_MASK   (0x00000002)
 
#define SMU_CLOCK_GATING_CONTROL_TXCLK_ENABLE_SHIFT   (2)
 
#define SMU_CLOCK_GATING_CONTROL_TXCLK_ENABLE_MASK   (0x00000004)
 
#define SMU_CLOCK_GATING_CONTROL_REGCLK_ENABLE_SHIFT   (3)
 
#define SMU_CLOCK_GATING_CONTROL_REGCLK_ENABLE_MASK   (0x00000008)
 
#define SMU_CLOCK_GATING_CONTROL_IDLE_TIMEOUT_SHIFT   (16)
 
#define SMU_CLOCK_GATING_CONTROL_IDLE_TIMEOUT_MASK   (0x000F0000)
 
#define SMU_CLOCK_GATING_CONTROL_FORCE_IDLE_SHIFT   (31)
 
#define SMU_CLOCK_GATING_CONTROL_FORCE_IDLE_MASK   (0x80000000)
 
#define SMU_CLOCK_GATING_CONTROL_RESERVED_MASK   (0x7FF0FFF0)
 
#define SMU_CGUCR_GEN_VAL(name, value)   SCU_GEN_VALUE(SMU_CLOCK_GATING_CONTROL_##name, value)
 
#define SMU_CGUCR_GEN_BIT(name)   SCU_GEN_BIT(SMU_CLOCK_GATING_CONTROL_##name)
 
#define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_SHIFT   (0)
 
#define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_MASK   (0x00000001)
 
#define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_SHIFT   (1)
 
#define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_MASK   (0x00000002)
 
#define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_SHIFT   (16)
 
#define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_MASK   (0x00010000)
 
#define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_SHIFT   (17)
 
#define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_MASK   (0x00020000)
 
#define SMU_CONTROL_STATUS_RESERVED_MASK   (0xFFFCFFFC)
 
#define SMU_SMUCSR_GEN_BIT(name)   SCU_GEN_BIT(SMU_CONTROL_STATUS_ ## name)
 
#define SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED   (SMU_SMUCSR_GEN_BIT(SCHEDULER_RAM_INIT_COMPLETED))
 
#define SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED   (SMU_SMUCSR_GEN_BIT(CONTEXT_RAM_INIT_COMPLETED))
 
#define SCU_RAM_INIT_COMPLETED
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_SHIFT   (0)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_MASK   (0x00000001)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_SHIFT   (1)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_MASK   (0x00000002)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_SHIFT   (2)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_MASK   (0x00000004)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_SHIFT   (3)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_MASK   (0x00000008)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_SHIFT   (8)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_MASK   (0x00000100)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_SHIFT   (9)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_MASK   (0x00000200)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_SHIFT   (10)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_MASK   (0x00000400)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_SHIFT   (11)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_MASK   (0x00000800)
 
#define SMU_RESET_PROTOCOL_ENGINE(peg, pe)   ((1 << (pe)) << ((peg) * 8))
 
#define SMU_RESET_PEG_PROTOCOL_ENGINES(peg)
 
#define SMU_RESET_ALL_PROTOCOL_ENGINES()
 
#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_SHIFT   (16)
 
#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_MASK   (0x00010000)
 
#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_SHIFT   (17)
 
#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_MASK   (0x00020000)
 
#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_SHIFT   (18)
 
#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_MASK   (0x00040000)
 
#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_SHIFT   (19)
 
#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_MASK   (0x00080000)
 
#define SMU_RESET_WIDE_PORT_QUEUE(peg, wide_port)   ((1 << ((wide_port) / 2)) << ((peg) * 2) << 16)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG0_SHIFT   (20)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG0_MASK   (0x00100000)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG1_SHIFT   (21)
 
#define SMU_SOFTRESET_CONTROL_RESET_PEG1_MASK   (0x00200000)
 
#define SMU_SOFTRESET_CONTROL_RESET_SCU_SHIFT   (22)
 
#define SMU_SOFTRESET_CONTROL_RESET_SCU_MASK   (0x00400000)
 
#define SMU_RESET_PROTOCOL_ENGINE_GROUP(peg)
 
#define SMU_RESET_ALL_PROTOCOL_ENGINE_GROUPS()
 
#define SMU_RESET_SCU()   (0xFFFFFFFF)
 
#define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_SHIFT   (0)
 
#define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_MASK   (0x00000FFF)
 
#define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_SHIFT   (16)
 
#define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_MASK   (0x0FFF0000)
 
#define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_SHIFT   (31)
 
#define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_MASK   (0x80000000)
 
#define SMU_TASK_CONTEXT_ASSIGNMENT_RESERVED_MASK   (0x7000F000)
 
#define SMU_TCA_GEN_VAL(name, value)   SCU_GEN_VALUE(SMU_TASK_CONTEXT_ASSIGNMENT_ ## name, value)
 
#define SMU_TCA_GEN_BIT(name)   SCU_GEN_BIT(SMU_TASK_CONTEXT_ASSIGNMENT_ ## name)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_SHIFT   (0)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_MASK   (0x00000FFF)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_RESERVED_MASK   (0xFFFFF000)
 
#define SCU_UFQC_GEN_VAL(name, value)   SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_ ## name, value)
 
#define SCU_UFQC_QUEUE_SIZE_SET(value)   SCU_UFQC_GEN_VAL(QUEUE_SIZE, value)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_SHIFT   (0)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_MASK   (0x00000FFF)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_SHIFT   (12)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_MASK   (0x00001000)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_RESERVED_MASK   (0xFFFFE000)
 
#define SCU_UFQPP_GEN_VAL(name, value)   SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_ ## name, value)
 
#define SCU_UFQPP_GEN_BIT(name)   SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_ ## name)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_SHIFT   (0)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_MASK   (0x00000FFF)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_SHIFT   (12)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_MASK   (12)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_SHIFT   (31)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_MASK   (0x80000000)
 
#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_RESERVED_MASK   (0x7FFFE000)
 
#define SCU_UFQGP_GEN_VAL(name, value)   SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ ## name, value)
 
#define SCU_UFQGP_GEN_BIT(name)   SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ ## name)
 
#define SCU_UFQGP_CYCLE_BIT(value)   SCU_UFQGP_GEN_BIT(CYCLE_BIT, value)
 
#define SCU_UFQGP_GET_POINTER(value)   SCU_UFQGP_GEN_VALUE(POINTER, value)
 
#define SCU_UFQGP_ENABLE(value)   (SCU_UFQGP_GEN_BIT(ENABLE) | value)
 
#define SCU_UFQGP_DISABLE(value)   (~SCU_UFQGP_GEN_BIT(ENABLE) & value)
 
#define SCU_UFQGP_VALUE(bit, value)   (SCU_UFQGP_CYCLE_BIT(bit) | SCU_UFQGP_GET_POINTER(value))
 
#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SHIFT   (0)
 
#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_MASK   (0x0000FFFF)
 
#define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT   (16)
 
#define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK   (0x00010000)
 
#define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_SHIFT   (17)
 
#define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_MASK   (0x00020000)
 
#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_SHIFT   (18)
 
#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_MASK   (0x00040000)
 
#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_SHIFT   (19)
 
#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_MASK   (0x00080000)
 
#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_SHIFT   (20)
 
#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_MASK   (0x00100000)
 
#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_SHIFT   (21)
 
#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_MASK   (0x00200000)
 
#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_SHIFT   (22)
 
#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_MASK   (0x00400000)
 
#define SCU_PDMA_CONFIGURATION_RESERVED_MASK   (0xFF800000)
 
#define SCU_PDMACR_GEN_VALUE(name, value)   SCU_GEN_VALUE(SCU_PDMA_CONFIGURATION_ ## name, value)
 
#define SCU_PDMACR_GEN_BIT(name)   SCU_GEN_BIT(SCU_PDMA_CONFIGURATION_ ## name)
 
#define SCU_PDMACR_BE_GEN_BIT(name)   SCU_PCMACR_GEN_BIT(BIG_ENDIAN_CONTROL_ ## name)
 
#define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT   (8)
 
#define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK   (0x00000100)
 
#define SCU_CDMACR_GEN_BIT(name)   SCU_GEN_BIT(SCU_CDMA_CONFIGURATION_ ## name)
 
#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_SHIFT   (0)
 
#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_MASK   (0x000000FF)
 
#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_SHIFT   (8)
 
#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_MASK   (0x0000FF00)
 
#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_SHIFT   (16)
 
#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_MASK   (0x00FF0000)
 
#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_SHIFT   (24)
 
#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_MASK   (0xFF000000)
 
#define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_REQUIRED_MASK   (0x00000000)
 
#define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_DEFAULT_MASK   (0x7D00676F)
 
#define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_RESERVED_MASK   (0x00FF0000)
 
#define SCU_SAS_SPDTOV_GEN_VALUE(name, value)   SCU_GEN_VALUE(SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_ ## name, value)
 
#define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_SHIFT   (2)
 
#define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_MASK   (0x00000004)
 
#define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_SHIFT   (4)
 
#define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_MASK   (0x00000010)
 
#define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_SHIFT   (5)
 
#define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_MASK   (0x00000020)
 
#define SCU_LINK_STATUS_RESERVED_MASK   (0xFFFFFFCD)
 
#define SCU_SAS_LLSTA_GEN_BIT(name)   SCU_GEN_BIT(SCU_LINK_STATUS_ ## name)
 
#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_SHIFT   (0)
 
#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_MASK   (0x00007FFF)
 
#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_SHIFT   (15)
 
#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_MASK   (0x00008000)
 
#define SCU_SAS_MAWTTOV_GEN_VALUE(name, value)   SCU_GEN_VALUE(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_ ## name, value)
 
#define SCU_SAS_MAWTTOV_GEN_BIT(name)   SCU_GEN_BIT(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_ ## name)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_SHIFT   (1)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_MASK   (0x00000002)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_SHIFT   (2)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_MASK   (0x00000004)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_SHIFT   (3)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_MASK   (0x00000008)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_SHIFT   (8)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_MASK   (0x00000100)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_SHIFT   (9)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_MASK   (0x00000200)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_SHIFT   (10)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_MASK   (0x00000400)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_SHIFT   (11)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_MASK   (0x00000800)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_SHIFT   (16)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_MASK   (0x000F0000)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_SHIFT   (24)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_MASK   (0x0F000000)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_SHIFT   (28)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_MASK   (0x70000000)
 
#define SCU_SAS_TRANSMIT_IDENTIFICATION_RESERVED_MASK   (0x80F0F1F1)
 
#define SCU_SAS_TIID_GEN_VAL(name, value)   SCU_GEN_VALUE(SCU_SAS_TRANSMIT_IDENTIFICATION_ ## name, value)
 
#define SCU_SAS_TIID_GEN_BIT(name)   SCU_GEN_BIT(SCU_SAS_TRANSMIT_IDENTIFICATION_ ## name)
 
#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_SHIFT   (16)
 
#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_MASK   (0x00010000)
 
#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_SHIFT   (17)
 
#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_MASK   (0x00020000)
 
#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_SHIFT   (18)
 
#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_MASK   (0x00040000)
 
#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_SHIFT   (24)
 
#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_MASK   (0xFF000000)
 
#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_RESERVED_MASK   (0x00F800FF)
 
#define SCU_SAS_TIPID_GEN_VALUE(name, value)   SCU_GEN_VALUE(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ ## name, value)
 
#define SCU_SAS_TIPID_GEN_BIT(name)   SCU_GEN_BIT(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ ## name)
 
#define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_SHIFT   (4)
 
#define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_MASK   (0x00000010)
 
#define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_SHIFT   (6)
 
#define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_MASK   (0x00000040)
 
#define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_SHIFT   (7)
 
#define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_MASK   (0x00000080)
 
#define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_SHIFT   (8)
 
#define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_MASK   (0x00000100)
 
#define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_SHIFT   (9)
 
#define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_MASK   (0x00000200)
 
#define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_SHIFT   (11)
 
#define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_MASK   (0x00000800)
 
#define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_SHIFT   (12)
 
#define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_MASK   (0x00001000)
 
#define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_SHIFT   (13)
 
#define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_MASK   (0x00002000)
 
#define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_SHIFT   (14)
 
#define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_MASK   (0x00004000)
 
#define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_SHIFT   (15)
 
#define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_MASK   (0x00008000)
 
#define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_SHIFT   (23)
 
#define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_MASK   (0x00800000)
 
#define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_SHIFT   (27)
 
#define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_MASK   (0x08000000)
 
#define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_SHIFT   (28)
 
#define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_MASK   (0x10000000)
 
#define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_SHIFT   (29)
 
#define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_MASK   (0x20000000)
 
#define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_SHIFT   (30)
 
#define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_MASK   (0x40000000)
 
#define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_SHIFT   (31)
 
#define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_MASK   (0x80000000)
 
#define SCU_SAS_PHY_CONFIGURATION_REQUIRED_MASK   (0x0100000F)
 
#define SCU_SAS_PHY_CONFIGURATION_DEFAULT_MASK   (0x4180100F)
 
#define SCU_SAS_PHY_CONFIGURATION_RESERVED_MASK   (0x00000000)
 
#define SCU_SAS_PCFG_GEN_BIT(name)   SCU_GEN_BIT(SCU_SAS_PHY_CONFIGURATION_ ## name)
 
#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_SHIFT   (0)
 
#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_MASK   (0x000007FF)
 
#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_SHIFT   (16)
 
#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_MASK   (0x00ff0000)
 
#define SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(name, value)   SCU_GEN_VALUE(SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_##name, value)
 
#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_SHIFT   (0)
 
#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_MASK   (0x0003FFFF)
 
#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_SHIFT   (31)
 
#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_MASK   (0x80000000)
 
#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_RESERVED_MASK   (0x7FFC0000)
 
#define SCU_ENSPINUP_GEN_VAL(name, value)   SCU_GEN_VALUE(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ ## name, value)
 
#define SCU_ENSPINUP_GEN_BIT(name)   SCU_GEN_BIT(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ ## name)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_SHIFT   (1)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_MASK   (0x00000002)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_SHIFT   (4)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_MASK   (0x000000F0)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_SHIFT   (8)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_MASK   (0x00000100)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_SHIFT   (9)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_MASK   (0x00000201)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_SHIFT   (10)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_MASK   (0x00000401)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_SHIFT   (11)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_MASK   (0x00000801)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_SHIFT   (12)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_MASK   (0x00001001)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_SHIFT   (13)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_MASK   (0x00002001)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_SHIFT   (31)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_MASK   (0x80000000)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_DEFAULT_MASK   (0x00003F01)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_REQUIRED_MASK   (0x00000001)
 
#define SCU_LINK_LAYER_PHY_CAPABILITIES_RESERVED_MASK   (0x7FFFC00D)
 
#define SCU_SAS_PHYCAP_GEN_VAL(name, value)   SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_CAPABILITIES_ ## name, value)
 
#define SCU_SAS_PHYCAP_GEN_BIT(name)   SCU_GEN_BIT(SCU_LINK_LAYER_PHY_CAPABILITIES_ ## name)
 
#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_SHIFT   (0)
 
#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_MASK   (0x000000FF)
 
#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_SHIFT   (31)
 
#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_MASK   (0x80000000)
 
#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_RESERVED_MASK   (0x7FFFFF00)
 
#define SCU_PSZGCR_GEN_VAL(name, value)   SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_ ## name, value)
 
#define SCU_PSZGCR_GEN_BIT(name)   SCU_GEN_BIT(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_ ## name)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_SHIFT   (1)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_MASK   (0x00000002)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_SHIFT   (2)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_MASK   (0x00000004)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_SHIFT   (4)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_MASK   (0x00000010)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_SHIFT   (5)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_MASK   (0x00000020)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_SHIFT   (16)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_MASK   (0x00030000)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_SHIFT   (19)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_MASK   (0x00080000)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_SHIFT   (20)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_MASK   (0x00300000)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_SHIFT   (23)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_MASK   (0x00800000)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_SHIFT   (24)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_MASK   (0x03000000)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_SHIFT   (27)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_MASK   (0x08000000)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_SHIFT   (28)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_MASK   (0x30000000)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_SHIFT   (31)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_MASK   (0x80000000)
 
#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_RESERVED_MASK   (0x4444FFC9)
 
#define SCU_PEG_SCUVZECR_GEN_VAL(name, val)   SCU_GEN_VALUE(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name, val)
 
#define SCU_PEG_SCUVZECR_GEN_BIT(name)   SCU_GEN_BIT(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name)
 
#define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_SHIFT   (0)
 
#define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_MASK   (0x0000FFFF)
 
#define SCU_PTSG_CONTROL_TASK_TIMEOUT_SHIFT   (16)
 
#define SCU_PTSG_CONTROL_TASK_TIMEOUT_MASK   (0x00FF0000)
 
#define SCU_PTSG_CONTROL_PTSG_ENABLE_SHIFT   (24)
 
#define SCU_PTSG_CONTROL_PTSG_ENABLE_MASK   (0x01000000)
 
#define SCU_PTSG_CONTROL_ETM_ENABLE_SHIFT   (25)
 
#define SCU_PTSG_CONTROL_ETM_ENABLE_MASK   (0x02000000)
 
#define SCU_PTSG_CONTROL_DEFAULT_MASK   (0x00020002)
 
#define SCU_PTSG_CONTROL_REQUIRED_MASK   (0x00000000)
 
#define SCU_PTSG_CONTROL_RESERVED_MASK   (0xFC000000)
 
#define SCU_PTSGCR_GEN_VAL(name, val)   SCU_GEN_VALUE(SCU_PTSG_CONTROL_ ## name, val)
 
#define SCU_PTSGCR_GEN_BIT(name)   SCU_GEN_BIT(SCU_PTSG_CONTROL_ ## name)
 
#define SCU_PTSG_REAL_TIME_CLOCK_SHIFT   (0)
 
#define SCU_PTSG_REAL_TIME_CLOCK_MASK   (0x0000FFFF)
 
#define SCU_PTSG_REAL_TIME_CLOCK_RESERVED_MASK   (0xFFFF0000)
 
#define SCU_RTCR_GEN_VAL(name, val)   SCU_GEN_VALUE(SCU_PTSG_ ## name, val)
 
#define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_SHIFT   (0)
 
#define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_MASK   (0x00FFFFFF)
 
#define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_RESERVED_MASK   (0xFF000000)
 
#define SCU_RTCCR_GEN_VAL(name, val)   SCU_GEN_VALUE(SCU_PTSG_REAL_TIME_CLOCK_CONTROL_ ## name, val)
 
#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_SHIFT   (0)
 
#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_MASK   (0x00000001)
 
#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_SHIFT   (1)
 
#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_MASK   (0x00000002)
 
#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_RESERVED_MASK   (0xFFFFFFFC)
 
#define SCU_PTSxCR_GEN_BIT(name)   SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ ## name)
 
#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_SHIFT   (0)
 
#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_MASK   (0x00000001)
 
#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_SHIFT   (1)
 
#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_MASK   (0x00000002)
 
#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_SHIFT   (2)
 
#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_MASK   (0x00000004)
 
#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_RESERVED_MASK   (0xFFFFFFF8)
 
#define SCU_PTSxSR_GEN_BIT(name)   SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ ## name)
 
#define SCU_SMU_PCP_OFFSET   0x0000
 
#define SCU_SMU_AMR_OFFSET   0x0004
 
#define SCU_SMU_ISR_OFFSET   0x0010
 
#define SCU_SMU_IMR_OFFSET   0x0014
 
#define SCU_SMU_ICC_OFFSET   0x0018
 
#define SCU_SMU_HTTLBAR_OFFSET   0x0020
 
#define SCU_SMU_HTTUBAR_OFFSET   0x0024
 
#define SCU_SMU_TCR_OFFSET   0x0028
 
#define SCU_SMU_CQLBAR_OFFSET   0x0030
 
#define SCU_SMU_CQUBAR_OFFSET   0x0034
 
#define SCU_SMU_CQPR_OFFSET   0x0040
 
#define SCU_SMU_CQGR_OFFSET   0x0044
 
#define SCU_SMU_CQC_OFFSET   0x0048
 
#define SCU_SMU_RNCLBAR_OFFSET   0x0080
 
#define SCU_SMU_RNCUBAR_OFFSET   0x0084
 
#define SCU_SMU_DCC_OFFSET   0x0090
 
#define SCU_SMU_DFC_OFFSET   0x0094
 
#define SCU_SMU_SMUCSR_OFFSET   0x0098
 
#define SCU_SMU_SCUSRCR_OFFSET   0x009C
 
#define SCU_SMU_SMAW_OFFSET   0x00A0
 
#define SCU_SMU_SMDW_OFFSET   0x00A4
 
#define SCU_SMU_TCA_OFFSET   0x0400
 
#define SCU_SMU_MT_MLAR0_OFFSET   0x2000
 
#define SCU_SMU_MT_MUAR0_OFFSET   0x2004
 
#define SCU_SMU_MT_MDR0_OFFSET   0x2008
 
#define SCU_SMU_MT_VCR0_OFFSET   0x200C
 
#define SCU_SMU_MT_MLAR1_OFFSET   0x2010
 
#define SCU_SMU_MT_MUAR1_OFFSET   0x2014
 
#define SCU_SMU_MT_MDR1_OFFSET   0x2018
 
#define SCU_SMU_MT_VCR1_OFFSET   0x201C
 
#define SCU_SMU_MPBA_OFFSET   0x3000
 
#define SCU_SDMA_BASE   0x6000
 
#define SCU_SDMA_PUFATLHAR_OFFSET   0x0000
 
#define SCU_SDMA_PUFATUHAR_OFFSET   0x0004
 
#define SCU_SDMA_UFLHBAR_OFFSET   0x0008
 
#define SCU_SDMA_UFUHBAR_OFFSET   0x000C
 
#define SCU_SDMA_UFQC_OFFSET   0x0010
 
#define SCU_SDMA_UFQPP_OFFSET   0x0014
 
#define SCU_SDMA_UFQGP_OFFSET   0x0018
 
#define SCU_SDMA_PDMACR_OFFSET   0x001C
 
#define SCU_SDMA_CDMACR_OFFSET   0x0080
 
#define SCU_PEG0_OFFSET   0x0000
 
#define SCU_PEG1_OFFSET   0x8000
 
#define SCU_TL0_OFFSET   0x0000
 
#define SCU_TL1_OFFSET   0x0400
 
#define SCU_TL2_OFFSET   0x0800
 
#define SCU_TL3_OFFSET   0x0C00
 
#define SCU_LL_OFFSET   0x0080
 
#define SCU_LL0_OFFSET   (SCU_TL0_OFFSET + SCU_LL_OFFSET)
 
#define SCU_LL1_OFFSET   (SCU_TL1_OFFSET + SCU_LL_OFFSET)
 
#define SCU_LL2_OFFSET   (SCU_TL2_OFFSET + SCU_LL_OFFSET)
 
#define SCU_LL3_OFFSET   (SCU_TL3_OFFSET + SCU_LL_OFFSET)
 
#define SCU_TLCR_OFFSET   0x0000
 
#define SCU_TLADTR_OFFSET   0x0004
 
#define SCU_TLTTMR_OFFSET   0x0008
 
#define SCU_TLEECR0_OFFSET   0x000C
 
#define SCU_STPTLDARNI_OFFSET   0x0010
 
#define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_SHIFT   (0)
 
#define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_MASK   (0x00000001)
 
#define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_SHIFT   (1)
 
#define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_MASK   (0x00000002)
 
#define SCU_TLCR_STP_WRITE_DATA_PREFETCH_SHIFT   (3)
 
#define SCU_TLCR_STP_WRITE_DATA_PREFETCH_MASK   (0x00000008)
 
#define SCU_TLCR_CMD_NAK_STATUS_CODE_SHIFT   (4)
 
#define SCU_TLCR_CMD_NAK_STATUS_CODE_MASK   (0x00000010)
 
#define SCU_TLCR_RESERVED_MASK   (0xFFFFFFEB)
 
#define SCU_TLCR_GEN_BIT(name)   SCU_GEN_BIT(SCU_TLCR_ ## name)
 
#define SCU_SCUVZECRx_OFFSET   0x1080
 
#define SCU_SAS_SPDTOV_OFFSET   0x0000
 
#define SCU_SAS_LLSTA_OFFSET   0x0004
 
#define SCU_SATA_PSELTOV_OFFSET   0x0008
 
#define SCU_SAS_TIMETOV_OFFSET   0x0010
 
#define SCU_SAS_LOSTOT_OFFSET   0x0014
 
#define SCU_SAS_LNKTOV_OFFSET   0x0018
 
#define SCU_SAS_PHYTOV_OFFSET   0x001C
 
#define SCU_SAS_AFERCNT_OFFSET   0x0020
 
#define SCU_SAS_WERCNT_OFFSET   0x0024
 
#define SCU_SAS_TIID_OFFSET   0x0028
 
#define SCU_SAS_TIDNH_OFFSET   0x002C
 
#define SCU_SAS_TIDNL_OFFSET   0x0030
 
#define SCU_SAS_TISSAH_OFFSET   0x0034
 
#define SCU_SAS_TISSAL_OFFSET   0x0038
 
#define SCU_SAS_TIPID_OFFSET   0x003C
 
#define SCU_SAS_TIRES2_OFFSET   0x0040
 
#define SCU_SAS_ADRSTA_OFFSET   0x0044
 
#define SCU_SAS_MAWTTOV_OFFSET   0x0048
 
#define SCU_SAS_FRPLDFIL_OFFSET   0x0054
 
#define SCU_SAS_RFCNT_OFFSET   0x0060
 
#define SCU_SAS_TFCNT_OFFSET   0x0064
 
#define SCU_SAS_RFDCNT_OFFSET   0x0068
 
#define SCU_SAS_TFDCNT_OFFSET   0x006C
 
#define SCU_SAS_LERCNT_OFFSET   0x0070
 
#define SCU_SAS_RDISERRCNT_OFFSET   0x0074
 
#define SCU_SAS_CRERCNT_OFFSET   0x0078
 
#define SCU_STPCTL_OFFSET   0x007C
 
#define SCU_SAS_PCFG_OFFSET   0x0080
 
#define SCU_SAS_CLKSM_OFFSET   0x0084
 
#define SCU_SAS_TXCOMWAKE_OFFSET   0x0088
 
#define SCU_SAS_TXCOMINIT_OFFSET   0x008C
 
#define SCU_SAS_TXCOMSAS_OFFSET   0x0090
 
#define SCU_SAS_COMINIT_OFFSET   0x0094
 
#define SCU_SAS_COMWAKE_OFFSET   0x0098
 
#define SCU_SAS_COMSAS_OFFSET   0x009C
 
#define SCU_SAS_SFERCNT_OFFSET   0x00A0
 
#define SCU_SAS_CDFERCNT_OFFSET   0x00A4
 
#define SCU_SAS_DNFERCNT_OFFSET   0x00A8
 
#define SCU_SAS_PRSTERCNT_OFFSET   0x00AC
 
#define SCU_SAS_CNTCTL_OFFSET   0x00B0
 
#define SCU_SAS_SSPTOV_OFFSET   0x00B4
 
#define SCU_FTCTL_OFFSET   0x00B8
 
#define SCU_FRCTL_OFFSET   0x00BC
 
#define SCU_FTWMRK_OFFSET   0x00C0
 
#define SCU_ENSPINUP_OFFSET   0x00C4
 
#define SCU_SAS_TRNTOV_OFFSET   0x00C8
 
#define SCU_SAS_PHYCAP_OFFSET   0x00CC
 
#define SCU_SAS_PHYCTL_OFFSET   0x00D0
 
#define SCU_SAS_LLCTL_OFFSET   0x00D8
 
#define SCU_AFE_XCVRCR_OFFSET   0x00DC
 
#define SCU_AFE_LUTCR_OFFSET   0x00E0
 
#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_SHIFT   (0UL)
 
#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_MASK   (0x000000FFUL)
 
#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_SHIFT   (8UL)
 
#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_MASK   (0x0000FF00UL)
 
#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_SHIFT   (16UL)
 
#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_MASK   (0x00FF0000UL)
 
#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_SHIFT   (24UL)
 
#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_MASK   (0xFF000000UL)
 
#define SCU_SAS_PHYTOV_GEN_VAL(name, value)   SCU_GEN_VALUE(SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_##name, value)
 
#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_SHIFT   (0)
 
#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_MASK   (0x00000003)
 
#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1   (0)
 
#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2   (1)
 
#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3   (2)
 
#define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_SHIFT   (2)
 
#define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_MASK   (0x000003FC)
 
#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_SHIFT   (16)
 
#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_MASK   (0x00010000)
 
#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_SHIFT   (17)
 
#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_MASK   (0x00020000)
 
#define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_SHIFT   (24)
 
#define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_MASK   (0xFF000000)
 
#define SCU_SAS_LINK_LAYER_CONTROL_RESERVED   (0x00FCFC00)
 
#define SCU_SAS_LLCTL_GEN_VAL(name, value)   SCU_GEN_VALUE(SCU_SAS_LINK_LAYER_CONTROL_ ## name, value)
 
#define SCU_SAS_LLCTL_GEN_BIT(name)   SCU_GEN_BIT(SCU_SAS_LINK_LAYER_CONTROL_ ## name)
 
#define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT   (0xF0)
 
#define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_EXTENDED   (0x1FF)
 
#define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_SHIFT   (0)
 
#define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_MASK   (0x3FF)
 
#define SCU_SAS_LLTXCOMSAS_GEN_VAL(name, value)   SCU_GEN_VALUE(SCU_SAS_LINK_LAYER_TXCOMSAS_ ## name, value)
 
#define SCU_PSZGCR_OFFSET   0x00E4
 
#define SCU_SAS_RECPHYCAP_OFFSET   0x00E8
 
#define SCU_SAS_PTxC_OFFSET   0x00D4 /* Same offset as SAS_TCTSTM */
 
#define SCU_SGPIO_OFFSET   0x1400
 
#define SCU_SGPIO_SGICR_OFFSET   0x0000
 
#define SCU_SGPIO_SGPBR_OFFSET   0x0004
 
#define SCU_SGPIO_SGSDLR_OFFSET   0x0008
 
#define SCU_SGPIO_SGSDUR_OFFSET   0x000C
 
#define SCU_SGPIO_SGSIDLR_OFFSET   0x0010
 
#define SCU_SGPIO_SGSIDUR_OFFSET   0x0014
 
#define SCU_SGPIO_SGVSCR_OFFSET   0x0018
 
#define SCU_SGPIO_SGODSR_OFFSET   0x0020
 
#define SCU_VIIT_BASE   0x1c00
 
#define SCU_PTSG_BASE   0x1000
 
#define SCU_PTSG_PTSGCR_OFFSET   0x0000
 
#define SCU_PTSG_RTCR_OFFSET   0x0004
 
#define SCU_PTSG_RTCCR_OFFSET   0x0008
 
#define SCU_PTSG_PTS0CR_OFFSET   0x0010
 
#define SCU_PTSG_PTS0SR_OFFSET   0x0014
 
#define SCU_PTSG_PTS1CR_OFFSET   0x0018
 
#define SCU_PTSG_PTS1SR_OFFSET   0x001C
 
#define SCU_PTSG_PTS2CR_OFFSET   0x0020
 
#define SCU_PTSG_PTS2SR_OFFSET   0x0024
 
#define SCU_PTSG_PTS3CR_OFFSET   0x0028
 
#define SCU_PTSG_PTS3SR_OFFSET   0x002C
 
#define SCU_PTSG_PCSPE0CR_OFFSET   0x0030
 
#define SCU_PTSG_PCSPE1CR_OFFSET   0x0034
 
#define SCU_PTSG_PCSPE2CR_OFFSET   0x0038
 
#define SCU_PTSG_PCSPE3CR_OFFSET   0x003C
 
#define SCU_PTSG_ETMTSCCR_OFFSET   0x0040
 
#define SCU_PTSG_ETMRNSCCR_OFFSET   0x0044
 
#define SCU_PTSG_SCUVZECR_OFFSET   0x003C
 
#define SCU_AFE_MMR_BASE   0xE000
 
#define scu_scratch_ram_SIZE_IN_DWORDS   256
 

Macro Definition Documentation

#define SCU_AFE_LUTCR_OFFSET   0x00E0

Definition at line 1207 of file registers.h.

#define SCU_AFE_MMR_BASE   0xE000

Definition at line 1549 of file registers.h.

#define SCU_AFE_XCVRCR_OFFSET   0x00DC

Definition at line 1206 of file registers.h.

#define SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_##name, value)

Definition at line 748 of file registers.h.

#define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK   (0x00000100)

Definition at line 599 of file registers.h.

#define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT   (8)

Definition at line 598 of file registers.h.

#define SCU_CDMACR_GEN_BIT (   name)    SCU_GEN_BIT(SCU_CDMA_CONFIGURATION_ ## name)

Definition at line 601 of file registers.h.

#define SCU_CLEAR_BIT (   name,
  reg_value 
)    ((reg_value)$ ~(SCU_GEN_BIT(name)))

Definition at line 190 of file registers.h.

#define SCU_ENSPINUP_GEN_BIT (   name)    SCU_GEN_BIT(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ ## name)

Definition at line 760 of file registers.h.

#define SCU_ENSPINUP_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ ## name, value)

Definition at line 757 of file registers.h.

#define SCU_ENSPINUP_OFFSET   0x00C4

Definition at line 1201 of file registers.h.

#define SCU_FRCTL_OFFSET   0x00BC

Definition at line 1199 of file registers.h.

#define SCU_FTCTL_OFFSET   0x00B8

Definition at line 1198 of file registers.h.

#define SCU_FTWMRK_OFFSET   0x00C0

Definition at line 1200 of file registers.h.

#define SCU_GEN_BIT (   name)    SCU_GEN_VALUE(name, ((u32)1))

Definition at line 184 of file registers.h.

#define SCU_GEN_VALUE (   name,
  value 
)    (((value) << name ## _SHIFT) & (name ## _MASK))

Definition at line 178 of file registers.h.

#define SCU_IIT_ENTRY_ID_IIT   (2 << SCU_IIT_ENTRY_ID_SHIFT)

Definition at line 160 of file registers.h.

#define SCU_IIT_ENTRY_ID_INVALID   (0 << SCU_IIT_ENTRY_ID_SHIFT)

Definition at line 158 of file registers.h.

#define SCU_IIT_ENTRY_ID_MASK   (0xC0000000)

Definition at line 139 of file registers.h.

#define SCU_IIT_ENTRY_ID_SHIFT   (30)

Definition at line 140 of file registers.h.

#define SCU_IIT_ENTRY_ID_VIIT   (1 << SCU_IIT_ENTRY_ID_SHIFT)

Definition at line 159 of file registers.h.

#define SCU_IIT_ENTRY_ID_VIRT_EXP   (3 << SCU_IIT_ENTRY_ID_SHIFT)

Definition at line 161 of file registers.h.

#define SCU_IIT_ENTRY_LPI_MASK   (0x00000F00)

Definition at line 145 of file registers.h.

#define SCU_IIT_ENTRY_LPI_SHIFT   (8)

Definition at line 146 of file registers.h.

#define SCU_IIT_ENTRY_REMOTE_RNC_MASK   (0x0FFF0000)

Definition at line 155 of file registers.h.

#define SCU_IIT_ENTRY_REMOTE_RNC_SHIFT   (16)

Definition at line 156 of file registers.h.

#define SCU_IIT_ENTRY_REMOTE_TAG_MASK   (0x0000FFFF)

Definition at line 152 of file registers.h.

#define SCU_IIT_ENTRY_REMOTE_TAG_SHIFT   (0)

Definition at line 153 of file registers.h.

#define SCU_IIT_ENTRY_STATUS_MASK   (0x000000FF)

Definition at line 148 of file registers.h.

#define SCU_IIT_ENTRY_STATUS_SHIFT   (0)

Definition at line 149 of file registers.h.

#define SCU_IIT_ENTRY_STATUS_UPDATE_MASK   (0x20000000)

Definition at line 142 of file registers.h.

#define SCU_IIT_ENTRY_STATUS_UPDATE_SHIFT   (29)

Definition at line 143 of file registers.h.

#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_MASK   (0x00ff0000)

Definition at line 746 of file registers.h.

#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_SHIFT   (16)

Definition at line 745 of file registers.h.

#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_MASK   (0x000007FF)

Definition at line 744 of file registers.h.

#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_SHIFT   (0)

Definition at line 743 of file registers.h.

#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_MASK   (0x0003FFFF)

Definition at line 752 of file registers.h.

#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_SHIFT   (0)

Definition at line 751 of file registers.h.

#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_MASK   (0x80000000)

Definition at line 754 of file registers.h.

#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_SHIFT   (31)

Definition at line 753 of file registers.h.

#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_RESERVED_MASK   (0x7FFC0000)

Definition at line 755 of file registers.h.

#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_MASK   (0x00010000)

Definition at line 688 of file registers.h.

#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_SHIFT   (16)

Definition at line 687 of file registers.h.

#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_MASK   (0xFF000000)

Definition at line 694 of file registers.h.

#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_SHIFT   (24)

Definition at line 693 of file registers.h.

#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_MASK   (0x00040000)

Definition at line 692 of file registers.h.

#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_SHIFT   (18)

Definition at line 691 of file registers.h.

#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_MASK   (0x00020000)

Definition at line 690 of file registers.h.

#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_SHIFT   (17)

Definition at line 689 of file registers.h.

#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_RESERVED_MASK   (0x00F800FF)

Definition at line 695 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_DEFAULT_MASK   (0x00003F01)

Definition at line 782 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_MASK   (0x80000000)

Definition at line 781 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_SHIFT   (31)

Definition at line 780 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_REQUIRED_MASK   (0x00000001)

Definition at line 783 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_RESERVED_MASK   (0x7FFFC00D)

Definition at line 784 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_MASK   (0x000000F0)

Definition at line 767 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_SHIFT   (4)

Definition at line 766 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_MASK   (0x00000201)

Definition at line 771 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_SHIFT   (9)

Definition at line 770 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_MASK   (0x00000801)

Definition at line 775 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_SHIFT   (11)

Definition at line 774 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_MASK   (0x00002001)

Definition at line 779 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_SHIFT   (13)

Definition at line 778 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_MASK   (0x00000100)

Definition at line 769 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_SHIFT   (8)

Definition at line 768 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_MASK   (0x00000401)

Definition at line 773 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_SHIFT   (10)

Definition at line 772 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_MASK   (0x00001001)

Definition at line 777 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_SHIFT   (12)

Definition at line 776 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_MASK   (0x00000002)

Definition at line 765 of file registers.h.

#define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_SHIFT   (1)

Definition at line 764 of file registers.h.

#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_MASK   (0x80000000)

Definition at line 796 of file registers.h.

#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_SHIFT   (31)

Definition at line 795 of file registers.h.

#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_RESERVED_MASK   (0x7FFFFF00)

Definition at line 797 of file registers.h.

#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_MASK   (0x000000FF)

Definition at line 794 of file registers.h.

#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_SHIFT   (0)

Definition at line 793 of file registers.h.

#define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_DEFAULT_MASK   (0x7D00676F)

Definition at line 617 of file registers.h.

#define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_REQUIRED_MASK   (0x00000000)

Definition at line 616 of file registers.h.

#define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_RESERVED_MASK   (0x00FF0000)

Definition at line 618 of file registers.h.

#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_MASK   (0xFF000000)

Definition at line 615 of file registers.h.

#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_SHIFT   (24)

Definition at line 614 of file registers.h.

#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_MASK   (0x0000FF00)

Definition at line 611 of file registers.h.

#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_SHIFT   (8)

Definition at line 610 of file registers.h.

#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_MASK   (0x00FF0000)

Definition at line 613 of file registers.h.

#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_SHIFT   (16)

Definition at line 612 of file registers.h.

#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_MASK   (0x000000FF)

Definition at line 609 of file registers.h.

#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_SHIFT   (0)

Definition at line 608 of file registers.h.

#define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_MASK   (0x00000004)

Definition at line 625 of file registers.h.

#define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_SHIFT   (2)

Definition at line 624 of file registers.h.

#define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_MASK   (0x00000020)

Definition at line 629 of file registers.h.

#define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_SHIFT   (5)

Definition at line 628 of file registers.h.

#define SCU_LINK_STATUS_RESERVED_MASK   (0xFFFFFFCD)

Definition at line 630 of file registers.h.

#define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_MASK   (0x00000010)

Definition at line 627 of file registers.h.

#define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_SHIFT   (4)

Definition at line 626 of file registers.h.

#define SCU_LL0_OFFSET   (SCU_TL0_OFFSET + SCU_LL_OFFSET)

Definition at line 1095 of file registers.h.

#define SCU_LL1_OFFSET   (SCU_TL1_OFFSET + SCU_LL_OFFSET)

Definition at line 1096 of file registers.h.

#define SCU_LL2_OFFSET   (SCU_TL2_OFFSET + SCU_LL_OFFSET)

Definition at line 1097 of file registers.h.

#define SCU_LL3_OFFSET   (SCU_TL3_OFFSET + SCU_LL_OFFSET)

Definition at line 1098 of file registers.h.

#define SCU_LL_OFFSET   0x0080

Definition at line 1094 of file registers.h.

#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_MASK   (0x0000FFFF)

Definition at line 571 of file registers.h.

#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_MASK   (0x00400000)

Definition at line 585 of file registers.h.

#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_SHIFT   (22)

Definition at line 584 of file registers.h.

#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SHIFT   (0)

Definition at line 570 of file registers.h.

#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_MASK   (0x00040000)

Definition at line 577 of file registers.h.

#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_SHIFT   (18)

Definition at line 576 of file registers.h.

#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_MASK   (0x00100000)

Definition at line 581 of file registers.h.

#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_SHIFT   (20)

Definition at line 580 of file registers.h.

#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_MASK   (0x00080000)

Definition at line 579 of file registers.h.

#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_SHIFT   (19)

Definition at line 578 of file registers.h.

#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_MASK   (0x00200000)

Definition at line 583 of file registers.h.

#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_SHIFT   (21)

Definition at line 582 of file registers.h.

#define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_MASK   (0x00020000)

Definition at line 575 of file registers.h.

#define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_SHIFT   (17)

Definition at line 574 of file registers.h.

#define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK   (0x00010000)

Definition at line 573 of file registers.h.

#define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT   (16)

Definition at line 572 of file registers.h.

#define SCU_PDMA_CONFIGURATION_RESERVED_MASK   (0xFF800000)

Definition at line 586 of file registers.h.

#define SCU_PDMACR_BE_GEN_BIT (   name)    SCU_PCMACR_GEN_BIT(BIG_ENDIAN_CONTROL_ ## name)

Definition at line 594 of file registers.h.

#define SCU_PDMACR_GEN_BIT (   name)    SCU_GEN_BIT(SCU_PDMA_CONFIGURATION_ ## name)

Definition at line 591 of file registers.h.

#define SCU_PDMACR_GEN_VALUE (   name,
  value 
)    SCU_GEN_VALUE(SCU_PDMA_CONFIGURATION_ ## name, value)

Definition at line 588 of file registers.h.

#define SCU_PEG0_OFFSET   0x0000

Definition at line 1086 of file registers.h.

#define SCU_PEG1_OFFSET   0x8000

Definition at line 1087 of file registers.h.

#define SCU_PEG_SCUVZECR_GEN_BIT (   name)    SCU_GEN_BIT(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name)

Definition at line 834 of file registers.h.

#define SCU_PEG_SCUVZECR_GEN_VAL (   name,
  val 
)    SCU_GEN_VALUE(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name, val)

Definition at line 831 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_MASK   (0x00080000)

Definition at line 816 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_SHIFT   (19)

Definition at line 815 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_MASK   (0x00800000)

Definition at line 820 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_SHIFT   (23)

Definition at line 819 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_MASK   (0x08000000)

Definition at line 824 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_SHIFT   (27)

Definition at line 823 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_MASK   (0x80000000)

Definition at line 828 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_SHIFT   (31)

Definition at line 827 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_RESERVED_MASK   (0x4444FFC9)

Definition at line 829 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_MASK   (0x00000002)

Definition at line 806 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_SHIFT   (1)

Definition at line 805 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_MASK   (0x00000004)

Definition at line 808 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_SHIFT   (2)

Definition at line 807 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_MASK   (0x00000010)

Definition at line 810 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_SHIFT   (4)

Definition at line 809 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_MASK   (0x00000020)

Definition at line 812 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_SHIFT   (5)

Definition at line 811 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_MASK   (0x00030000)

Definition at line 814 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_SHIFT   (16)

Definition at line 813 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_MASK   (0x00300000)

Definition at line 818 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_SHIFT   (20)

Definition at line 817 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_MASK   (0x03000000)

Definition at line 822 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_SHIFT   (24)

Definition at line 821 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_MASK   (0x30000000)

Definition at line 826 of file registers.h.

#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_SHIFT   (28)

Definition at line 825 of file registers.h.

#define SCU_PSZGCR_GEN_BIT (   name)    SCU_GEN_BIT(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_ ## name)

Definition at line 802 of file registers.h.

#define SCU_PSZGCR_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_ ## name, value)

Definition at line 799 of file registers.h.

#define SCU_PSZGCR_OFFSET   0x00E4

Definition at line 1252 of file registers.h.

#define SCU_PTSG_BASE   0x1000

Definition at line 1472 of file registers.h.

#define SCU_PTSG_CONTROL_DEFAULT_MASK   (0x00020002)

Definition at line 850 of file registers.h.

#define SCU_PTSG_CONTROL_ETM_ENABLE_MASK   (0x02000000)

Definition at line 849 of file registers.h.

#define SCU_PTSG_CONTROL_ETM_ENABLE_SHIFT   (25)

Definition at line 848 of file registers.h.

#define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_MASK   (0x0000FFFF)

Definition at line 843 of file registers.h.

#define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_SHIFT   (0)

Definition at line 842 of file registers.h.

#define SCU_PTSG_CONTROL_PTSG_ENABLE_MASK   (0x01000000)

Definition at line 847 of file registers.h.

#define SCU_PTSG_CONTROL_PTSG_ENABLE_SHIFT   (24)

Definition at line 846 of file registers.h.

#define SCU_PTSG_CONTROL_REQUIRED_MASK   (0x00000000)

Definition at line 851 of file registers.h.

#define SCU_PTSG_CONTROL_RESERVED_MASK   (0xFC000000)

Definition at line 852 of file registers.h.

#define SCU_PTSG_CONTROL_TASK_TIMEOUT_MASK   (0x00FF0000)

Definition at line 845 of file registers.h.

#define SCU_PTSG_CONTROL_TASK_TIMEOUT_SHIFT   (16)

Definition at line 844 of file registers.h.

#define SCU_PTSG_ETMRNSCCR_OFFSET   0x0044

Definition at line 1490 of file registers.h.

#define SCU_PTSG_ETMTSCCR_OFFSET   0x0040

Definition at line 1489 of file registers.h.

#define SCU_PTSG_PCSPE0CR_OFFSET   0x0030

Definition at line 1485 of file registers.h.

#define SCU_PTSG_PCSPE1CR_OFFSET   0x0034

Definition at line 1486 of file registers.h.

#define SCU_PTSG_PCSPE2CR_OFFSET   0x0038

Definition at line 1487 of file registers.h.

#define SCU_PTSG_PCSPE3CR_OFFSET   0x003C

Definition at line 1488 of file registers.h.

#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_MASK   (0x00000002)

Definition at line 881 of file registers.h.

#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_SHIFT   (1)

Definition at line 880 of file registers.h.

#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_RESERVED_MASK   (0xFFFFFFFC)

Definition at line 882 of file registers.h.

#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_MASK   (0x00000001)

Definition at line 879 of file registers.h.

#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_SHIFT   (0)

Definition at line 878 of file registers.h.

#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_MASK   (0x00000002)

Definition at line 891 of file registers.h.

#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_SHIFT   (1)

Definition at line 890 of file registers.h.

#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_MASK   (0x00000001)

Definition at line 889 of file registers.h.

#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_SHIFT   (0)

Definition at line 888 of file registers.h.

#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_MASK   (0x00000004)

Definition at line 893 of file registers.h.

#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_SHIFT   (2)

Definition at line 892 of file registers.h.

#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_RESERVED_MASK   (0xFFFFFFF8)

Definition at line 894 of file registers.h.

#define SCU_PTSG_PTS0CR_OFFSET   0x0010

Definition at line 1477 of file registers.h.

#define SCU_PTSG_PTS0SR_OFFSET   0x0014

Definition at line 1478 of file registers.h.

#define SCU_PTSG_PTS1CR_OFFSET   0x0018

Definition at line 1479 of file registers.h.

#define SCU_PTSG_PTS1SR_OFFSET   0x001C

Definition at line 1480 of file registers.h.

#define SCU_PTSG_PTS2CR_OFFSET   0x0020

Definition at line 1481 of file registers.h.

#define SCU_PTSG_PTS2SR_OFFSET   0x0024

Definition at line 1482 of file registers.h.

#define SCU_PTSG_PTS3CR_OFFSET   0x0028

Definition at line 1483 of file registers.h.

#define SCU_PTSG_PTS3SR_OFFSET   0x002C

Definition at line 1484 of file registers.h.

#define SCU_PTSG_PTSGCR_OFFSET   0x0000

Definition at line 1474 of file registers.h.

#define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_MASK   (0x00FFFFFF)

Definition at line 871 of file registers.h.

#define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_SHIFT   (0)

Definition at line 870 of file registers.h.

#define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_RESERVED_MASK   (0xFF000000)

Definition at line 872 of file registers.h.

#define SCU_PTSG_REAL_TIME_CLOCK_MASK   (0x0000FFFF)

Definition at line 863 of file registers.h.

#define SCU_PTSG_REAL_TIME_CLOCK_RESERVED_MASK   (0xFFFF0000)

Definition at line 864 of file registers.h.

#define SCU_PTSG_REAL_TIME_CLOCK_SHIFT   (0)

Definition at line 862 of file registers.h.

#define SCU_PTSG_RTCCR_OFFSET   0x0008

Definition at line 1476 of file registers.h.

#define SCU_PTSG_RTCR_OFFSET   0x0004

Definition at line 1475 of file registers.h.

#define SCU_PTSG_SCUVZECR_OFFSET   0x003C

Definition at line 1543 of file registers.h.

#define SCU_PTSGCR_GEN_BIT (   name)    SCU_GEN_BIT(SCU_PTSG_CONTROL_ ## name)

Definition at line 857 of file registers.h.

#define SCU_PTSGCR_GEN_VAL (   name,
  val 
)    SCU_GEN_VALUE(SCU_PTSG_CONTROL_ ## name, val)

Definition at line 854 of file registers.h.

#define SCU_PTSxCR_GEN_BIT (   name)    SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ ## name)

Definition at line 884 of file registers.h.

#define SCU_PTSxSR_GEN_BIT (   name)    SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ ## name)

Definition at line 896 of file registers.h.

#define SCU_RAM_INIT_COMPLETED
Value:
(\
SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED \
| SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED \
)

Definition at line 415 of file registers.h.

#define SCU_RTCCR_GEN_VAL (   name,
  val 
)    SCU_GEN_VALUE(SCU_PTSG_REAL_TIME_CLOCK_CONTROL_ ## name, val)

Definition at line 874 of file registers.h.

#define SCU_RTCR_GEN_VAL (   name,
  val 
)    SCU_GEN_VALUE(SCU_PTSG_ ## name, val)

Definition at line 866 of file registers.h.

#define SCU_SAS_ADRSTA_OFFSET   0x0044

Definition at line 1173 of file registers.h.

#define SCU_SAS_AFERCNT_OFFSET   0x0020

Definition at line 1164 of file registers.h.

#define SCU_SAS_CDFERCNT_OFFSET   0x00A4

Definition at line 1193 of file registers.h.

#define SCU_SAS_CLKSM_OFFSET   0x0084

Definition at line 1185 of file registers.h.

#define SCU_SAS_CNTCTL_OFFSET   0x00B0

Definition at line 1196 of file registers.h.

#define SCU_SAS_COMINIT_OFFSET   0x0094

Definition at line 1189 of file registers.h.

#define SCU_SAS_COMSAS_OFFSET   0x009C

Definition at line 1191 of file registers.h.

#define SCU_SAS_COMWAKE_OFFSET   0x0098

Definition at line 1190 of file registers.h.

#define SCU_SAS_CRERCNT_OFFSET   0x0078

Definition at line 1182 of file registers.h.

#define SCU_SAS_DNFERCNT_OFFSET   0x00A8

Definition at line 1194 of file registers.h.

#define SCU_SAS_FRPLDFIL_OFFSET   0x0054

Definition at line 1175 of file registers.h.

#define SCU_SAS_LERCNT_OFFSET   0x0070

Definition at line 1180 of file registers.h.

#define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_MASK   (0x000003FC)

Definition at line 1227 of file registers.h.

#define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_SHIFT   (2)

Definition at line 1226 of file registers.h.

#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_MASK   (0x00010000)

Definition at line 1229 of file registers.h.

#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_SHIFT   (16)

Definition at line 1228 of file registers.h.

#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_MASK   (0x00020000)

Definition at line 1231 of file registers.h.

#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_SHIFT   (17)

Definition at line 1230 of file registers.h.

#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1   (0)

Definition at line 1223 of file registers.h.

#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2   (1)

Definition at line 1224 of file registers.h.

#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3   (2)

Definition at line 1225 of file registers.h.

#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_MASK   (0x00000003)

Definition at line 1222 of file registers.h.

#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_SHIFT   (0)

Definition at line 1221 of file registers.h.

#define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_MASK   (0xFF000000)

Definition at line 1233 of file registers.h.

#define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_SHIFT   (24)

Definition at line 1232 of file registers.h.

#define SCU_SAS_LINK_LAYER_CONTROL_RESERVED   (0x00FCFC00)

Definition at line 1234 of file registers.h.

#define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT   (0xF0)

Definition at line 1242 of file registers.h.

#define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_EXTENDED   (0x1FF)

Definition at line 1243 of file registers.h.

#define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_MASK   (0x3FF)

Definition at line 1245 of file registers.h.

#define SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_SHIFT   (0)

Definition at line 1244 of file registers.h.

#define SCU_SAS_LLCTL_GEN_BIT (   name)    SCU_GEN_BIT(SCU_SAS_LINK_LAYER_CONTROL_ ## name)

Definition at line 1239 of file registers.h.

#define SCU_SAS_LLCTL_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SCU_SAS_LINK_LAYER_CONTROL_ ## name, value)

Definition at line 1236 of file registers.h.

#define SCU_SAS_LLCTL_OFFSET   0x00D8

Definition at line 1205 of file registers.h.

#define SCU_SAS_LLSTA_GEN_BIT (   name)    SCU_GEN_BIT(SCU_LINK_STATUS_ ## name)

Definition at line 632 of file registers.h.

#define SCU_SAS_LLSTA_OFFSET   0x0004

Definition at line 1158 of file registers.h.

#define SCU_SAS_LLTXCOMSAS_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SCU_SAS_LINK_LAYER_TXCOMSAS_ ## name, value)

Definition at line 1247 of file registers.h.

#define SCU_SAS_LNKTOV_OFFSET   0x0018

Definition at line 1162 of file registers.h.

#define SCU_SAS_LOSTOT_OFFSET   0x0014

Definition at line 1161 of file registers.h.

#define SCU_SAS_MAWTTOV_GEN_BIT (   name)    SCU_GEN_BIT(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_ ## name)

Definition at line 650 of file registers.h.

#define SCU_SAS_MAWTTOV_GEN_VALUE (   name,
  value 
)    SCU_GEN_VALUE(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_ ## name, value)

Definition at line 647 of file registers.h.

#define SCU_SAS_MAWTTOV_OFFSET   0x0048

Definition at line 1174 of file registers.h.

#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_MASK   (0x00008000)

Definition at line 645 of file registers.h.

#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_SHIFT   (15)

Definition at line 644 of file registers.h.

#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_MASK   (0x00007FFF)

Definition at line 643 of file registers.h.

#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_SHIFT   (0)

Definition at line 642 of file registers.h.

#define SCU_SAS_PCFG_GEN_BIT (   name)    SCU_GEN_BIT(SCU_SAS_PHY_CONFIGURATION_ ## name)

Definition at line 740 of file registers.h.

#define SCU_SAS_PCFG_OFFSET   0x0080

Definition at line 1184 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_DEFAULT_MASK   (0x4180100F)

Definition at line 737 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_MASK   (0x10000000)

Definition at line 729 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_SHIFT   (28)

Definition at line 728 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_MASK   (0x00000200)

Definition at line 713 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_SHIFT   (9)

Definition at line 712 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_MASK   (0x00000100)

Definition at line 711 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_SHIFT   (8)

Definition at line 710 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_MASK   (0x00000080)

Definition at line 709 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_SHIFT   (7)

Definition at line 708 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_MASK   (0x00800000)

Definition at line 725 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_SHIFT   (23)

Definition at line 724 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_MASK   (0x08000000)

Definition at line 727 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_SHIFT   (27)

Definition at line 726 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_MASK   (0x00004000)

Definition at line 721 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_SHIFT   (14)

Definition at line 720 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_MASK   (0x80000000)

Definition at line 735 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_SHIFT   (31)

Definition at line 734 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_MASK   (0x00008000)

Definition at line 723 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_SHIFT   (15)

Definition at line 722 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_MASK   (0x20000000)

Definition at line 731 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_SHIFT   (29)

Definition at line 730 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_REQUIRED_MASK   (0x0100000F)

Definition at line 736 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_RESERVED_MASK   (0x00000000)

Definition at line 738 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_MASK   (0x00001000)

Definition at line 717 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_SHIFT   (12)

Definition at line 716 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_MASK   (0x00000800)

Definition at line 715 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_SHIFT   (11)

Definition at line 714 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_MASK   (0x40000000)

Definition at line 733 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_SHIFT   (30)

Definition at line 732 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_MASK   (0x00002000)

Definition at line 719 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_SHIFT   (13)

Definition at line 718 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_MASK   (0x00000040)

Definition at line 707 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_SHIFT   (6)

Definition at line 706 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_MASK   (0x00000010)

Definition at line 705 of file registers.h.

#define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_SHIFT   (4)

Definition at line 704 of file registers.h.

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_MASK   (0x000000FFUL)

Definition at line 1210 of file registers.h.

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_SHIFT   (0UL)

Definition at line 1209 of file registers.h.

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_MASK   (0x00FF0000UL)

Definition at line 1214 of file registers.h.

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_SHIFT   (16UL)

Definition at line 1213 of file registers.h.

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_MASK   (0x0000FF00UL)

Definition at line 1212 of file registers.h.

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_SHIFT   (8UL)

Definition at line 1211 of file registers.h.

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_MASK   (0xFF000000UL)

Definition at line 1216 of file registers.h.

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_SHIFT   (24UL)

Definition at line 1215 of file registers.h.

#define SCU_SAS_PHYCAP_GEN_BIT (   name)    SCU_GEN_BIT(SCU_LINK_LAYER_PHY_CAPABILITIES_ ## name)

Definition at line 789 of file registers.h.

#define SCU_SAS_PHYCAP_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_CAPABILITIES_ ## name, value)

Definition at line 786 of file registers.h.

#define SCU_SAS_PHYCAP_OFFSET   0x00CC

Definition at line 1203 of file registers.h.

#define SCU_SAS_PHYCTL_OFFSET   0x00D0

Definition at line 1204 of file registers.h.

#define SCU_SAS_PHYTOV_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_##name, value)

Definition at line 1218 of file registers.h.

#define SCU_SAS_PHYTOV_OFFSET   0x001C

Definition at line 1163 of file registers.h.

#define SCU_SAS_PRSTERCNT_OFFSET   0x00AC

Definition at line 1195 of file registers.h.

#define SCU_SAS_PTxC_OFFSET   0x00D4 /* Same offset as SAS_TCTSTM */

Definition at line 1256 of file registers.h.

#define SCU_SAS_RDISERRCNT_OFFSET   0x0074

Definition at line 1181 of file registers.h.

#define SCU_SAS_RECPHYCAP_OFFSET   0x00E8

Definition at line 1253 of file registers.h.

#define SCU_SAS_RFCNT_OFFSET   0x0060

Definition at line 1176 of file registers.h.

#define SCU_SAS_RFDCNT_OFFSET   0x0068

Definition at line 1178 of file registers.h.

#define SCU_SAS_SFERCNT_OFFSET   0x00A0

Definition at line 1192 of file registers.h.

#define SCU_SAS_SPDTOV_GEN_VALUE (   name,
  value 
)    SCU_GEN_VALUE(SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_ ## name, value)

Definition at line 620 of file registers.h.

#define SCU_SAS_SPDTOV_OFFSET   0x0000

Definition at line 1157 of file registers.h.

#define SCU_SAS_SSPTOV_OFFSET   0x00B4

Definition at line 1197 of file registers.h.

#define SCU_SAS_TFCNT_OFFSET   0x0064

Definition at line 1177 of file registers.h.

#define SCU_SAS_TFDCNT_OFFSET   0x006C

Definition at line 1179 of file registers.h.

#define SCU_SAS_TIDNH_OFFSET   0x002C

Definition at line 1167 of file registers.h.

#define SCU_SAS_TIDNL_OFFSET   0x0030

Definition at line 1168 of file registers.h.

#define SCU_SAS_TIID_GEN_BIT (   name)    SCU_GEN_BIT(SCU_SAS_TRANSMIT_IDENTIFICATION_ ## name)

Definition at line 683 of file registers.h.

#define SCU_SAS_TIID_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SCU_SAS_TRANSMIT_IDENTIFICATION_ ## name, value)

Definition at line 680 of file registers.h.

#define SCU_SAS_TIID_OFFSET   0x0028

Definition at line 1166 of file registers.h.

#define SCU_SAS_TIMETOV_OFFSET   0x0010

Definition at line 1160 of file registers.h.

#define SCU_SAS_TIPID_GEN_BIT (   name)    SCU_GEN_BIT(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ ## name)

Definition at line 700 of file registers.h.

#define SCU_SAS_TIPID_GEN_VALUE (   name,
  value 
)    SCU_GEN_VALUE(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ ## name, value)

Definition at line 697 of file registers.h.

#define SCU_SAS_TIPID_OFFSET   0x003C

Definition at line 1171 of file registers.h.

#define SCU_SAS_TIRES2_OFFSET   0x0040

Definition at line 1172 of file registers.h.

#define SCU_SAS_TISSAH_OFFSET   0x0034

Definition at line 1169 of file registers.h.

#define SCU_SAS_TISSAL_OFFSET   0x0038

Definition at line 1170 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_MASK   (0x0F000000)

Definition at line 675 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_SHIFT   (24)

Definition at line 674 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_MASK   (0x00000100)

Definition at line 665 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_SHIFT   (8)

Definition at line 664 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_MASK   (0x70000000)

Definition at line 677 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_SHIFT   (28)

Definition at line 676 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_MASK   (0x000F0000)

Definition at line 673 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_SHIFT   (16)

Definition at line 672 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_RESERVED_MASK   (0x80F0F1F1)

Definition at line 678 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_MASK   (0x00000200)

Definition at line 667 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_SHIFT   (9)

Definition at line 666 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_MASK   (0x00000002)

Definition at line 659 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_SHIFT   (1)

Definition at line 658 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_MASK   (0x00000800)

Definition at line 671 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_SHIFT   (11)

Definition at line 670 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_MASK   (0x00000008)

Definition at line 663 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_SHIFT   (3)

Definition at line 662 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_MASK   (0x00000400)

Definition at line 669 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_SHIFT   (10)

Definition at line 668 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_MASK   (0x00000004)

Definition at line 661 of file registers.h.

#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_SHIFT   (2)

Definition at line 660 of file registers.h.

#define SCU_SAS_TRNTOV_OFFSET   0x00C8

Definition at line 1202 of file registers.h.

#define SCU_SAS_TXCOMINIT_OFFSET   0x008C

Definition at line 1187 of file registers.h.

#define SCU_SAS_TXCOMSAS_OFFSET   0x0090

Definition at line 1188 of file registers.h.

#define SCU_SAS_TXCOMWAKE_OFFSET   0x0088

Definition at line 1186 of file registers.h.

#define SCU_SAS_WERCNT_OFFSET   0x0024

Definition at line 1165 of file registers.h.

#define SCU_SATA_PSELTOV_OFFSET   0x0008

Definition at line 1159 of file registers.h.

#define scu_scratch_ram_SIZE_IN_DWORDS   256

Definition at line 1761 of file registers.h.

#define SCU_SCUVZECRx_OFFSET   0x1080

Definition at line 1154 of file registers.h.

#define SCU_SDMA_BASE   0x6000

Definition at line 1040 of file registers.h.

#define SCU_SDMA_CDMACR_OFFSET   0x0080

Definition at line 1049 of file registers.h.

#define SCU_SDMA_PDMACR_OFFSET   0x001C

Definition at line 1048 of file registers.h.

#define SCU_SDMA_PUFATLHAR_OFFSET   0x0000

Definition at line 1041 of file registers.h.

#define SCU_SDMA_PUFATUHAR_OFFSET   0x0004

Definition at line 1042 of file registers.h.

#define SCU_SDMA_UFLHBAR_OFFSET   0x0008

Definition at line 1043 of file registers.h.

#define SCU_SDMA_UFQC_OFFSET   0x0010

Definition at line 1045 of file registers.h.

#define SCU_SDMA_UFQGP_OFFSET   0x0018

Definition at line 1047 of file registers.h.

#define SCU_SDMA_UFQPP_OFFSET   0x0014

Definition at line 1046 of file registers.h.

#define SCU_SDMA_UFUHBAR_OFFSET   0x000C

Definition at line 1044 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_MASK   (0x00000FFF)

Definition at line 514 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_SHIFT   (0)

Definition at line 513 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_RESERVED_MASK   (0xFFFFF000)

Definition at line 515 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_MASK   (12)

Definition at line 543 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_SHIFT   (12)

Definition at line 542 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_MASK   (0x80000000)

Definition at line 545 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_SHIFT   (31)

Definition at line 544 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_MASK   (0x00000FFF)

Definition at line 541 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_SHIFT   (0)

Definition at line 540 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_RESERVED_MASK   (0x7FFFE000)

Definition at line 546 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_MASK   (0x00001000)

Definition at line 527 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_SHIFT   (12)

Definition at line 526 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_MASK   (0x00000FFF)

Definition at line 525 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_SHIFT   (0)

Definition at line 524 of file registers.h.

#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_RESERVED_MASK   (0xFFFFE000)

Definition at line 528 of file registers.h.

#define SCU_SET_BIT (   name,
  reg_value 
)    ((reg_value) | SCU_GEN_BIT(name))

Definition at line 187 of file registers.h.

#define SCU_SGPIO_OFFSET   0x1400

Definition at line 1414 of file registers.h.

#define SCU_SGPIO_SGICR_OFFSET   0x0000

Definition at line 1417 of file registers.h.

#define SCU_SGPIO_SGODSR_OFFSET   0x0020

Definition at line 1425 of file registers.h.

#define SCU_SGPIO_SGPBR_OFFSET   0x0004

Definition at line 1418 of file registers.h.

#define SCU_SGPIO_SGSDLR_OFFSET   0x0008

Definition at line 1419 of file registers.h.

#define SCU_SGPIO_SGSDUR_OFFSET   0x000C

Definition at line 1420 of file registers.h.

#define SCU_SGPIO_SGSIDLR_OFFSET   0x0010

Definition at line 1421 of file registers.h.

#define SCU_SGPIO_SGSIDUR_OFFSET   0x0014

Definition at line 1422 of file registers.h.

#define SCU_SGPIO_SGVSCR_OFFSET   0x0018

Definition at line 1423 of file registers.h.

#define SCU_SMU_AMR_OFFSET   0x0004

Definition at line 920 of file registers.h.

#define SCU_SMU_CQC_OFFSET   0x0048

Definition at line 931 of file registers.h.

#define SCU_SMU_CQGR_OFFSET   0x0044

Definition at line 930 of file registers.h.

#define SCU_SMU_CQLBAR_OFFSET   0x0030

Definition at line 927 of file registers.h.

#define SCU_SMU_CQPR_OFFSET   0x0040

Definition at line 929 of file registers.h.

#define SCU_SMU_CQUBAR_OFFSET   0x0034

Definition at line 928 of file registers.h.

#define SCU_SMU_DCC_OFFSET   0x0090

Definition at line 935 of file registers.h.

#define SCU_SMU_DFC_OFFSET   0x0094

Definition at line 936 of file registers.h.

#define SCU_SMU_HTTLBAR_OFFSET   0x0020

Definition at line 924 of file registers.h.

#define SCU_SMU_HTTUBAR_OFFSET   0x0024

Definition at line 925 of file registers.h.

#define SCU_SMU_ICC_OFFSET   0x0018

Definition at line 923 of file registers.h.

#define SCU_SMU_IMR_OFFSET   0x0014

Definition at line 922 of file registers.h.

#define SCU_SMU_ISR_OFFSET   0x0010

Definition at line 921 of file registers.h.

#define SCU_SMU_MPBA_OFFSET   0x3000

Definition at line 952 of file registers.h.

#define SCU_SMU_MT_MDR0_OFFSET   0x2008

Definition at line 946 of file registers.h.

#define SCU_SMU_MT_MDR1_OFFSET   0x2018

Definition at line 950 of file registers.h.

#define SCU_SMU_MT_MLAR0_OFFSET   0x2000

Definition at line 944 of file registers.h.

#define SCU_SMU_MT_MLAR1_OFFSET   0x2010

Definition at line 948 of file registers.h.

#define SCU_SMU_MT_MUAR0_OFFSET   0x2004

Definition at line 945 of file registers.h.

#define SCU_SMU_MT_MUAR1_OFFSET   0x2014

Definition at line 949 of file registers.h.

#define SCU_SMU_MT_VCR0_OFFSET   0x200C

Definition at line 947 of file registers.h.

#define SCU_SMU_MT_VCR1_OFFSET   0x201C

Definition at line 951 of file registers.h.

#define SCU_SMU_PCP_OFFSET   0x0000

Definition at line 919 of file registers.h.

#define SCU_SMU_RNCLBAR_OFFSET   0x0080

Definition at line 933 of file registers.h.

#define SCU_SMU_RNCUBAR_OFFSET   0x0084

Definition at line 934 of file registers.h.

#define SCU_SMU_SCUSRCR_OFFSET   0x009C

Definition at line 938 of file registers.h.

#define SCU_SMU_SMAW_OFFSET   0x00A0

Definition at line 939 of file registers.h.

#define SCU_SMU_SMDW_OFFSET   0x00A4

Definition at line 940 of file registers.h.

#define SCU_SMU_SMUCSR_OFFSET   0x0098

Definition at line 937 of file registers.h.

#define SCU_SMU_TCA_OFFSET   0x0400

Definition at line 942 of file registers.h.

#define SCU_SMU_TCR_OFFSET   0x0028

Definition at line 926 of file registers.h.

#define SCU_STPCTL_OFFSET   0x007C

Definition at line 1183 of file registers.h.

#define SCU_STPTLDARNI_OFFSET   0x0010

Definition at line 1105 of file registers.h.

#define SCU_TL0_OFFSET   0x0000

Definition at line 1089 of file registers.h.

#define SCU_TL1_OFFSET   0x0400

Definition at line 1090 of file registers.h.

#define SCU_TL2_OFFSET   0x0800

Definition at line 1091 of file registers.h.

#define SCU_TL3_OFFSET   0x0C00

Definition at line 1092 of file registers.h.

#define SCU_TLADTR_OFFSET   0x0004

Definition at line 1102 of file registers.h.

#define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_MASK   (0x00000002)

Definition at line 1111 of file registers.h.

#define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_SHIFT   (1)

Definition at line 1110 of file registers.h.

#define SCU_TLCR_CMD_NAK_STATUS_CODE_MASK   (0x00000010)

Definition at line 1115 of file registers.h.

#define SCU_TLCR_CMD_NAK_STATUS_CODE_SHIFT   (4)

Definition at line 1114 of file registers.h.

#define SCU_TLCR_GEN_BIT (   name)    SCU_GEN_BIT(SCU_TLCR_ ## name)

Definition at line 1118 of file registers.h.

#define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_MASK   (0x00000001)

Definition at line 1109 of file registers.h.

#define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_SHIFT   (0)

Definition at line 1108 of file registers.h.

#define SCU_TLCR_OFFSET   0x0000

Definition at line 1101 of file registers.h.

#define SCU_TLCR_RESERVED_MASK   (0xFFFFFFEB)

Definition at line 1116 of file registers.h.

#define SCU_TLCR_STP_WRITE_DATA_PREFETCH_MASK   (0x00000008)

Definition at line 1113 of file registers.h.

#define SCU_TLCR_STP_WRITE_DATA_PREFETCH_SHIFT   (3)

Definition at line 1112 of file registers.h.

#define SCU_TLEECR0_OFFSET   0x000C

Definition at line 1104 of file registers.h.

#define SCU_TLTTMR_OFFSET   0x0008

Definition at line 1103 of file registers.h.

#define SCU_UFQC_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_ ## name, value)

Definition at line 517 of file registers.h.

#define SCU_UFQC_QUEUE_SIZE_SET (   value)    SCU_UFQC_GEN_VAL(QUEUE_SIZE, value)

Definition at line 520 of file registers.h.

#define SCU_UFQGP_CYCLE_BIT (   value)    SCU_UFQGP_GEN_BIT(CYCLE_BIT, value)

Definition at line 554 of file registers.h.

#define SCU_UFQGP_DISABLE (   value)    (~SCU_UFQGP_GEN_BIT(ENABLE) & value)

Definition at line 563 of file registers.h.

#define SCU_UFQGP_ENABLE (   value)    (SCU_UFQGP_GEN_BIT(ENABLE) | value)

Definition at line 560 of file registers.h.

#define SCU_UFQGP_GEN_BIT (   name)    SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ ## name)

Definition at line 551 of file registers.h.

#define SCU_UFQGP_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ ## name, value)

Definition at line 548 of file registers.h.

#define SCU_UFQGP_GET_POINTER (   value)    SCU_UFQGP_GEN_VALUE(POINTER, value)

Definition at line 557 of file registers.h.

#define SCU_UFQGP_VALUE (   bit,
  value 
)    (SCU_UFQGP_CYCLE_BIT(bit) | SCU_UFQGP_GET_POINTER(value))

Definition at line 566 of file registers.h.

#define SCU_UFQPP_GEN_BIT (   name)    SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_ ## name)

Definition at line 533 of file registers.h.

#define SCU_UFQPP_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_ ## name, value)

Definition at line 530 of file registers.h.

#define SCU_VIIT_BASE   0x1c00

Definition at line 1461 of file registers.h.

#define SCU_VIIT_ENTRY_FUNCTION_MASK   (0x0FF00000)

Definition at line 69 of file registers.h.

#define SCU_VIIT_ENTRY_FUNCTION_SHIFT   (20)

Definition at line 70 of file registers.h.

#define SCU_VIIT_ENTRY_ID_IIT   (2 << SCU_VIIT_ENTRY_ID_SHIFT)

Definition at line 83 of file registers.h.

#define SCU_VIIT_ENTRY_ID_INVALID   (0 << SCU_VIIT_ENTRY_ID_SHIFT)

Definition at line 81 of file registers.h.

#define SCU_VIIT_ENTRY_ID_MASK   (0xC0000000)

This file contains the constants and structures for the SCU memory mapped registers.

Definition at line 66 of file registers.h.

#define SCU_VIIT_ENTRY_ID_SHIFT   (30)

Definition at line 67 of file registers.h.

#define SCU_VIIT_ENTRY_ID_VIIT   (1 << SCU_VIIT_ENTRY_ID_SHIFT)

Definition at line 82 of file registers.h.

#define SCU_VIIT_ENTRY_ID_VIRT_EXP   (3 << SCU_VIIT_ENTRY_ID_SHIFT)

Definition at line 84 of file registers.h.

#define SCU_VIIT_ENTRY_IPPTMODE_MASK   (0x0001F800)

Definition at line 72 of file registers.h.

#define SCU_VIIT_ENTRY_IPPTMODE_SHIFT   (12)

Definition at line 73 of file registers.h.

#define SCU_VIIT_ENTRY_LPVIE_MASK   (0x00000F00)

Definition at line 75 of file registers.h.

#define SCU_VIIT_ENTRY_LPVIE_SHIFT   (8)

Definition at line 76 of file registers.h.

#define SCU_VIIT_ENTRY_STATUS_MASK   (0x000000FF)

Definition at line 78 of file registers.h.

#define SCU_VIIT_ENTRY_STATUS_SHIFT   (0)

Definition at line 79 of file registers.h.

#define SCU_VIIT_IPPT_INITIATOR
Value:
(\
SCU_VIIT_IPPT_SSP_INITIATOR \
| SCU_VIIT_IPPT_SMP_INITIATOR \
| SCU_VIIT_IPPT_STP_INITIATOR \
)

Definition at line 89 of file registers.h.

#define SCU_VIIT_IPPT_SMP_INITIATOR   (0x02 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)

Definition at line 87 of file registers.h.

#define SCU_VIIT_IPPT_SMP_TARGET   (0x10 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)

Definition at line 106 of file registers.h.

#define SCU_VIIT_IPPT_SSP_INITIATOR   (0x01 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)

Definition at line 86 of file registers.h.

#define SCU_VIIT_IPPT_STP_INITIATOR   (0x04 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)

Definition at line 88 of file registers.h.

#define SCU_VIIT_STATUS_ADDRESS_VALID   (0x02 << SCU_VIIT_ENTRY_STATUS_SHIFT)

Definition at line 97 of file registers.h.

#define SCU_VIIT_STATUS_ALL_VALID
Value:
(\
SCU_VIIT_STATUS_RNC_VALID \
| SCU_VIIT_STATUS_ADDRESS_VALID \
| SCU_VIIT_STATUS_RNI_VALID \
)

Definition at line 99 of file registers.h.

#define SCU_VIIT_STATUS_RNC_VALID   (0x01 << SCU_VIIT_ENTRY_STATUS_SHIFT)

Definition at line 96 of file registers.h.

#define SCU_VIIT_STATUS_RNI_VALID   (0x04 << SCU_VIIT_ENTRY_STATUS_SHIFT)

Definition at line 98 of file registers.h.

#define SMU_CGUCR_GEN_BIT (   name)    SCU_GEN_BIT(SMU_CLOCK_GATING_CONTROL_##name)

Definition at line 391 of file registers.h.

#define SMU_CGUCR_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SMU_CLOCK_GATING_CONTROL_##name, value)

Definition at line 388 of file registers.h.

#define SMU_CLOCK_GATING_CONTROL_FORCE_IDLE_MASK   (0x80000000)

Definition at line 385 of file registers.h.

#define SMU_CLOCK_GATING_CONTROL_FORCE_IDLE_SHIFT   (31)

Definition at line 384 of file registers.h.

#define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_MASK   (0x00000001)

Definition at line 375 of file registers.h.

#define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_SHIFT   (0)

Definition at line 374 of file registers.h.

#define SMU_CLOCK_GATING_CONTROL_IDLE_TIMEOUT_MASK   (0x000F0000)

Definition at line 383 of file registers.h.

#define SMU_CLOCK_GATING_CONTROL_IDLE_TIMEOUT_SHIFT   (16)

Definition at line 382 of file registers.h.

#define SMU_CLOCK_GATING_CONTROL_REGCLK_ENABLE_MASK   (0x00000008)

Definition at line 381 of file registers.h.

#define SMU_CLOCK_GATING_CONTROL_REGCLK_ENABLE_SHIFT   (3)

Definition at line 380 of file registers.h.

#define SMU_CLOCK_GATING_CONTROL_RESERVED_MASK   (0x7FF0FFF0)

Definition at line 386 of file registers.h.

#define SMU_CLOCK_GATING_CONTROL_TXCLK_ENABLE_MASK   (0x00000004)

Definition at line 379 of file registers.h.

#define SMU_CLOCK_GATING_CONTROL_TXCLK_ENABLE_SHIFT   (2)

Definition at line 378 of file registers.h.

#define SMU_CLOCK_GATING_CONTROL_XCLK_ENABLE_MASK   (0x00000002)

Definition at line 377 of file registers.h.

#define SMU_CLOCK_GATING_CONTROL_XCLK_ENABLE_SHIFT   (1)

Definition at line 376 of file registers.h.

#define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_MASK   (0x03FF0000)

Definition at line 322 of file registers.h.

#define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_SHIFT   (16)

Definition at line 321 of file registers.h.

#define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_MASK   (0x00003FFF)

Definition at line 320 of file registers.h.

#define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_SHIFT   (0)

Definition at line 319 of file registers.h.

#define SMU_COMPLETION_QUEUE_CONTROL_RESERVED_MASK   (0xFC00C000)

Definition at line 323 of file registers.h.

#define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_MASK   (0x00008000)

Definition at line 291 of file registers.h.

#define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT   (15)

Definition at line 290 of file registers.h.

#define SMU_COMPLETION_QUEUE_GET_ENABLE_MASK   (0x40000000)

Definition at line 297 of file registers.h.

#define SMU_COMPLETION_QUEUE_GET_ENABLE_SHIFT   (30)

Definition at line 296 of file registers.h.

#define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_MASK   (0x04000000)

Definition at line 295 of file registers.h.

#define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT   (26)

Definition at line 294 of file registers.h.

#define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_MASK   (0x80000000)

Definition at line 299 of file registers.h.

#define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_SHIFT   (31)

Definition at line 298 of file registers.h.

#define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK   (0x03FF0000)

Definition at line 293 of file registers.h.

#define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT   (16)

Definition at line 292 of file registers.h.

#define SMU_COMPLETION_QUEUE_GET_POINTER_MASK   (0x00003FFF)

Definition at line 289 of file registers.h.

#define SMU_COMPLETION_QUEUE_GET_POINTER_SHIFT   (0)

Definition at line 288 of file registers.h.

#define SMU_COMPLETION_QUEUE_GET_RESERVED_MASK   (0x38004000)

Definition at line 300 of file registers.h.

#define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_MASK   (0x00008000)

Definition at line 273 of file registers.h.

#define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_SHIFT   (15)

Definition at line 272 of file registers.h.

#define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_MASK   (0x04000000)

Definition at line 277 of file registers.h.

#define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_SHIFT   (26)

Definition at line 276 of file registers.h.

#define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_MASK   (0x03FF0000)

Definition at line 275 of file registers.h.

#define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_SHIFT   (16)

Definition at line 274 of file registers.h.

#define SMU_COMPLETION_QUEUE_PUT_POINTER_MASK   (0x00003FFF)

Definition at line 271 of file registers.h.

#define SMU_COMPLETION_QUEUE_PUT_POINTER_SHIFT   (0)

Definition at line 270 of file registers.h.

#define SMU_COMPLETION_QUEUE_PUT_RESERVED_MASK   (0xF8004000)

Definition at line 278 of file registers.h.

#define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_MASK   (0x00000002)

Definition at line 399 of file registers.h.

#define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_SHIFT   (1)

Definition at line 398 of file registers.h.

#define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_MASK   (0x00010000)

Definition at line 401 of file registers.h.

#define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_SHIFT   (16)

Definition at line 400 of file registers.h.

#define SMU_CONTROL_STATUS_RESERVED_MASK   (0xFFFCFFFC)

Definition at line 404 of file registers.h.

#define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_MASK   (0x00020000)

Definition at line 403 of file registers.h.

#define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_SHIFT   (17)

Definition at line 402 of file registers.h.

#define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_MASK   (0x00000001)

Definition at line 397 of file registers.h.

#define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_SHIFT   (0)

Definition at line 396 of file registers.h.

#define SMU_CQC_EVENT_LIMIT_SET (   value)    SMU_CQC_GEN_VAL(EVENT_LIMIT, value)

Definition at line 331 of file registers.h.

#define SMU_CQC_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_CONTROL_ ## name, value)

Definition at line 325 of file registers.h.

#define SMU_CQC_QUEUE_LIMIT_SET (   value)    SMU_CQC_GEN_VAL(QUEUE_LIMIT, value)

Definition at line 328 of file registers.h.

#define SMU_CQGR_CYCLE_BIT   SMU_CQGR_GEN_BIT(CYCLE_BIT)

Definition at line 308 of file registers.h.

#define SMU_CQGR_EVENT_CYCLE_BIT   SMU_CQGR_GEN_BIT(EVENT_CYCLE_BIT)

Definition at line 311 of file registers.h.

#define SMU_CQGR_GEN_BIT (   name)    SCU_GEN_BIT(SMU_COMPLETION_QUEUE_GET_ ## name)

Definition at line 305 of file registers.h.

#define SMU_CQGR_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_GET_ ## name, value)

Definition at line 302 of file registers.h.

#define SMU_CQGR_GET_POINTER_SET (   value)    SMU_CQGR_GEN_VAL(POINTER, value)

Definition at line 314 of file registers.h.

#define SMU_CQPR_GEN_BIT (   name)    SCU_GEN_BIT(SMU_COMPLETION_QUEUE_PUT_ ## name)

Definition at line 283 of file registers.h.

#define SMU_CQPR_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_PUT_ ## name, value)

Definition at line 280 of file registers.h.

#define SMU_DCC_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SMU_DEVICE_CONTEXT_CAPACITY_ ## name, value)

Definition at line 346 of file registers.h.

#define SMU_DCC_GET_MAX_LP (   value)
Value:
(\
((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
>> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \
)

Definition at line 355 of file registers.h.

#define SMU_DCC_GET_MAX_PEG (   value)
Value:
(\
((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK) \
>> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \
)

Definition at line 349 of file registers.h.

#define SMU_DCC_GET_MAX_RNC (   value)
Value:
(\
((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
>> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT \
)

Definition at line 367 of file registers.h.

#define SMU_DCC_GET_MAX_TC (   value)
Value:
(\
((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
>> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT \
)

Definition at line 361 of file registers.h.

#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK   (0x00007000)

Definition at line 339 of file registers.h.

#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT   (12)

Definition at line 338 of file registers.h.

#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK   (0x08000000)

Definition at line 343 of file registers.h.

#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_SHIFT   (27)

Definition at line 342 of file registers.h.

#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK   (0x07FF8000)

Definition at line 341 of file registers.h.

#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT   (15)

Definition at line 340 of file registers.h.

#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK   (0x00000FFF)

Definition at line 337 of file registers.h.

#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT   (0)

Definition at line 336 of file registers.h.

#define SMU_DEVICE_CONTEXT_CAPACITY_RESERVED_MASK   (0xF0000000)

Definition at line 344 of file registers.h.

#define SMU_ICC_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SMU_INTERRUPT_COALESCING_CONTROL_ ## name, value)

Definition at line 250 of file registers.h.

#define SMU_IMR_COMPLETION   SMU_IMR_GEN_BIT(COMPLETION)

Definition at line 241 of file registers.h.

#define SMU_IMR_GEN_BIT (   name)    SCU_GEN_BIT(SMU_INTERRUPT_MASK_ ## name)

Definition at line 236 of file registers.h.

#define SMU_IMR_QUEUE_ERROR   SMU_IMR_GEN_BIT(QUEUE_ERROR)

Definition at line 239 of file registers.h.

#define SMU_IMR_QUEUE_SUSPEND   SMU_IMR_GEN_BIT(QUEUE_SUSPEND)

Definition at line 240 of file registers.h.

#define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_MASK   (0x0000FF00)

Definition at line 247 of file registers.h.

#define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_SHIFT   (8)

Definition at line 246 of file registers.h.

#define SMU_INTERRUPT_COALESCING_CONTROL_RESERVED_MASK   (0xFFFF00E0)

Definition at line 248 of file registers.h.

#define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_MASK   (0x0000001F)

Definition at line 245 of file registers.h.

#define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_SHIFT   (0)

Definition at line 244 of file registers.h.

#define SMU_INTERRUPT_MASK_COMPLETION_MASK   (0x80000000)

Definition at line 229 of file registers.h.

#define SMU_INTERRUPT_MASK_COMPLETION_SHIFT   (31)

Definition at line 228 of file registers.h.

#define SMU_INTERRUPT_MASK_QUEUE_ERROR_MASK   (0x00000001)

Definition at line 233 of file registers.h.

#define SMU_INTERRUPT_MASK_QUEUE_ERROR_SHIFT   (0)

Definition at line 232 of file registers.h.

#define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_MASK   (0x00000002)

Definition at line 231 of file registers.h.

#define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_SHIFT   (1)

Definition at line 230 of file registers.h.

#define SMU_INTERRUPT_MASK_RESERVED_MASK   (0x7FFFFFFC)

Definition at line 234 of file registers.h.

#define SMU_INTERRUPT_STATUS_COMPLETION_MASK   (0x80000000)

Definition at line 213 of file registers.h.

#define SMU_INTERRUPT_STATUS_COMPLETION_SHIFT   (31)

Definition at line 212 of file registers.h.

#define SMU_INTERRUPT_STATUS_QUEUE_ERROR_MASK   (0x00000001)

Definition at line 217 of file registers.h.

#define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT   (0)

Definition at line 216 of file registers.h.

#define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_MASK   (0x00000002)

Definition at line 215 of file registers.h.

#define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_SHIFT   (1)

Definition at line 214 of file registers.h.

#define SMU_INTERRUPT_STATUS_RESERVED_MASK   (0x7FFFFFFC)

Definition at line 218 of file registers.h.

#define SMU_ISR_COMPLETION   SMU_ISR_GEN_BIT(COMPLETION)

Definition at line 225 of file registers.h.

#define SMU_ISR_GEN_BIT (   name)    SCU_GEN_BIT(SMU_INTERRUPT_STATUS_ ## name)

Definition at line 220 of file registers.h.

#define SMU_ISR_QUEUE_ERROR   SMU_ISR_GEN_BIT(QUEUE_ERROR)

Definition at line 223 of file registers.h.

#define SMU_ISR_QUEUE_SUSPEND   SMU_ISR_GEN_BIT(QUEUE_SUSPEND)

Definition at line 224 of file registers.h.

#define SMU_PCP_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SMU_POST_CONTEXT_PORT_ ## name, value)

Definition at line 208 of file registers.h.

#define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_MASK   (0x00FC0000)

Definition at line 205 of file registers.h.

#define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_SHIFT   (18)

Definition at line 204 of file registers.h.

#define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_MASK   (0x00000FFF)

Definition at line 199 of file registers.h.

#define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT   (0)

Definition at line 198 of file registers.h.

#define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_MASK   (0x0000F000)

Definition at line 201 of file registers.h.

#define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_SHIFT   (12)

Definition at line 200 of file registers.h.

#define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_MASK   (0x00030000)

Definition at line 203 of file registers.h.

#define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_SHIFT   (16)

Definition at line 202 of file registers.h.

#define SMU_POST_CONTEXT_PORT_RESERVED_MASK   (0xFF000000)

Definition at line 206 of file registers.h.

#define SMU_RESET_ALL_PROTOCOL_ENGINE_GROUPS ( )
Value:
(\
SMU_RESET_PROTOCOL_ENGINE_GROUP(0) \
| SMU_RESET_PROTOCOL_ENGINE_GROUP(1) \
)

Definition at line 487 of file registers.h.

#define SMU_RESET_ALL_PROTOCOL_ENGINES ( )
Value:
(\
SMU_RESET_PEG_PROTOCOL_ENGINES(0) \
| SMU_RESET_PEG_PROTOCOL_ENGINES(1) \
)

Definition at line 451 of file registers.h.

#define SMU_RESET_PEG_PROTOCOL_ENGINES (   peg)
Value:
(\
SMU_RESET_PROTOCOL_ENGINE(peg, 0) \
| SMU_RESET_PROTOCOL_ENGINE(peg, 1) \
| SMU_RESET_PROTOCOL_ENGINE(peg, 2) \
| SMU_RESET_PROTOCOL_ENGINE(peg, 3) \
)

Definition at line 443 of file registers.h.

#define SMU_RESET_PROTOCOL_ENGINE (   peg,
  pe 
)    ((1 << (pe)) << ((peg) * 8))

Definition at line 440 of file registers.h.

#define SMU_RESET_PROTOCOL_ENGINE_GROUP (   peg)
Value:
(\
(1 << ((peg) + 20)) \
| SMU_RESET_WIDE_PORT_QUEUE(peg, 0) \
| SMU_RESET_WIDE_PORT_QUEUE(peg, 1) \
| SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \
)

Definition at line 479 of file registers.h.

#define SMU_RESET_SCU ( )    (0xFFFFFFFF)

Definition at line 493 of file registers.h.

#define SMU_RESET_WIDE_PORT_QUEUE (   peg,
  wide_port 
)    ((1 << ((wide_port) / 2)) << ((peg) * 2) << 16)

Definition at line 466 of file registers.h.

#define SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED   (SMU_SMUCSR_GEN_BIT(CONTEXT_RAM_INIT_COMPLETED))

Definition at line 412 of file registers.h.

#define SMU_SMUCSR_GEN_BIT (   name)    SCU_GEN_BIT(SMU_CONTROL_STATUS_ ## name)

Definition at line 406 of file registers.h.

#define SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED   (SMU_SMUCSR_GEN_BIT(SCHEDULER_RAM_INIT_COMPLETED))

Definition at line 409 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG0_MASK   (0x00100000)

Definition at line 470 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_MASK   (0x00000001)

Definition at line 424 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_SHIFT   (0)

Definition at line 423 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_MASK   (0x00000002)

Definition at line 426 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_SHIFT   (1)

Definition at line 425 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_MASK   (0x00000004)

Definition at line 428 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_SHIFT   (2)

Definition at line 427 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_MASK   (0x00000008)

Definition at line 430 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_SHIFT   (3)

Definition at line 429 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG0_SHIFT   (20)

Definition at line 469 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG1_MASK   (0x00200000)

Definition at line 472 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_MASK   (0x00000100)

Definition at line 432 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_SHIFT   (8)

Definition at line 431 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_MASK   (0x00000200)

Definition at line 434 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_SHIFT   (9)

Definition at line 433 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_MASK   (0x00000400)

Definition at line 436 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_SHIFT   (10)

Definition at line 435 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_MASK   (0x00000800)

Definition at line 438 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_SHIFT   (11)

Definition at line 437 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_PEG1_SHIFT   (21)

Definition at line 471 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_SCU_MASK   (0x00400000)

Definition at line 474 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_SCU_SHIFT   (22)

Definition at line 473 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_MASK   (0x00010000)

Definition at line 458 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_SHIFT   (16)

Definition at line 457 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_MASK   (0x00020000)

Definition at line 460 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_SHIFT   (17)

Definition at line 459 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_MASK   (0x00040000)

Definition at line 462 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_SHIFT   (18)

Definition at line 461 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_MASK   (0x00080000)

Definition at line 464 of file registers.h.

#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_SHIFT   (19)

Definition at line 463 of file registers.h.

#define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_MASK   (0x0FFF0000)

Definition at line 501 of file registers.h.

#define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_SHIFT   (16)

Definition at line 500 of file registers.h.

#define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_MASK   (0x80000000)

Definition at line 503 of file registers.h.

#define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_SHIFT   (31)

Definition at line 502 of file registers.h.

#define SMU_TASK_CONTEXT_ASSIGNMENT_RESERVED_MASK   (0x7000F000)

Definition at line 504 of file registers.h.

#define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_MASK   (0x00000FFF)

Definition at line 499 of file registers.h.

#define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_SHIFT   (0)

Definition at line 498 of file registers.h.

#define SMU_TASK_CONTEXT_RANGE_ENABLE_MASK   (0x80000000)

Definition at line 259 of file registers.h.

#define SMU_TASK_CONTEXT_RANGE_ENABLE_SHIFT   (31)

Definition at line 258 of file registers.h.

#define SMU_TASK_CONTEXT_RANGE_ENDING_MASK   (0x0FFF0000)

Definition at line 257 of file registers.h.

#define SMU_TASK_CONTEXT_RANGE_ENDING_SHIFT   (16)

Definition at line 256 of file registers.h.

#define SMU_TASK_CONTEXT_RANGE_RESERVED_MASK   (0x7000F000)

Definition at line 260 of file registers.h.

#define SMU_TASK_CONTEXT_RANGE_START_MASK   (0x00000FFF)

Definition at line 255 of file registers.h.

#define SMU_TASK_CONTEXT_RANGE_START_SHIFT   (0)

Definition at line 254 of file registers.h.

#define SMU_TCA_GEN_BIT (   name)    SCU_GEN_BIT(SMU_TASK_CONTEXT_ASSIGNMENT_ ## name)

Definition at line 509 of file registers.h.

#define SMU_TCA_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SMU_TASK_CONTEXT_ASSIGNMENT_ ## name, value)

Definition at line 506 of file registers.h.

#define SMU_TCR_GEN_BIT (   name,
  value 
)    SCU_GEN_BIT(SMU_TASK_CONTEXT_RANGE_ ## name)

Definition at line 265 of file registers.h.

#define SMU_TCR_GEN_VAL (   name,
  value 
)    SCU_GEN_VALUE(SMU_TASK_CONTEXT_RANGE_ ## name, value)

Definition at line 262 of file registers.h.

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