Linux Kernel
3.7.1
|
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/crc32.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/jiffies.h>
#include <linux/firmware.h>
#include <pcmcia/cistpl.h>
#include <pcmcia/cisreg.h>
#include <pcmcia/ciscode.h>
#include <pcmcia/ds.h>
#include <pcmcia/ss.h>
#include <asm/io.h>
#include <asm/uaccess.h>
Go to the source code of this file.
Data Structures | |
struct | smc_private |
Macros | |
#define | pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
#define | FIRMWARE_NAME "ositech/Xilinx7OD.bin" |
#define | INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0) |
#define | DRV_NAME "smc91c92_cs" |
#define | DRV_VERSION "1.123" |
#define | TX_TIMEOUT ((400*HZ)/1000) |
#define | INTR_WORK 4 |
#define | MEMORY_WAIT_TIME 8 |
#define | MEGAHERTZ_ISR 0x0380 |
#define | MOT_LAN 0x0000 |
#define | MOT_UART 0x0020 |
#define | MOT_EEPROM 0x20 |
#define | MOT_NORMAL (COR_LEVEL_REQ | COR_FUNC_ENA | COR_ADDR_DECODE | COR_IREQ_ENA) |
#define | OSITECH_AUI_CTL 0x0c |
#define | OSITECH_PWRDOWN 0x0d |
#define | OSITECH_RESET 0x0e |
#define | OSITECH_ISR 0x0f |
#define | OSITECH_AUI_PWR 0x0c |
#define | OSITECH_RESET_ISR 0x0e |
#define | OSI_AUI_PWR 0x40 |
#define | OSI_LAN_PWRDOWN 0x02 |
#define | OSI_MODEM_PWRDOWN 0x01 |
#define | OSI_LAN_RESET 0x02 |
#define | OSI_MODEM_RESET 0x01 |
#define | BANK_SELECT 14 /* Window select register. */ |
#define | SMC_SELECT_BANK(x) { outw(x, ioaddr + BANK_SELECT); } |
#define | TCR 0 /* transmit control register */ |
#define | TCR_CLEAR 0 /* do NOTHING */ |
#define | TCR_ENABLE 0x0001 /* if this is 1, we can transmit */ |
#define | TCR_PAD_EN 0x0080 /* pads short packets to 64 bytes */ |
#define | TCR_MONCSN 0x0400 /* Monitor Carrier. */ |
#define | TCR_FDUPLX 0x0800 /* Full duplex mode. */ |
#define | TCR_NORMAL TCR_ENABLE | TCR_PAD_EN |
#define | EPH 2 /* Ethernet Protocol Handler report. */ |
#define | EPH_TX_SUC 0x0001 |
#define | EPH_SNGLCOL 0x0002 |
#define | EPH_MULCOL 0x0004 |
#define | EPH_LTX_MULT 0x0008 |
#define | EPH_16COL 0x0010 |
#define | EPH_SQET 0x0020 |
#define | EPH_LTX_BRD 0x0040 |
#define | EPH_TX_DEFR 0x0080 |
#define | EPH_LAT_COL 0x0200 |
#define | EPH_LOST_CAR 0x0400 |
#define | EPH_EXC_DEF 0x0800 |
#define | EPH_CTR_ROL 0x1000 |
#define | EPH_RX_OVRN 0x2000 |
#define | EPH_LINK_OK 0x4000 |
#define | EPH_TX_UNRN 0x8000 |
#define | MEMINFO 8 /* Memory Information Register */ |
#define | MEMCFG 10 /* Memory Configuration Register */ |
#define | CONFIG 0 |
#define | CFG_MII_SELECT 0x8000 /* 91C100 only */ |
#define | CFG_NO_WAIT 0x1000 |
#define | CFG_FULL_STEP 0x0400 |
#define | CFG_SET_SQLCH 0x0200 |
#define | CFG_AUI_SELECT 0x0100 |
#define | CFG_16BIT 0x0080 |
#define | CFG_DIS_LINK 0x0040 |
#define | CFG_STATIC 0x0030 |
#define | CFG_IRQ_SEL_1 0x0004 |
#define | CFG_IRQ_SEL_0 0x0002 |
#define | BASE_ADDR 2 |
#define | ADDR0 4 |
#define | GENERAL 10 |
#define | CONTROL 12 |
#define | CTL_STORE 0x0001 |
#define | CTL_RELOAD 0x0002 |
#define | CTL_EE_SELECT 0x0004 |
#define | CTL_TE_ENABLE 0x0020 |
#define | CTL_CR_ENABLE 0x0040 |
#define | CTL_LE_ENABLE 0x0080 |
#define | CTL_AUTO_RELEASE 0x0800 |
#define | CTL_POWERDOWN 0x2000 |
#define | MMU_CMD 0 |
#define | MC_ALLOC 0x20 /* or with number of 256 byte packets */ |
#define | MC_RESET 0x40 |
#define | MC_RELEASE 0x80 /* remove and release the current rx packet */ |
#define | MC_FREEPKT 0xA0 /* Release packet in PNR register */ |
#define | MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */ |
#define | PNR_ARR 2 |
#define | FIFO_PORTS 4 |
#define | FP_RXEMPTY 0x8000 |
#define | POINTER 6 |
#define | PTR_AUTO_INC 0x0040 |
#define | PTR_READ 0x2000 |
#define | PTR_AUTOINC 0x4000 |
#define | PTR_RCV 0x8000 |
#define | DATA_1 8 |
#define | INTERRUPT 12 |
#define | IM_RCV_INT 0x1 |
#define | IM_TX_INT 0x2 |
#define | IM_TX_EMPTY_INT 0x4 |
#define | IM_ALLOC_INT 0x8 |
#define | IM_RX_OVRN_INT 0x10 |
#define | IM_EPH_INT 0x20 |
#define | RCR 4 |
#define | RCR_SOFTRESET 0x8000 /* resets the chip */ |
#define | RCR_STRIP_CRC 0x200 /* strips CRC */ |
#define | RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */ |
#define | RCR_ALMUL 0x4 /* receive all multicast packets */ |
#define | RCR_PROMISC 0x2 /* enable promiscuous mode */ |
#define | RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE) |
#define | RCR_CLEAR 0x0 /* set it to a base state */ |
#define | COUNTER 6 |
#define | MULTICAST0 0 |
#define | MULTICAST2 2 |
#define | MULTICAST4 4 |
#define | MULTICAST6 6 |
#define | MGMT 8 |
#define | REVISION 0x0a |
#define | TS_SUCCESS 0x0001 |
#define | TS_16COL 0x0010 |
#define | TS_LATCOL 0x0200 |
#define | TS_LOSTCAR 0x0400 |
#define | RS_ALGNERR 0x8000 |
#define | RS_BADCRC 0x2000 |
#define | RS_ODDFRAME 0x1000 |
#define | RS_TOOLONG 0x0800 |
#define | RS_TOOSHORT 0x0400 |
#define | RS_MULTICAST 0x0001 |
#define | RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) |
#define | set_bits(v, p) outw(inw(p)|(v), (p)) |
#define | mask_bits(v, p) outw(inw(p)&(v), (p)) |
#define | MDIO_SHIFT_CLK 0x04 |
#define | MDIO_DATA_OUT 0x01 |
#define | MDIO_DIR_WRITE 0x08 |
#define | MDIO_DATA_WRITE0 (MDIO_DIR_WRITE) |
#define | MDIO_DATA_WRITE1 (MDIO_DIR_WRITE | MDIO_DATA_OUT) |
#define | MDIO_DATA_READ 0x02 |
Enumerations | |
enum | RxCfg { RxAllMulti = 0x0004, RxPromisc = 0x0002, RxEnable = 0x0100, RxStripCRC = 0x0200 } |
Functions | |
MODULE_DESCRIPTION ("SMC 91c92 series PCMCIA ethernet driver") | |
MODULE_LICENSE ("GPL") | |
MODULE_FIRMWARE (FIRMWARE_NAME) | |
INT_MODULE_PARM (if_port, 0) | |
MODULE_DEVICE_TABLE (pcmcia, smc91c92_ids) | |
module_init (init_smc91c92_cs) | |
module_exit (exit_smc91c92_cs) | |
#define ADDR0 4 |
Definition at line 189 of file smc91c92_cs.c.
#define BANK_SELECT 14 /* Window select register. */ |
Definition at line 145 of file smc91c92_cs.c.
#define BASE_ADDR 2 |
Definition at line 188 of file smc91c92_cs.c.
#define CFG_16BIT 0x0080 |
Definition at line 183 of file smc91c92_cs.c.
#define CFG_AUI_SELECT 0x0100 |
Definition at line 182 of file smc91c92_cs.c.
#define CFG_DIS_LINK 0x0040 |
Definition at line 184 of file smc91c92_cs.c.
#define CFG_FULL_STEP 0x0400 |
Definition at line 180 of file smc91c92_cs.c.
#define CFG_IRQ_SEL_0 0x0002 |
Definition at line 187 of file smc91c92_cs.c.
#define CFG_IRQ_SEL_1 0x0004 |
Definition at line 186 of file smc91c92_cs.c.
#define CFG_MII_SELECT 0x8000 /* 91C100 only */ |
Definition at line 178 of file smc91c92_cs.c.
#define CFG_NO_WAIT 0x1000 |
Definition at line 179 of file smc91c92_cs.c.
#define CFG_SET_SQLCH 0x0200 |
Definition at line 181 of file smc91c92_cs.c.
#define CFG_STATIC 0x0030 |
Definition at line 185 of file smc91c92_cs.c.
#define CONFIG 0 |
Definition at line 177 of file smc91c92_cs.c.
#define CONTROL 12 |
Definition at line 191 of file smc91c92_cs.c.
#define COUNTER 6 |
Definition at line 237 of file smc91c92_cs.c.
#define CTL_AUTO_RELEASE 0x0800 |
Definition at line 198 of file smc91c92_cs.c.
#define CTL_CR_ENABLE 0x0040 |
Definition at line 196 of file smc91c92_cs.c.
#define CTL_EE_SELECT 0x0004 |
Definition at line 194 of file smc91c92_cs.c.
#define CTL_LE_ENABLE 0x0080 |
Definition at line 197 of file smc91c92_cs.c.
#define CTL_POWERDOWN 0x2000 |
Definition at line 199 of file smc91c92_cs.c.
#define CTL_RELOAD 0x0002 |
Definition at line 193 of file smc91c92_cs.c.
#define CTL_STORE 0x0001 |
Definition at line 192 of file smc91c92_cs.c.
#define CTL_TE_ENABLE 0x0020 |
Definition at line 195 of file smc91c92_cs.c.
#define DATA_1 8 |
Definition at line 216 of file smc91c92_cs.c.
#define DRV_NAME "smc91c92_cs" |
Definition at line 82 of file smc91c92_cs.c.
#define DRV_VERSION "1.123" |
Definition at line 83 of file smc91c92_cs.c.
Definition at line 157 of file smc91c92_cs.c.
#define EPH_16COL 0x0010 |
Definition at line 162 of file smc91c92_cs.c.
#define EPH_CTR_ROL 0x1000 |
Definition at line 169 of file smc91c92_cs.c.
#define EPH_EXC_DEF 0x0800 |
Definition at line 168 of file smc91c92_cs.c.
#define EPH_LAT_COL 0x0200 |
Definition at line 166 of file smc91c92_cs.c.
#define EPH_LINK_OK 0x4000 |
Definition at line 171 of file smc91c92_cs.c.
#define EPH_LOST_CAR 0x0400 |
Definition at line 167 of file smc91c92_cs.c.
#define EPH_LTX_BRD 0x0040 |
Definition at line 164 of file smc91c92_cs.c.
#define EPH_LTX_MULT 0x0008 |
Definition at line 161 of file smc91c92_cs.c.
#define EPH_MULCOL 0x0004 |
Definition at line 160 of file smc91c92_cs.c.
#define EPH_RX_OVRN 0x2000 |
Definition at line 170 of file smc91c92_cs.c.
#define EPH_SNGLCOL 0x0002 |
Definition at line 159 of file smc91c92_cs.c.
#define EPH_SQET 0x0020 |
Definition at line 163 of file smc91c92_cs.c.
#define EPH_TX_DEFR 0x0080 |
Definition at line 165 of file smc91c92_cs.c.
#define EPH_TX_SUC 0x0001 |
Definition at line 158 of file smc91c92_cs.c.
#define EPH_TX_UNRN 0x8000 |
Definition at line 172 of file smc91c92_cs.c.
#define FIFO_PORTS 4 |
Definition at line 209 of file smc91c92_cs.c.
#define FIRMWARE_NAME "ositech/Xilinx7OD.bin" |
Definition at line 63 of file smc91c92_cs.c.
#define FP_RXEMPTY 0x8000 |
Definition at line 210 of file smc91c92_cs.c.
#define GENERAL 10 |
Definition at line 190 of file smc91c92_cs.c.
#define IM_ALLOC_INT 0x8 |
Definition at line 221 of file smc91c92_cs.c.
#define IM_EPH_INT 0x20 |
Definition at line 223 of file smc91c92_cs.c.
#define IM_RCV_INT 0x1 |
Definition at line 218 of file smc91c92_cs.c.
#define IM_RX_OVRN_INT 0x10 |
Definition at line 222 of file smc91c92_cs.c.
#define IM_TX_EMPTY_INT 0x4 |
Definition at line 220 of file smc91c92_cs.c.
#define IM_TX_INT 0x2 |
Definition at line 219 of file smc91c92_cs.c.
Definition at line 71 of file smc91c92_cs.c.
#define INTERRUPT 12 |
Definition at line 217 of file smc91c92_cs.c.
#define INTR_WORK 4 |
Definition at line 93 of file smc91c92_cs.c.
#define MC_ALLOC 0x20 /* or with number of 256 byte packets */ |
Definition at line 203 of file smc91c92_cs.c.
#define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */ |
Definition at line 207 of file smc91c92_cs.c.
#define MC_FREEPKT 0xA0 /* Release packet in PNR register */ |
Definition at line 206 of file smc91c92_cs.c.
#define MC_RELEASE 0x80 /* remove and release the current rx packet */ |
Definition at line 205 of file smc91c92_cs.c.
#define MC_RESET 0x40 |
Definition at line 204 of file smc91c92_cs.c.
#define MDIO_DATA_OUT 0x01 |
Definition at line 971 of file smc91c92_cs.c.
#define MDIO_DATA_READ 0x02 |
Definition at line 975 of file smc91c92_cs.c.
#define MDIO_DATA_WRITE0 (MDIO_DIR_WRITE) |
Definition at line 973 of file smc91c92_cs.c.
#define MDIO_DATA_WRITE1 (MDIO_DIR_WRITE | MDIO_DATA_OUT) |
Definition at line 974 of file smc91c92_cs.c.
#define MDIO_DIR_WRITE 0x08 |
Definition at line 972 of file smc91c92_cs.c.
#define MDIO_SHIFT_CLK 0x04 |
Definition at line 970 of file smc91c92_cs.c.
#define MEGAHERTZ_ISR 0x0380 |
Definition at line 120 of file smc91c92_cs.c.
#define MEMCFG 10 /* Memory Configuration Register */ |
Definition at line 174 of file smc91c92_cs.c.
#define MEMINFO 8 /* Memory Information Register */ |
Definition at line 173 of file smc91c92_cs.c.
#define MEMORY_WAIT_TIME 8 |
Definition at line 97 of file smc91c92_cs.c.
#define MGMT 8 |
Definition at line 244 of file smc91c92_cs.c.
#define MMU_CMD 0 |
Definition at line 202 of file smc91c92_cs.c.
#define MOT_EEPROM 0x20 |
Definition at line 125 of file smc91c92_cs.c.
#define MOT_LAN 0x0000 |
Definition at line 123 of file smc91c92_cs.c.
#define MOT_NORMAL (COR_LEVEL_REQ | COR_FUNC_ENA | COR_ADDR_DECODE | COR_IREQ_ENA) |
Definition at line 127 of file smc91c92_cs.c.
#define MOT_UART 0x0020 |
Definition at line 124 of file smc91c92_cs.c.
#define MULTICAST0 0 |
Definition at line 240 of file smc91c92_cs.c.
#define MULTICAST2 2 |
Definition at line 241 of file smc91c92_cs.c.
#define MULTICAST4 4 |
Definition at line 242 of file smc91c92_cs.c.
#define MULTICAST6 6 |
Definition at line 243 of file smc91c92_cs.c.
#define OSI_AUI_PWR 0x40 |
Definition at line 138 of file smc91c92_cs.c.
#define OSI_LAN_PWRDOWN 0x02 |
Definition at line 139 of file smc91c92_cs.c.
#define OSI_LAN_RESET 0x02 |
Definition at line 141 of file smc91c92_cs.c.
#define OSI_MODEM_PWRDOWN 0x01 |
Definition at line 140 of file smc91c92_cs.c.
#define OSI_MODEM_RESET 0x01 |
Definition at line 142 of file smc91c92_cs.c.
#define OSITECH_AUI_CTL 0x0c |
Definition at line 131 of file smc91c92_cs.c.
#define OSITECH_AUI_PWR 0x0c |
Definition at line 135 of file smc91c92_cs.c.
#define OSITECH_ISR 0x0f |
Definition at line 134 of file smc91c92_cs.c.
#define OSITECH_PWRDOWN 0x0d |
Definition at line 132 of file smc91c92_cs.c.
#define OSITECH_RESET 0x0e |
Definition at line 133 of file smc91c92_cs.c.
#define OSITECH_RESET_ISR 0x0e |
Definition at line 136 of file smc91c92_cs.c.
#define PNR_ARR 2 |
Definition at line 208 of file smc91c92_cs.c.
#define POINTER 6 |
Definition at line 211 of file smc91c92_cs.c.
Definition at line 28 of file smc91c92_cs.c.
#define PTR_AUTO_INC 0x0040 |
Definition at line 212 of file smc91c92_cs.c.
#define PTR_AUTOINC 0x4000 |
Definition at line 214 of file smc91c92_cs.c.
#define PTR_RCV 0x8000 |
Definition at line 215 of file smc91c92_cs.c.
#define PTR_READ 0x2000 |
Definition at line 213 of file smc91c92_cs.c.
#define RCR 4 |
Definition at line 225 of file smc91c92_cs.c.
#define RCR_ALMUL 0x4 /* receive all multicast packets */ |
Definition at line 231 of file smc91c92_cs.c.
#define RCR_CLEAR 0x0 /* set it to a base state */ |
Definition at line 236 of file smc91c92_cs.c.
#define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */ |
Definition at line 230 of file smc91c92_cs.c.
#define RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE) |
Definition at line 235 of file smc91c92_cs.c.
#define RCR_PROMISC 0x2 /* enable promiscuous mode */ |
Definition at line 232 of file smc91c92_cs.c.
#define RCR_SOFTRESET 0x8000 /* resets the chip */ |
Definition at line 228 of file smc91c92_cs.c.
#define RCR_STRIP_CRC 0x200 /* strips CRC */ |
Definition at line 229 of file smc91c92_cs.c.
#define REVISION 0x0a |
Definition at line 245 of file smc91c92_cs.c.
#define RS_ALGNERR 0x8000 |
Definition at line 254 of file smc91c92_cs.c.
#define RS_BADCRC 0x2000 |
Definition at line 255 of file smc91c92_cs.c.
#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) |
Definition at line 260 of file smc91c92_cs.c.
#define RS_MULTICAST 0x0001 |
Definition at line 259 of file smc91c92_cs.c.
#define RS_ODDFRAME 0x1000 |
Definition at line 256 of file smc91c92_cs.c.
#define RS_TOOLONG 0x0800 |
Definition at line 257 of file smc91c92_cs.c.
#define RS_TOOSHORT 0x0400 |
Definition at line 258 of file smc91c92_cs.c.
#define SMC_SELECT_BANK | ( | x | ) | { outw(x, ioaddr + BANK_SELECT); } |
Definition at line 146 of file smc91c92_cs.c.
#define TCR 0 /* transmit control register */ |
Definition at line 149 of file smc91c92_cs.c.
#define TCR_CLEAR 0 /* do NOTHING */ |
Definition at line 150 of file smc91c92_cs.c.
#define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */ |
Definition at line 151 of file smc91c92_cs.c.
#define TCR_FDUPLX 0x0800 /* Full duplex mode. */ |
Definition at line 154 of file smc91c92_cs.c.
#define TCR_MONCSN 0x0400 /* Monitor Carrier. */ |
Definition at line 153 of file smc91c92_cs.c.
#define TCR_NORMAL TCR_ENABLE | TCR_PAD_EN |
Definition at line 155 of file smc91c92_cs.c.
#define TCR_PAD_EN 0x0080 /* pads short packets to 64 bytes */ |
Definition at line 152 of file smc91c92_cs.c.
#define TS_16COL 0x0010 |
Definition at line 249 of file smc91c92_cs.c.
#define TS_LATCOL 0x0200 |
Definition at line 250 of file smc91c92_cs.c.
#define TS_LOSTCAR 0x0400 |
Definition at line 251 of file smc91c92_cs.c.
#define TS_SUCCESS 0x0001 |
Definition at line 248 of file smc91c92_cs.c.
#define TX_TIMEOUT ((400*HZ)/1000) |
Definition at line 90 of file smc91c92_cs.c.
enum RxCfg |
Definition at line 226 of file smc91c92_cs.c.
INT_MODULE_PARM | ( | if_port | , |
0 | |||
) |
MODULE_DESCRIPTION | ( | "SMC 91c92 series PCMCIA ethernet driver" | ) |
MODULE_DEVICE_TABLE | ( | pcmcia | , |
smc91c92_ids | |||
) |
module_exit | ( | exit_smc91c92_cs | ) |
MODULE_FIRMWARE | ( | FIRMWARE_NAME | ) |
module_init | ( | init_smc91c92_cs | ) |
MODULE_LICENSE | ( | "GPL" | ) |