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drxk_hard.h
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1 #include "drxk_map.h"
2 
3 #define DRXK_VERSION_MAJOR 0
4 #define DRXK_VERSION_MINOR 9
5 #define DRXK_VERSION_PATCH 4300
6 
7 #define HI_I2C_DELAY 42
8 #define HI_I2C_BRIDGE_DELAY 350
9 #define DRXK_MAX_RETRIES 100
10 
11 #define DRIVER_4400 1
12 
13 #define DRXX_JTAGID 0x039210D9
14 #define DRXX_J_JTAGID 0x239310D9
15 #define DRXX_K_JTAGID 0x039210D9
16 
17 #define DRX_UNKNOWN 254
18 #define DRX_AUTO 255
19 
20 #define DRX_SCU_READY 0
21 #define DRXK_MAX_WAITTIME (200)
22 #define SCU_RESULT_OK 0
23 #define SCU_RESULT_SIZE -4
24 #define SCU_RESULT_INVPAR -3
25 #define SCU_RESULT_UNKSTD -2
26 #define SCU_RESULT_UNKCMD -1
27 
28 #ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT
29 #define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200)
30 #endif
31 
32 #define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/
33 #define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/
34 #define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/
35 #define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/
36 #define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/
37 #define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/
38 #define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/
39 #define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/
40 
41 #define IQM_CF_OUT_ENA_OFDM__M 0x4
42 #define IQM_FS_ADJ_SEL_B_QAM 0x1
43 #define IQM_FS_ADJ_SEL_B_OFF 0x0
44 #define IQM_FS_ADJ_SEL_B_VSB 0x2
45 #define IQM_RC_ADJ_SEL_B_OFF 0x0
46 #define IQM_RC_ADJ_SEL_B_QAM 0x1
47 #define IQM_RC_ADJ_SEL_B_VSB 0x2
48 
49 enum OperationMode {
50  OM_NONE,
51  OM_QAM_ITU_A,
52  OM_QAM_ITU_B,
53  OM_QAM_ITU_C,
54  OM_DVBT
55 };
56 
57 enum DRXPowerMode {
58  DRX_POWER_UP = 0,
59  DRX_POWER_MODE_1,
60  DRX_POWER_MODE_2,
61  DRX_POWER_MODE_3,
62  DRX_POWER_MODE_4,
63  DRX_POWER_MODE_5,
64  DRX_POWER_MODE_6,
65  DRX_POWER_MODE_7,
66  DRX_POWER_MODE_8,
67 
68  DRX_POWER_MODE_9,
69  DRX_POWER_MODE_10,
70  DRX_POWER_MODE_11,
71  DRX_POWER_MODE_12,
72  DRX_POWER_MODE_13,
73  DRX_POWER_MODE_14,
74  DRX_POWER_MODE_15,
75  DRX_POWER_MODE_16,
76  DRX_POWER_DOWN = 255
77 };
78 
79 
81 #ifndef DRXK_POWER_DOWN_OFDM
82 #define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1
83 #endif
84 
86 #ifndef DRXK_POWER_DOWN_CORE
87 #define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9
88 #endif
89 
91 #ifndef DRXK_POWER_DOWN_PLL
92 #define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10
93 #endif
94 
95 
96 enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF };
97 enum EDrxkState {
98  DRXK_UNINITIALIZED = 0,
99  DRXK_STOPPED,
100  DRXK_DTV_STARTED,
101  DRXK_ATV_STARTED,
102  DRXK_POWERED_DOWN,
103  DRXK_NO_DEV /* If drxk init failed */
104 };
105 
106 enum EDrxkCoefArrayIndex {
107  DRXK_COEF_IDX_MN = 0,
108  DRXK_COEF_IDX_FM ,
109  DRXK_COEF_IDX_L ,
110  DRXK_COEF_IDX_LP ,
111  DRXK_COEF_IDX_BG ,
112  DRXK_COEF_IDX_DK ,
113  DRXK_COEF_IDX_I ,
114  DRXK_COEF_IDX_MAX
115 };
116 enum EDrxkSifAttenuation {
117  DRXK_SIF_ATTENUATION_0DB,
118  DRXK_SIF_ATTENUATION_3DB,
119  DRXK_SIF_ATTENUATION_6DB,
120  DRXK_SIF_ATTENUATION_9DB
121 };
122 enum EDrxkConstellation {
123  DRX_CONSTELLATION_BPSK = 0,
124  DRX_CONSTELLATION_QPSK,
125  DRX_CONSTELLATION_PSK8,
126  DRX_CONSTELLATION_QAM16,
127  DRX_CONSTELLATION_QAM32,
128  DRX_CONSTELLATION_QAM64,
129  DRX_CONSTELLATION_QAM128,
130  DRX_CONSTELLATION_QAM256,
131  DRX_CONSTELLATION_QAM512,
132  DRX_CONSTELLATION_QAM1024,
133  DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
134  DRX_CONSTELLATION_AUTO = DRX_AUTO
135 };
136 enum EDrxkInterleaveMode {
137  DRXK_QAM_I12_J17 = 16,
138  DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN
139 };
140 enum {
141  DRXK_SPIN_A1 = 0,
142  DRXK_SPIN_A2,
143  DRXK_SPIN_A3,
144  DRXK_SPIN_UNKNOWN
145 };
146 
147 enum DRXKCfgDvbtSqiSpeed {
148  DRXK_DVBT_SQI_SPEED_FAST = 0,
149  DRXK_DVBT_SQI_SPEED_MEDIUM,
150  DRXK_DVBT_SQI_SPEED_SLOW,
151  DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
152 } ;
153 
154 enum DRXFftmode_t {
155  DRX_FFTMODE_2K = 0,
156  DRX_FFTMODE_4K,
157  DRX_FFTMODE_8K,
158  DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
159  DRX_FFTMODE_AUTO = DRX_AUTO
160 };
161 
162 enum DRXMPEGStrWidth_t {
163  DRX_MPEG_STR_WIDTH_1,
164  DRX_MPEG_STR_WIDTH_8
165 };
166 
167 enum DRXQamLockRange_t {
168  DRX_QAM_LOCKRANGE_NORMAL,
169  DRX_QAM_LOCKRANGE_EXTENDED
170 };
171 
172 struct DRXKCfgDvbtEchoThres_t {
173  u16 threshold;
174  enum DRXFftmode_t fftMode;
175 } ;
176 
177 struct SCfgAgc {
178  enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */
179  u16 outputLevel; /* range dependent on AGC */
180  u16 minOutputLevel; /* range dependent on AGC */
181  u16 maxOutputLevel; /* range dependent on AGC */
182  u16 speed; /* range dependent on AGC */
183  u16 top; /* rf-agc take over point */
184  u16 cutOffCurrent; /* rf-agc is accelerated if output current
185  is below cut-off current */
186  u16 IngainTgtMax;
187  u16 FastClipCtrlDelay;
188 };
189 
190 struct SCfgPreSaw {
191  u16 reference; /* pre SAW reference value, range 0 .. 31 */
192  bool usePreSaw; /* TRUE algorithms must use pre SAW sense */
193 };
194 
195 struct DRXKOfdmScCmd_t {
196  u16 cmd;
197  u16 subcmd;
198  u16 param0;
199  u16 param1;
200  u16 param2;
201  u16 param3;
202  u16 param4;
203 };
204 
205 struct drxk_state {
206  struct dvb_frontend frontend;
207  struct dtv_frontend_properties props;
208  struct device *dev;
209 
210  struct i2c_adapter *i2c;
211  u8 demod_address;
212  void *priv;
213 
214  struct mutex mutex;
215 
216  u32 m_Instance;
218  int m_ChunkSize;
219  u8 Chunk[256];
220 
221  bool m_hasLNA;
222  bool m_hasDVBT;
223  bool m_hasDVBC;
224  bool m_hasAudio;
225  bool m_hasATV;
226  bool m_hasOOB;
227  bool m_hasSAWSW;
228  bool m_hasGPIO1;
229  bool m_hasGPIO2;
230  bool m_hasIRQN;
231  u16 m_oscClockFreq;
232  u16 m_HICfgTimingDiv;
233  u16 m_HICfgBridgeDelay;
234  u16 m_HICfgWakeUpKey;
235  u16 m_HICfgTimeout;
236  u16 m_HICfgCtrl;
237  s32 m_sysClockFreq;
239  enum EDrxkState m_DrxkState;
240  enum OperationMode m_OperationMode;
241  struct SCfgAgc m_vsbRfAgcCfg;
242  struct SCfgAgc m_vsbIfAgcCfg;
243  u16 m_vsbPgaCfg;
244  struct SCfgPreSaw m_vsbPreSawCfg;
245  s32 m_Quality83percent;
246  s32 m_Quality93percent;
247  bool m_smartAntInverted;
248  bool m_bDebugEnableBridge;
249  bool m_bPDownOpenBridge;
250  bool m_bPowerDown;
252  u32 m_IqmFsRateOfs;
254  bool m_enableMPEGOutput;
255  bool m_insertRSByte;
256  bool m_enableParallel;
257  bool m_invertDATA;
258  bool m_invertERR;
259  bool m_invertSTR;
260  bool m_invertVAL;
261  bool m_invertCLK;
262  bool m_DVBCStaticCLK;
263  bool m_DVBTStaticCLK;
266  u32 m_DVBTBitrate;
267  u32 m_DVBCBitrate;
268 
269  u8 m_TSDataStrength;
270  u8 m_TSClockkStrength;
271 
272  bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */
273 
274  enum DRXMPEGStrWidth_t m_widthSTR;
275  u32 m_mpegTsStaticBitrate;
278  /* LARGE_INTEGER m_StartTime; */
279  s32 m_MpegLockTimeOut;
280  s32 m_DemodLockTimeOut;
282  bool m_disableTEIhandling;
283 
284  bool m_RfAgcPol;
285  bool m_IfAgcPol;
286 
287  struct SCfgAgc m_atvRfAgcCfg;
288  struct SCfgAgc m_atvIfAgcCfg;
289  struct SCfgPreSaw m_atvPreSawCfg;
290  bool m_phaseCorrectionBypass;
291  s16 m_atvTopVidPeak;
292  u16 m_atvTopNoiseTh;
293  enum EDrxkSifAttenuation m_sifAttenuation;
294  bool m_enableCVBSOutput;
295  bool m_enableSIFOutput;
296  bool m_bMirrorFreqSpect;
297  enum EDrxkConstellation m_Constellation;
298  u32 m_CurrSymbolRate;
299  struct SCfgAgc m_qamRfAgcCfg;
300  struct SCfgAgc m_qamIfAgcCfg;
301  u16 m_qamPgaCfg;
302  struct SCfgPreSaw m_qamPreSawCfg;
303  enum EDrxkInterleaveMode m_qamInterleaveMode;
304  u16 m_fecRsPlen;
305  u16 m_fecRsPrescale;
306 
307  enum DRXKCfgDvbtSqiSpeed m_sqiSpeed;
308 
309  u16 m_GPIO;
310  u16 m_GPIOCfg;
311 
312  struct SCfgAgc m_dvbtRfAgcCfg;
313  struct SCfgAgc m_dvbtIfAgcCfg;
314  struct SCfgPreSaw m_dvbtPreSawCfg;
316  u16 m_agcFastClipCtrlDelay;
317  bool m_adcCompPassed;
318  u16 m_adcCompCoef[64];
319  u16 m_adcState;
320 
321  u8 *m_microcode;
322  int m_microcode_length;
323  bool m_DRXK_A1_PATCH_CODE;
324  bool m_DRXK_A1_ROM_CODE;
325  bool m_DRXK_A2_ROM_CODE;
326  bool m_DRXK_A3_ROM_CODE;
327  bool m_DRXK_A2_PATCH_CODE;
328  bool m_DRXK_A3_PATCH_CODE;
329 
330  bool m_rfmirror;
331  u8 m_deviceSpin;
332  u32 m_iqmRcRate;
333 
334  enum DRXPowerMode m_currentPowerMode;
335 
336  /* when true, avoids other devices to use the I2C bus */
337  bool drxk_i2c_exclusive_lock;
338 
339  /*
340  * Configurable parameters at the driver. They stores the values found
341  * at struct drxk_config.
342  */
343 
344  u16 UIO_mask; /* Bits used by UIO */
345 
346  bool enable_merr_cfg;
347  bool single_master;
348  bool no_i2c_bridge;
349  bool antenna_dvbt;
350  u16 antenna_gpio;
351 
352  /* Firmware */
353  const char *microcode_name;
354  struct completion fw_wait_load;
355  const struct firmware *fw;
356  int qam_demod_parameter_count;
357 };
358 
359 #define NEVER_LOCK 0
360 #define NOT_LOCKED 1
361 #define DEMOD_LOCK 2
362 #define FEC_LOCK 3
363 #define MPEG_LOCK 4
364 
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