33 #define NS2501_VID 0x1305
34 #define NS2501_DID 0x6726
36 #define NS2501_VID_LO 0x00
37 #define NS2501_VID_HI 0x01
38 #define NS2501_DID_LO 0x02
39 #define NS2501_DID_HI 0x03
40 #define NS2501_REV 0x04
41 #define NS2501_RSVD 0x05
42 #define NS2501_FREQ_LO 0x06
43 #define NS2501_FREQ_HI 0x07
45 #define NS2501_REG8 0x08
46 #define NS2501_8_VEN (1<<5)
47 #define NS2501_8_HEN (1<<4)
48 #define NS2501_8_DSEL (1<<3)
49 #define NS2501_8_BPAS (1<<2)
50 #define NS2501_8_RSVD (1<<1)
51 #define NS2501_8_PD (1<<0)
53 #define NS2501_REG9 0x09
54 #define NS2501_9_VLOW (1<<7)
55 #define NS2501_9_MSEL_MASK (0x7<<4)
56 #define NS2501_9_TSEL (1<<3)
57 #define NS2501_9_RSEN (1<<2)
58 #define NS2501_9_RSVD (1<<1)
59 #define NS2501_9_MDI (1<<0)
61 #define NS2501_REGC 0x0c
75 #define NSPTR(d) ((NS2501Ptr)(d->DriverPrivate.ptr))
99 DRM_DEBUG_KMS(
"%s: Trying to re-enable the DVO\n",
__FUNCTION__);
171 (
"Unable to read register 0x%02x from %s:0x%02x.\n", addr,
205 DRM_DEBUG_KMS(
"Unable to write register 0x%02x to %s:%d\n",
237 DRM_DEBUG_KMS(
"ns2501 not detected got %d: from %s Slave %d.\n",
246 DRM_DEBUG_KMS(
"ns2501 not detected got %d: from %s Slave %d.\n",
255 DRM_DEBUG_KMS(
"init ns2501 dvo controller successfully!\n");
279 (
"%s: is mode valid (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d)\n",
303 bool restore =
false;
307 (
"%s: set mode (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d).\n",
323 DRM_DEBUG_KMS(
"%s: switching to 800x600\n",
333 ok &= ns2501_writeb(dvo, 0x11, 0xc8);
334 ok &= ns2501_writeb(dvo, 0x1b, 0x19);
335 ok &= ns2501_writeb(dvo, 0x1c, 0x62);
336 ok &= ns2501_writeb(dvo, 0x1d, 0x02);
338 ok &= ns2501_writeb(dvo, 0x34, 0x03);
339 ok &= ns2501_writeb(dvo, 0x35, 0xff);
341 ok &= ns2501_writeb(dvo, 0x80, 0x27);
342 ok &= ns2501_writeb(dvo, 0x81, 0x03);
343 ok &= ns2501_writeb(dvo, 0x82, 0x41);
344 ok &= ns2501_writeb(dvo, 0x83, 0x05);
346 ok &= ns2501_writeb(dvo, 0x8d, 0x02);
347 ok &= ns2501_writeb(dvo, 0x8e, 0x04);
348 ok &= ns2501_writeb(dvo, 0x8f, 0x00);
350 ok &= ns2501_writeb(dvo, 0x90, 0xfe);
351 ok &= ns2501_writeb(dvo, 0x91, 0x07);
352 ok &= ns2501_writeb(dvo, 0x94, 0x00);
353 ok &= ns2501_writeb(dvo, 0x95, 0x00);
355 ok &= ns2501_writeb(dvo, 0x96, 0x00);
357 ok &= ns2501_writeb(dvo, 0x99, 0x00);
358 ok &= ns2501_writeb(dvo, 0x9a, 0x88);
360 ok &= ns2501_writeb(dvo, 0x9c, 0x23);
361 ok &= ns2501_writeb(dvo, 0x9d, 0x00);
362 ok &= ns2501_writeb(dvo, 0x9e, 0x25);
363 ok &= ns2501_writeb(dvo, 0x9f, 0x03);
365 ok &= ns2501_writeb(dvo, 0xa4, 0x80);
367 ok &= ns2501_writeb(dvo, 0xb6, 0x00);
369 ok &= ns2501_writeb(dvo, 0xb9, 0xc8);
370 ok &= ns2501_writeb(dvo, 0xba, 0x00);
372 ok &= ns2501_writeb(dvo, 0xc0, 0x05);
373 ok &= ns2501_writeb(dvo, 0xc1, 0xd7);
375 ok &= ns2501_writeb(dvo, 0xc2, 0x00);
376 ok &= ns2501_writeb(dvo, 0xc3, 0xf8);
378 ok &= ns2501_writeb(dvo, 0xc4, 0x03);
379 ok &= ns2501_writeb(dvo, 0xc5, 0x1a);
381 ok &= ns2501_writeb(dvo, 0xc6, 0x00);
382 ok &= ns2501_writeb(dvo, 0xc7, 0x73);
383 ok &= ns2501_writeb(dvo, 0xc8, 0x02);
387 DRM_DEBUG_KMS(
"%s: switching to 640x480\n",
398 ok &= ns2501_writeb(dvo, 0x11, 0xa0);
399 ok &= ns2501_writeb(dvo, 0x1b, 0x11);
400 ok &= ns2501_writeb(dvo, 0x1c, 0x54);
401 ok &= ns2501_writeb(dvo, 0x1d, 0x03);
403 ok &= ns2501_writeb(dvo, 0x34, 0x03);
404 ok &= ns2501_writeb(dvo, 0x35, 0xff);
406 ok &= ns2501_writeb(dvo, 0x80, 0xff);
407 ok &= ns2501_writeb(dvo, 0x81, 0x07);
408 ok &= ns2501_writeb(dvo, 0x82, 0x3d);
409 ok &= ns2501_writeb(dvo, 0x83, 0x05);
411 ok &= ns2501_writeb(dvo, 0x8d, 0x02);
412 ok &= ns2501_writeb(dvo, 0x8e, 0x10);
413 ok &= ns2501_writeb(dvo, 0x8f, 0x00);
415 ok &= ns2501_writeb(dvo, 0x90, 0xff);
416 ok &= ns2501_writeb(dvo, 0x91, 0x07);
417 ok &= ns2501_writeb(dvo, 0x94, 0x00);
418 ok &= ns2501_writeb(dvo, 0x95, 0x00);
420 ok &= ns2501_writeb(dvo, 0x96, 0x05);
422 ok &= ns2501_writeb(dvo, 0x99, 0x00);
423 ok &= ns2501_writeb(dvo, 0x9a, 0x88);
425 ok &= ns2501_writeb(dvo, 0x9c, 0x24);
426 ok &= ns2501_writeb(dvo, 0x9d, 0x00);
427 ok &= ns2501_writeb(dvo, 0x9e, 0x25);
428 ok &= ns2501_writeb(dvo, 0x9f, 0x03);
430 ok &= ns2501_writeb(dvo, 0xa4, 0x84);
432 ok &= ns2501_writeb(dvo, 0xb6, 0x09);
434 ok &= ns2501_writeb(dvo, 0xb9, 0xa0);
435 ok &= ns2501_writeb(dvo, 0xba, 0x00);
437 ok &= ns2501_writeb(dvo, 0xc0, 0x05);
438 ok &= ns2501_writeb(dvo, 0xc1, 0x90);
440 ok &= ns2501_writeb(dvo, 0xc2, 0x00);
441 ok &= ns2501_writeb(dvo, 0xc3, 0x0f);
443 ok &= ns2501_writeb(dvo, 0xc4, 0x03);
444 ok &= ns2501_writeb(dvo, 0xc5, 0x16);
446 ok &= ns2501_writeb(dvo, 0xc6, 0x00);
447 ok &= ns2501_writeb(dvo, 0xc7, 0x02);
448 ok &= ns2501_writeb(dvo, 0xc8, 0x02);
452 DRM_DEBUG_KMS(
"%s: switching to 1024x768\n",
469 ok &= ns2501_writeb(dvo, 0x37, 0x44);
513 bool restore =
false;
517 DRM_DEBUG_KMS(
"%s: Trying set the dpms of the DVO to %i\n",
535 ns2501_writeb(dvo, 0x34,
536 enable ? 0x03 : 0x00);
538 ns2501_writeb(dvo, 0x35,
539 enable ? 0xff : 0x00);
558 DRM_LOG_KMS(
"NS2501_FREQ_LO: 0x%02x\n", val);
560 DRM_LOG_KMS(
"NS2501_FREQ_HI: 0x%02x\n", val);
562 DRM_LOG_KMS(
"NS2501_REG8: 0x%02x\n", val);
564 DRM_LOG_KMS(
"NS2501_REG9: 0x%02x\n", val);
566 DRM_LOG_KMS(
"NS2501_REGC: 0x%02x\n", val);
581 .detect = ns2501_detect,
582 .mode_valid = ns2501_mode_valid,
583 .mode_set = ns2501_mode_set,
585 .get_hw_state = ns2501_get_hw_state,
586 .dump_regs = ns2501_dump_regs,
587 .destroy = ns2501_destroy,