Linux Kernel
3.7.1
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#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <linux/platform_data/usb-ehci-mxc.h>
Go to the source code of this file.
Macros | |
#define | MXC_OTG_OFFSET 0 |
#define | MXC_H1_OFFSET 0x200 |
#define | MXC_H2_OFFSET 0x400 |
#define | MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ |
#define | MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ |
#define | MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ |
#define | MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ |
#define | MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ |
#define | MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */ |
#define | MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ |
#define | MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */ |
#define | MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ |
#define | MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */ |
#define | MXC_H2_UCTRL_H2UIE_BIT (1 << 8) |
#define | MXC_H2_UCTRL_H2WIE_BIT (1 << 7) |
#define | MXC_H2_UCTRL_H2PM_BIT (1 << 4) |
#define | MXC_USBCMD_OFFSET 0x140 |
#define | MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */ |
Functions | |
int | mx51_initialize_usb_hw (int port, unsigned int flags) |
#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ |
Definition at line 37 of file ehci-imx5.c.
#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */ |
Definition at line 36 of file ehci-imx5.c.
#define MXC_H1_OFFSET 0x200 |
Definition at line 23 of file ehci-imx5.c.
#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ |
Definition at line 31 of file ehci-imx5.c.
Definition at line 29 of file ehci-imx5.c.
Definition at line 30 of file ehci-imx5.c.
#define MXC_H2_OFFSET 0x400 |
Definition at line 24 of file ehci-imx5.c.
#define MXC_H2_UCTRL_H2PM_BIT (1 << 4) |
Definition at line 43 of file ehci-imx5.c.
#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) |
Definition at line 41 of file ehci-imx5.c.
#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) |
Definition at line 42 of file ehci-imx5.c.
#define MXC_OTG_OFFSET 0 |
Definition at line 22 of file ehci-imx5.c.
#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ |
Definition at line 35 of file ehci-imx5.c.
#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */ |
Definition at line 34 of file ehci-imx5.c.
Definition at line 38 of file ehci-imx5.c.
Definition at line 28 of file ehci-imx5.c.
Definition at line 27 of file ehci-imx5.c.
#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */ |
Definition at line 48 of file ehci-imx5.c.
#define MXC_USBCMD_OFFSET 0x140 |
Definition at line 45 of file ehci-imx5.c.
Definition at line 50 of file ehci-imx5.c.