51 nva3_copy_sclass[] = {
71 *pobject = nv_object(priv);
82 .ctor = nva3_copy_context_ctor,
96 static const struct nouveau_enum nva3_copy_isr_error_name[] = {
97 { 0x0001,
"ILLEGAL_MTHD" },
98 { 0x0002,
"INVALID_ENUM" },
99 { 0x0003,
"INVALID_BITFIELD" },
110 u32 dispatch = nv_rd32(priv, 0x10401c);
111 u32 stat = nv_rd32(priv, 0x104008) & dispatch & ~(dispatch >> 16);
112 u64 inst = nv_rd32(priv, 0x104050) & 0x3fffffff;
113 u32 ssta = nv_rd32(priv, 0x104040) & 0x0000ffff;
114 u32 addr = nv_rd32(priv, 0x104040) >> 16;
115 u32 mthd = (addr & 0x07ff) << 2;
116 u32 subc = (addr & 0x3800) >> 11;
117 u32 data = nv_rd32(priv, 0x104044);
121 chid = pfifo->
chid(pfifo, engctx);
123 if (stat & 0x00000040) {
126 printk(
"] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n",
127 chid, inst << 12, subc, mthd, data);
128 nv_wr32(priv, 0x104004, 0x00000040);
133 nv_error(priv,
"unhandled intr 0x%08x\n", stat);
134 nv_wr32(priv, 0x104004, stat);
153 bool enable = (nv_device(parent)->chipset != 0xaf);
158 *pobject = nv_object(priv);
162 nv_subdev(priv)->unit = 0x00802000;
163 nv_subdev(priv)->intr = nva3_copy_intr;
164 nv_engine(priv)->cclass = &nva3_copy_cclass;
165 nv_engine(priv)->sclass = nva3_copy_sclass;
166 nv_engine(priv)->tlb_flush = nva3_copy_tlb_flush;
181 nv_wr32(priv, 0x104014, 0xffffffff);
184 nv_wr32(priv, 0x1041c0, 0x01000000);
185 for (i = 0; i <
sizeof(nva3_pcopy_data) / 4; i++)
186 nv_wr32(priv, 0x1041c4, nva3_pcopy_data[i]);
188 nv_wr32(priv, 0x104180, 0x01000000);
189 for (i = 0; i <
sizeof(nva3_pcopy_code) / 4; i++) {
191 nv_wr32(priv, 0x104188, i >> 6);
192 nv_wr32(priv, 0x104184, nva3_pcopy_code[i]);
196 nv_wr32(priv, 0x10410c, 0x00000000);
197 nv_wr32(priv, 0x104104, 0x00000000);
198 nv_wr32(priv, 0x104100, 0x00000002);
207 nv_mask(priv, 0x104048, 0x00000003, 0x00000000);
208 nv_wr32(priv, 0x104014, 0xffffffff);
217 .ctor = nva3_copy_ctor,
219 .init = nva3_copy_init,
220 .fini = nva3_copy_fini,