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nv50.c
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1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 
25 #include <core/os.h>
26 #include <core/class.h>
27 #include <core/handle.h>
28 #include <core/engctx.h>
29 #include <core/enum.h>
30 
31 #include <subdev/fb.h>
32 #include <subdev/vm.h>
33 #include <subdev/timer.h>
34 
35 #include <engine/fifo.h>
36 #include <engine/graph.h>
37 
38 #include "nv50.h"
39 
40 struct nv50_graph_priv {
41  struct nouveau_graph base;
42  spinlock_t lock;
43  u32 size;
44 };
45 
46 struct nv50_graph_chan {
47  struct nouveau_graph_chan base;
48 };
49 
50 /*******************************************************************************
51  * Graphics object classes
52  ******************************************************************************/
53 
54 static int
55 nv50_graph_object_ctor(struct nouveau_object *parent,
56  struct nouveau_object *engine,
57  struct nouveau_oclass *oclass, void *data, u32 size,
58  struct nouveau_object **pobject)
59 {
60  struct nouveau_gpuobj *obj;
61  int ret;
62 
63  ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
64  16, 16, 0, &obj);
65  *pobject = nv_object(obj);
66  if (ret)
67  return ret;
68 
69  nv_wo32(obj, 0x00, nv_mclass(obj));
70  nv_wo32(obj, 0x04, 0x00000000);
71  nv_wo32(obj, 0x08, 0x00000000);
72  nv_wo32(obj, 0x0c, 0x00000000);
73  return 0;
74 }
75 
76 static struct nouveau_ofuncs
77 nv50_graph_ofuncs = {
78  .ctor = nv50_graph_object_ctor,
79  .dtor = _nouveau_gpuobj_dtor,
80  .init = _nouveau_gpuobj_init,
81  .fini = _nouveau_gpuobj_fini,
82  .rd32 = _nouveau_gpuobj_rd32,
83  .wr32 = _nouveau_gpuobj_wr32,
84 };
85 
86 static struct nouveau_oclass
87 nv50_graph_sclass[] = {
88  { 0x0030, &nv50_graph_ofuncs },
89  { 0x502d, &nv50_graph_ofuncs },
90  { 0x5039, &nv50_graph_ofuncs },
91  { 0x5097, &nv50_graph_ofuncs },
92  { 0x50c0, &nv50_graph_ofuncs },
93  {}
94 };
95 
96 static struct nouveau_oclass
97 nv84_graph_sclass[] = {
98  { 0x0030, &nv50_graph_ofuncs },
99  { 0x502d, &nv50_graph_ofuncs },
100  { 0x5039, &nv50_graph_ofuncs },
101  { 0x50c0, &nv50_graph_ofuncs },
102  { 0x8297, &nv50_graph_ofuncs },
103  {}
104 };
105 
106 static struct nouveau_oclass
107 nva0_graph_sclass[] = {
108  { 0x0030, &nv50_graph_ofuncs },
109  { 0x502d, &nv50_graph_ofuncs },
110  { 0x5039, &nv50_graph_ofuncs },
111  { 0x50c0, &nv50_graph_ofuncs },
112  { 0x8397, &nv50_graph_ofuncs },
113  {}
114 };
115 
116 static struct nouveau_oclass
117 nva3_graph_sclass[] = {
118  { 0x0030, &nv50_graph_ofuncs },
119  { 0x502d, &nv50_graph_ofuncs },
120  { 0x5039, &nv50_graph_ofuncs },
121  { 0x50c0, &nv50_graph_ofuncs },
122  { 0x8597, &nv50_graph_ofuncs },
123  { 0x85c0, &nv50_graph_ofuncs },
124  {}
125 };
126 
127 static struct nouveau_oclass
128 nvaf_graph_sclass[] = {
129  { 0x0030, &nv50_graph_ofuncs },
130  { 0x502d, &nv50_graph_ofuncs },
131  { 0x5039, &nv50_graph_ofuncs },
132  { 0x50c0, &nv50_graph_ofuncs },
133  { 0x85c0, &nv50_graph_ofuncs },
134  { 0x8697, &nv50_graph_ofuncs },
135  {}
136 };
137 
138 /*******************************************************************************
139  * PGRAPH context
140  ******************************************************************************/
141 
142 static int
143 nv50_graph_context_ctor(struct nouveau_object *parent,
144  struct nouveau_object *engine,
145  struct nouveau_oclass *oclass, void *data, u32 size,
146  struct nouveau_object **pobject)
147 {
148  struct nv50_graph_priv *priv = (void *)engine;
149  struct nv50_graph_chan *chan;
150  int ret;
151 
152  ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
153  priv->size, 0,
154  NVOBJ_FLAG_ZERO_ALLOC, &chan);
155  *pobject = nv_object(chan);
156  if (ret)
157  return ret;
158 
159  nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan));
160  return 0;
161 }
162 
163 static struct nouveau_oclass
164 nv50_graph_cclass = {
165  .handle = NV_ENGCTX(GR, 0x50),
166  .ofuncs = &(struct nouveau_ofuncs) {
167  .ctor = nv50_graph_context_ctor,
168  .dtor = _nouveau_graph_context_dtor,
169  .init = _nouveau_graph_context_init,
170  .fini = _nouveau_graph_context_fini,
171  .rd32 = _nouveau_graph_context_rd32,
172  .wr32 = _nouveau_graph_context_wr32,
173  },
174 };
175 
176 /*******************************************************************************
177  * PGRAPH engine/subdev functions
178  ******************************************************************************/
179 
180 static int
181 nv50_graph_tlb_flush(struct nouveau_engine *engine)
182 {
183  nv50_vm_flush_engine(&engine->base, 0x00);
184  return 0;
185 }
186 
187 static int
188 nv84_graph_tlb_flush(struct nouveau_engine *engine)
189 {
190  struct nouveau_timer *ptimer = nouveau_timer(engine);
191  struct nv50_graph_priv *priv = (void *)engine;
192  bool idle, timeout = false;
193  unsigned long flags;
194  u64 start;
195  u32 tmp;
196 
197  spin_lock_irqsave(&priv->lock, flags);
198  nv_mask(priv, 0x400500, 0x00000001, 0x00000000);
199 
200  start = ptimer->read(ptimer);
201  do {
202  idle = true;
203 
204  for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) {
205  if ((tmp & 7) == 1)
206  idle = false;
207  }
208 
209  for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) {
210  if ((tmp & 7) == 1)
211  idle = false;
212  }
213 
214  for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) {
215  if ((tmp & 7) == 1)
216  idle = false;
217  }
218  } while (!idle &&
219  !(timeout = ptimer->read(ptimer) - start > 2000000000));
220 
221  if (timeout) {
222  nv_error(priv, "PGRAPH TLB flush idle timeout fail: "
223  "0x%08x 0x%08x 0x%08x 0x%08x\n",
224  nv_rd32(priv, 0x400700), nv_rd32(priv, 0x400380),
225  nv_rd32(priv, 0x400384), nv_rd32(priv, 0x400388));
226  }
227 
228  nv50_vm_flush_engine(&engine->base, 0x00);
229 
230  nv_mask(priv, 0x400500, 0x00000001, 0x00000001);
231  spin_unlock_irqrestore(&priv->lock, flags);
232  return timeout ? -EBUSY : 0;
233 }
234 
235 static const struct nouveau_enum nv50_mp_exec_error_names[] = {
236  { 3, "STACK_UNDERFLOW", NULL },
237  { 4, "QUADON_ACTIVE", NULL },
238  { 8, "TIMEOUT", NULL },
239  { 0x10, "INVALID_OPCODE", NULL },
240  { 0x40, "BREAKPOINT", NULL },
241  {}
242 };
243 
244 static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
245  { 0x00000001, "NOTIFY" },
246  { 0x00000002, "IN" },
247  { 0x00000004, "OUT" },
248  {}
249 };
250 
251 static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
252  { 0x00000001, "FAULT" },
253  {}
254 };
255 
256 static const struct nouveau_bitfield nv50_graph_trap_strmout[] = {
257  { 0x00000001, "FAULT" },
258  {}
259 };
260 
261 static const struct nouveau_bitfield nv50_graph_trap_ccache[] = {
262  { 0x00000001, "FAULT" },
263  {}
264 };
265 
266 /* There must be a *lot* of these. Will take some time to gather them up. */
267 const struct nouveau_enum nv50_data_error_names[] = {
268  { 0x00000003, "INVALID_OPERATION", NULL },
269  { 0x00000004, "INVALID_VALUE", NULL },
270  { 0x00000005, "INVALID_ENUM", NULL },
271  { 0x00000008, "INVALID_OBJECT", NULL },
272  { 0x00000009, "READ_ONLY_OBJECT", NULL },
273  { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
274  { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
275  { 0x0000000c, "INVALID_BITFIELD", NULL },
276  { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
277  { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
278  { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
279  { 0x00000010, "RT_DOUBLE_BIND", NULL },
280  { 0x00000011, "RT_TYPES_MISMATCH", NULL },
281  { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
282  { 0x00000015, "FP_TOO_FEW_REGS", NULL },
283  { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
284  { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
285  { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
286  { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
287  { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
288  { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
289  { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
290  { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
291  { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
292  { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
293  { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
294  { 0x00000024, "VP_ZERO_INPUTS", NULL },
295  { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
296  { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
297  { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
298  { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
299  { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
300  { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
301  { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
302  { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
303  { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
304  { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
305  { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
306  { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
307  { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
308  { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
309  { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
310  {}
311 };
312 
313 static const struct nouveau_bitfield nv50_graph_intr_name[] = {
314  { 0x00000001, "NOTIFY" },
315  { 0x00000002, "COMPUTE_QUERY" },
316  { 0x00000010, "ILLEGAL_MTHD" },
317  { 0x00000020, "ILLEGAL_CLASS" },
318  { 0x00000040, "DOUBLE_NOTIFY" },
319  { 0x00001000, "CONTEXT_SWITCH" },
320  { 0x00010000, "BUFFER_NOTIFY" },
321  { 0x00100000, "DATA_ERROR" },
322  { 0x00200000, "TRAP" },
323  { 0x01000000, "SINGLE_STEP" },
324  {}
325 };
326 
327 static void
328 nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
329 {
330  u32 units = nv_rd32(priv, 0x1540);
331  u32 addr, mp10, status, pc, oplow, ophigh;
332  int i;
333  int mps = 0;
334  for (i = 0; i < 4; i++) {
335  if (!(units & 1 << (i+24)))
336  continue;
337  if (nv_device(priv)->chipset < 0xa0)
338  addr = 0x408200 + (tpid << 12) + (i << 7);
339  else
340  addr = 0x408100 + (tpid << 11) + (i << 7);
341  mp10 = nv_rd32(priv, addr + 0x10);
342  status = nv_rd32(priv, addr + 0x14);
343  if (!status)
344  continue;
345  if (display) {
346  nv_rd32(priv, addr + 0x20);
347  pc = nv_rd32(priv, addr + 0x24);
348  oplow = nv_rd32(priv, addr + 0x70);
349  ophigh = nv_rd32(priv, addr + 0x74);
350  nv_error(priv, "TRAP_MP_EXEC - "
351  "TP %d MP %d: ", tpid, i);
352  nouveau_enum_print(nv50_mp_exec_error_names, status);
353  printk(" at %06x warp %d, opcode %08x %08x\n",
354  pc&0xffffff, pc >> 24,
355  oplow, ophigh);
356  }
357  nv_wr32(priv, addr + 0x10, mp10);
358  nv_wr32(priv, addr + 0x14, 0);
359  mps++;
360  }
361  if (!mps && display)
362  nv_error(priv, "TRAP_MP_EXEC - TP %d: "
363  "No MPs claiming errors?\n", tpid);
364 }
365 
366 static void
367 nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
368  u32 ustatus_new, int display, const char *name)
369 {
370  int tps = 0;
371  u32 units = nv_rd32(priv, 0x1540);
372  int i, r;
373  u32 ustatus_addr, ustatus;
374  for (i = 0; i < 16; i++) {
375  if (!(units & (1 << i)))
376  continue;
377  if (nv_device(priv)->chipset < 0xa0)
378  ustatus_addr = ustatus_old + (i << 12);
379  else
380  ustatus_addr = ustatus_new + (i << 11);
381  ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff;
382  if (!ustatus)
383  continue;
384  tps++;
385  switch (type) {
386  case 6: /* texture error... unknown for now */
387  if (display) {
388  nv_error(priv, "magic set %d:\n", i);
389  for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
390  nv_error(priv, "\t0x%08x: 0x%08x\n", r,
391  nv_rd32(priv, r));
392  }
393  break;
394  case 7: /* MP error */
395  if (ustatus & 0x04030000) {
396  nv50_priv_mp_trap(priv, i, display);
397  ustatus &= ~0x04030000;
398  }
399  break;
400  case 8: /* TPDMA error */
401  {
402  u32 e0c = nv_rd32(priv, ustatus_addr + 4);
403  u32 e10 = nv_rd32(priv, ustatus_addr + 8);
404  u32 e14 = nv_rd32(priv, ustatus_addr + 0xc);
405  u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
406  u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
407  u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
408  u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
409  /* 2d engine destination */
410  if (ustatus & 0x00000010) {
411  if (display) {
412  nv_error(priv, "TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
413  i, e14, e10);
414  nv_error(priv, "TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
415  i, e0c, e18, e1c, e20, e24);
416  }
417  ustatus &= ~0x00000010;
418  }
419  /* Render target */
420  if (ustatus & 0x00000040) {
421  if (display) {
422  nv_error(priv, "TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
423  i, e14, e10);
424  nv_error(priv, "TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
425  i, e0c, e18, e1c, e20, e24);
426  }
427  ustatus &= ~0x00000040;
428  }
429  /* CUDA memory: l[], g[] or stack. */
430  if (ustatus & 0x00000080) {
431  if (display) {
432  if (e18 & 0x80000000) {
433  /* g[] read fault? */
434  nv_error(priv, "TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
435  i, e14, e10 | ((e18 >> 24) & 0x1f));
436  e18 &= ~0x1f000000;
437  } else if (e18 & 0xc) {
438  /* g[] write fault? */
439  nv_error(priv, "TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
440  i, e14, e10 | ((e18 >> 7) & 0x1f));
441  e18 &= ~0x00000f80;
442  } else {
443  nv_error(priv, "TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
444  i, e14, e10);
445  }
446  nv_error(priv, "TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
447  i, e0c, e18, e1c, e20, e24);
448  }
449  ustatus &= ~0x00000080;
450  }
451  }
452  break;
453  }
454  if (ustatus) {
455  if (display)
456  nv_info(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
457  }
458  nv_wr32(priv, ustatus_addr, 0xc0000000);
459  }
460 
461  if (!tps && display)
462  nv_info(priv, "%s - No TPs claiming errors?\n", name);
463 }
464 
465 static int
466 nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
467  int chid, u64 inst)
468 {
469  u32 status = nv_rd32(priv, 0x400108);
470  u32 ustatus;
471 
472  if (!status && display) {
473  nv_error(priv, "TRAP: no units reporting traps?\n");
474  return 1;
475  }
476 
477  /* DISPATCH: Relays commands to other units and handles NOTIFY,
478  * COND, QUERY. If you get a trap from it, the command is still stuck
479  * in DISPATCH and you need to do something about it. */
480  if (status & 0x001) {
481  ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff;
482  if (!ustatus && display) {
483  nv_error(priv, "TRAP_DISPATCH - no ustatus?\n");
484  }
485 
486  nv_wr32(priv, 0x400500, 0x00000000);
487 
488  /* Known to be triggered by screwed up NOTIFY and COND... */
489  if (ustatus & 0x00000001) {
490  u32 addr = nv_rd32(priv, 0x400808);
491  u32 subc = (addr & 0x00070000) >> 16;
492  u32 mthd = (addr & 0x00001ffc);
493  u32 datal = nv_rd32(priv, 0x40080c);
494  u32 datah = nv_rd32(priv, 0x400810);
495  u32 class = nv_rd32(priv, 0x400814);
496  u32 r848 = nv_rd32(priv, 0x400848);
497 
498  nv_error(priv, "TRAP DISPATCH_FAULT\n");
499  if (display && (addr & 0x80000000)) {
500  nv_error(priv, "ch %d [0x%010llx] "
501  "subc %d class 0x%04x mthd 0x%04x "
502  "data 0x%08x%08x "
503  "400808 0x%08x 400848 0x%08x\n",
504  chid, inst, subc, class, mthd, datah,
505  datal, addr, r848);
506  } else
507  if (display) {
508  nv_error(priv, "no stuck command?\n");
509  }
510 
511  nv_wr32(priv, 0x400808, 0);
512  nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3);
513  nv_wr32(priv, 0x400848, 0);
514  ustatus &= ~0x00000001;
515  }
516 
517  if (ustatus & 0x00000002) {
518  u32 addr = nv_rd32(priv, 0x40084c);
519  u32 subc = (addr & 0x00070000) >> 16;
520  u32 mthd = (addr & 0x00001ffc);
521  u32 data = nv_rd32(priv, 0x40085c);
522  u32 class = nv_rd32(priv, 0x400814);
523 
524  nv_error(priv, "TRAP DISPATCH_QUERY\n");
525  if (display && (addr & 0x80000000)) {
526  nv_error(priv, "ch %d [0x%010llx] "
527  "subc %d class 0x%04x mthd 0x%04x "
528  "data 0x%08x 40084c 0x%08x\n",
529  chid, inst, subc, class, mthd,
530  data, addr);
531  } else
532  if (display) {
533  nv_error(priv, "no stuck command?\n");
534  }
535 
536  nv_wr32(priv, 0x40084c, 0);
537  ustatus &= ~0x00000002;
538  }
539 
540  if (ustatus && display) {
541  nv_error(priv, "TRAP_DISPATCH (unknown "
542  "0x%08x)\n", ustatus);
543  }
544 
545  nv_wr32(priv, 0x400804, 0xc0000000);
546  nv_wr32(priv, 0x400108, 0x001);
547  status &= ~0x001;
548  if (!status)
549  return 0;
550  }
551 
552  /* M2MF: Memory to memory copy engine. */
553  if (status & 0x002) {
554  u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff;
555  if (display) {
556  nv_error(priv, "TRAP_M2MF");
557  nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
558  printk("\n");
559  nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
560  nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
561  nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810));
562 
563  }
564 
565  /* No sane way found yet -- just reset the bugger. */
566  nv_wr32(priv, 0x400040, 2);
567  nv_wr32(priv, 0x400040, 0);
568  nv_wr32(priv, 0x406800, 0xc0000000);
569  nv_wr32(priv, 0x400108, 0x002);
570  status &= ~0x002;
571  }
572 
573  /* VFETCH: Fetches data from vertex buffers. */
574  if (status & 0x004) {
575  u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff;
576  if (display) {
577  nv_error(priv, "TRAP_VFETCH");
578  nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
579  printk("\n");
580  nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
581  nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
582  nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10));
583  }
584 
585  nv_wr32(priv, 0x400c04, 0xc0000000);
586  nv_wr32(priv, 0x400108, 0x004);
587  status &= ~0x004;
588  }
589 
590  /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
591  if (status & 0x008) {
592  ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff;
593  if (display) {
594  nv_error(priv, "TRAP_STRMOUT");
595  nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
596  printk("\n");
597  nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
598  nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
599  nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810));
600 
601  }
602 
603  /* No sane way found yet -- just reset the bugger. */
604  nv_wr32(priv, 0x400040, 0x80);
605  nv_wr32(priv, 0x400040, 0);
606  nv_wr32(priv, 0x401800, 0xc0000000);
607  nv_wr32(priv, 0x400108, 0x008);
608  status &= ~0x008;
609  }
610 
611  /* CCACHE: Handles code and c[] caches and fills them. */
612  if (status & 0x010) {
613  ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff;
614  if (display) {
615  nv_error(priv, "TRAP_CCACHE");
616  nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
617  printk("\n");
618  nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
619  " %08x %08x %08x\n",
620  nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004),
621  nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c),
622  nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014),
623  nv_rd32(priv, 0x40501c));
624 
625  }
626 
627  nv_wr32(priv, 0x405018, 0xc0000000);
628  nv_wr32(priv, 0x400108, 0x010);
629  status &= ~0x010;
630  }
631 
632  /* Unknown, not seen yet... 0x402000 is the only trap status reg
633  * remaining, so try to handle it anyway. Perhaps related to that
634  * unknown DMA slot on tesla? */
635  if (status & 0x20) {
636  ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff;
637  if (display)
638  nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus);
639  nv_wr32(priv, 0x402000, 0xc0000000);
640  /* no status modifiction on purpose */
641  }
642 
643  /* TEXTURE: CUDA texturing units */
644  if (status & 0x040) {
645  nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display,
646  "TRAP_TEXTURE");
647  nv_wr32(priv, 0x400108, 0x040);
648  status &= ~0x040;
649  }
650 
651  /* MP: CUDA execution engines. */
652  if (status & 0x080) {
653  nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display,
654  "TRAP_MP");
655  nv_wr32(priv, 0x400108, 0x080);
656  status &= ~0x080;
657  }
658 
659  /* TPDMA: Handles TP-initiated uncached memory accesses:
660  * l[], g[], stack, 2d surfaces, render targets. */
661  if (status & 0x100) {
662  nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display,
663  "TRAP_TPDMA");
664  nv_wr32(priv, 0x400108, 0x100);
665  status &= ~0x100;
666  }
667 
668  if (status) {
669  if (display)
670  nv_error(priv, "TRAP: unknown 0x%08x\n", status);
671  nv_wr32(priv, 0x400108, status);
672  }
673 
674  return 1;
675 }
676 
677 static void
678 nv50_graph_intr(struct nouveau_subdev *subdev)
679 {
680  struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
681  struct nouveau_engine *engine = nv_engine(subdev);
682  struct nouveau_object *engctx;
683  struct nouveau_handle *handle = NULL;
684  struct nv50_graph_priv *priv = (void *)subdev;
685  u32 stat = nv_rd32(priv, 0x400100);
686  u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff;
687  u32 addr = nv_rd32(priv, 0x400704);
688  u32 subc = (addr & 0x00070000) >> 16;
689  u32 mthd = (addr & 0x00001ffc);
690  u32 data = nv_rd32(priv, 0x400708);
691  u32 class = nv_rd32(priv, 0x400814);
692  u32 show = stat;
693  int chid;
694 
695  engctx = nouveau_engctx_get(engine, inst);
696  chid = pfifo->chid(pfifo, engctx);
697 
698  if (stat & 0x00000010) {
699  handle = nouveau_handle_get_class(engctx, class);
700  if (handle && !nv_call(handle->object, mthd, data))
701  show &= ~0x00000010;
702  nouveau_handle_put(handle);
703  }
704 
705  if (show & 0x00100000) {
706  u32 ecode = nv_rd32(priv, 0x400110);
707  nv_error(priv, "DATA_ERROR ");
708  nouveau_enum_print(nv50_data_error_names, ecode);
709  printk("\n");
710  }
711 
712  if (stat & 0x00200000) {
713  if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12))
714  show &= ~0x00200000;
715  }
716 
717  nv_wr32(priv, 0x400100, stat);
718  nv_wr32(priv, 0x400500, 0x00010001);
719 
720  if (show) {
721  nv_info(priv, "");
722  nouveau_bitfield_print(nv50_graph_intr_name, show);
723  printk("\n");
724  nv_error(priv, "ch %d [0x%010llx] subc %d class 0x%04x "
725  "mthd 0x%04x data 0x%08x\n",
726  chid, (u64)inst << 12, subc, class, mthd, data);
727  nv50_fb_trap(nouveau_fb(priv), 1);
728  }
729 
730  if (nv_rd32(priv, 0x400824) & (1 << 31))
731  nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31));
732 
733  nouveau_engctx_put(engctx);
734 }
735 
736 static int
737 nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
738  struct nouveau_oclass *oclass, void *data, u32 size,
739  struct nouveau_object **pobject)
740 {
741  struct nv50_graph_priv *priv;
742  int ret;
743 
744  ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
745  *pobject = nv_object(priv);
746  if (ret)
747  return ret;
748 
749  nv_subdev(priv)->unit = 0x00201000;
750  nv_subdev(priv)->intr = nv50_graph_intr;
751  nv_engine(priv)->cclass = &nv50_graph_cclass;
752 
753  switch (nv_device(priv)->chipset) {
754  case 0x50:
755  nv_engine(priv)->sclass = nv50_graph_sclass;
756  break;
757  case 0x84:
758  case 0x86:
759  case 0x92:
760  case 0x94:
761  case 0x96:
762  case 0x98:
763  nv_engine(priv)->sclass = nv84_graph_sclass;
764  break;
765  case 0xa0:
766  case 0xaa:
767  case 0xac:
768  nv_engine(priv)->sclass = nva0_graph_sclass;
769  break;
770  case 0xa3:
771  case 0xa5:
772  case 0xa8:
773  nv_engine(priv)->sclass = nva3_graph_sclass;
774  break;
775  case 0xaf:
776  nv_engine(priv)->sclass = nvaf_graph_sclass;
777  break;
778 
779  };
780 
781  if (nv_device(priv)->chipset == 0x50 ||
782  nv_device(priv)->chipset == 0xac)
783  nv_engine(priv)->tlb_flush = nv50_graph_tlb_flush;
784  else
785  nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush;
786 
787  spin_lock_init(&priv->lock);
788  return 0;
789 }
790 
791 static int
792 nv50_graph_init(struct nouveau_object *object)
793 {
794  struct nv50_graph_priv *priv = (void *)object;
795  int ret, units, i;
796 
797  ret = nouveau_graph_init(&priv->base);
798  if (ret)
799  return ret;
800 
801  /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */
802  nv_wr32(priv, 0x40008c, 0x00000004);
803 
804  /* reset/enable traps and interrupts */
805  nv_wr32(priv, 0x400804, 0xc0000000);
806  nv_wr32(priv, 0x406800, 0xc0000000);
807  nv_wr32(priv, 0x400c04, 0xc0000000);
808  nv_wr32(priv, 0x401800, 0xc0000000);
809  nv_wr32(priv, 0x405018, 0xc0000000);
810  nv_wr32(priv, 0x402000, 0xc0000000);
811 
812  units = nv_rd32(priv, 0x001540);
813  for (i = 0; i < 16; i++) {
814  if (!(units & (1 << i)))
815  continue;
816 
817  if (nv_device(priv)->chipset < 0xa0) {
818  nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000);
819  nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000);
820  nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000);
821  } else {
822  nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000);
823  nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000);
824  nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000);
825  }
826  }
827 
828  nv_wr32(priv, 0x400108, 0xffffffff);
829  nv_wr32(priv, 0x400138, 0xffffffff);
830  nv_wr32(priv, 0x400100, 0xffffffff);
831  nv_wr32(priv, 0x40013c, 0xffffffff);
832  nv_wr32(priv, 0x400500, 0x00010001);
833 
834  /* upload context program, initialise ctxctl defaults */
835  ret = nv50_grctx_init(nv_device(priv), &priv->size);
836  if (ret)
837  return ret;
838 
839  nv_wr32(priv, 0x400824, 0x00000000);
840  nv_wr32(priv, 0x400828, 0x00000000);
841  nv_wr32(priv, 0x40082c, 0x00000000);
842  nv_wr32(priv, 0x400830, 0x00000000);
843  nv_wr32(priv, 0x400724, 0x00000000);
844  nv_wr32(priv, 0x40032c, 0x00000000);
845  nv_wr32(priv, 0x400320, 4); /* CTXCTL_CMD = NEWCTXDMA */
846 
847  /* some unknown zcull magic */
848  switch (nv_device(priv)->chipset & 0xf0) {
849  case 0x50:
850  case 0x80:
851  case 0x90:
852  nv_wr32(priv, 0x402ca8, 0x00000800);
853  break;
854  case 0xa0:
855  default:
856  nv_wr32(priv, 0x402cc0, 0x00000000);
857  if (nv_device(priv)->chipset == 0xa0 ||
858  nv_device(priv)->chipset == 0xaa ||
859  nv_device(priv)->chipset == 0xac) {
860  nv_wr32(priv, 0x402ca8, 0x00000802);
861  } else {
862  nv_wr32(priv, 0x402cc0, 0x00000000);
863  nv_wr32(priv, 0x402ca8, 0x00000002);
864  }
865 
866  break;
867  }
868 
869  /* zero out zcull regions */
870  for (i = 0; i < 8; i++) {
871  nv_wr32(priv, 0x402c20 + (i * 8), 0x00000000);
872  nv_wr32(priv, 0x402c24 + (i * 8), 0x00000000);
873  nv_wr32(priv, 0x402c28 + (i * 8), 0x00000000);
874  nv_wr32(priv, 0x402c2c + (i * 8), 0x00000000);
875  }
876  return 0;
877 }
878 
879 struct nouveau_oclass
880 nv50_graph_oclass = {
881  .handle = NV_ENGINE(GR, 0x50),
882  .ofuncs = &(struct nouveau_ofuncs) {
883  .ctor = nv50_graph_ctor,
884  .dtor = _nouveau_graph_dtor,
885  .init = nv50_graph_init,
886  .fini = _nouveau_graph_fini,
887  },
888 };
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